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CSE/EE 462 L12 ROM and PLA First Look.1
CSE/EE 462 L12 ROM and PLA First Look.1
CSE/EE 462 L12 ROM and PLA First Look.1
CSE/EE 462 L12 ROM and PLA First Look.1
CSE/EE 462 L12 ROM and PLA First Look.1
CSE/EE 462 L12 ROM and PLA First Look.1
CSE/EE 462 L12 ROM and PLA First Look.1
CSE/EE 462 L12 ROM and PLA First Look.1
CSE/EE 462 L12 ROM and PLA First Look.1
CSE/EE 462 L12 ROM and PLA First Look.1
CSE/EE 462 L12 ROM and PLA First Look.1
CSE/EE 462 L12 ROM and PLA First Look.1
CSE/EE 462 L12 ROM and PLA First Look.1
CSE/EE 462 L12 ROM and PLA First Look.1
CSE/EE 462 L12 ROM and PLA First Look.1
CSE/EE 462 L12 ROM and PLA First Look.1
CSE/EE 462 L12 ROM and PLA First Look.1
CSE/EE 462 L12 ROM and PLA First Look.1
CSE/EE 462 L12 ROM and PLA First Look.1
CSE/EE 462 L12 ROM and PLA First Look.1
CSE/EE 462 L12 ROM and PLA First Look.1
CSE/EE 462 L12 ROM and PLA First Look.1
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CSE/EE 462 L12 ROM and PLA First Look.1

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  • Other handouts In class quiz Course information sheet To handout next time Course schedule with due dates HW#1 Project Description
  • Transcript

    • 1. CSE/EE 462: VLSI Design Fall 2006 A First Look at ROMs and PLAs Jay Brockman [Adapted from Mary Jane Irwin and Vijay Narananan, CSE Penn State adaptation of Rabaey’s Digital Integrated Circuits , © 2002, J. Rabaey et al.]
    • 2. Array-Structured Memory Architecture
      • All cells on selected row sensed simultaneously
      column decode sense amplifiers row decode row address column address Din/Dout
    • 3. MOS NOR ROM Cell Array WL [0] BL [0] WL [1] WL [2] WL [3] V DD BL [1] Pull-up devices BL [2] BL [3]
    • 4. MOS NOR ROM Layer Assignments
      • Poly and diffusion is patterned for all cells
      • Use contacts to connect cells with zeros to metal columns
      WL [0] GND BL [0] WL [1] WL [2] WL [3] V DD BL [1] Pull-up devices BL [2] BL [3] GND mirroring alternate rows saves area
    • 5. Contact Programmable NOR ROM Layout + =
    • 6. Row Decoder WL [0] BL [0] WL [1] WL [2] WL [3] V DD BL [1] Pull-up devices BL [2] BL [3] A 1 A 0 A 1 A 0 A 1 A 0 A 1 A 0
    • 7. Row Decoder WL [0] BL [0] WL [1] WL [2] WL [3] V DD BL [1] Pull-up devices BL [2] BL [3] NOR A 1 A 0 NOR NOR NOR A 1 A 0 A 0 look familiar?
    • 8. Row Decoders Collection of 2 M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder
    • 9. 4-input pass-transistor based column decoder Advantages: speed ( t pd does not add to overall memory access time) Only one extra transistor in signal path Disadvantage: Large transistor count 2-input NOR decoder A 0 S 0 BL 0 BL 1 BL 2 BL 3 A 1 S 1 S 2 S 3 D
    • 10. Non-Volatile Memories The Floating-gate transistor (FAMOS) Floating gate Source Substrate Gate Drain n + n +_ p t ox t ox Device cross-section Schematic symbol G S D
    • 11. MOS NAND ROM All word lines high by default with exception of selected row WL [0] WL [1] WL [2] WL [3] V DD Pull-up devices BL [3] BL [2] BL [1] BL [0]
    • 12. NAND Flash Memory Unit Cell Word line(poly) Source line (Diff. Layer) Courtesy Toshiba
    • 13. NAND Flash Memory Courtesy Toshiba Word lines Select transistor Bit line contact Source line contact Active area STI
    • 14. 6-transistor CMOS SRAM Cell WL BL V DD M 5 M 6 M 4 M 1 M 2 M 3 BL Q Q
    • 15. 6T-SRAM — Layout V DD GND Q Q WL BL BL M1 M3 M4 M2 M5 M6
    • 16. 1-Transistor DRAM Cell Write: C S is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance Voltage swing is small; typically around 250 mV.  V BL V PRE – V BIT V PRE – C S C S C BL + ------------ = = V
    • 17. 1-T DRAM Cell Uses Polysilicon-Diffusion Capacitance Expensive in Area M 1 word line Capacitor Cross-section Layout Diffused bit line Polysilicon gate Polysilicon plate Metal word line Poly SiO 2 Field Oxide n + n + Inversion layer induced by plate bias Poly
    • 18. SEM of poly-diffusion capacitor 1T-DRAM
    • 19. Advanced 1T DRAM Cells Cell Plate Si Capacitor Insulator Storage Node Poly 2nd Field Oxide Refilling Poly Si Substrate Trench Cell Stacked-capacitor Cell Capacitor dielectric layer Cell plate Word line Insulating Layer Isolation Transfer gate Storage electrode
    • 20. MRAM
    • 21. The Radical Fringe: Carbon Nanotubes Scientific American, Feb. 2005
    • 22. The Radical Fringe: Carbon Nanotubes Developed by Nantera, being commercialized by LSI Logic

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