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Cost-Efficient Memory Architecture Design of NAND Flash Memory
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Cost-Efficient Memory Architecture Design of NAND Flash Memory


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  • 1. Cost-Efficient Memory Architecture Design of NAND Flash Memory Embedded Systems Chanik Park et all. Proceedings of the ICCD 2003
  • 2. Introduction
    • Objective
      • Cost efficient NAND flash memory architecture for XIP (execute-in-place)
    • Why NAND flash memory?
      • NAND offers
        • extremely high cell densities
        • high capacity
        • fast write and erase rates
        • low cost
  • 3. Backgrounds
    • NAND vs. NOR
    8KB – 64KB 64KB – 128KB Erase block Low High Price Data Storage Code Storage Ideal Usage Sequential Access Random Access Access Mode I/O (CLE, ALE, OLE signal toggle) Full Memory Interface Interface Over 10 times more than NOR Less than 10% of NAND Life span Fast erase/write/read (long initial latency/fast serial read) Very slow erase Slow write/Fast read Performance No Yes XIP 16MB-512MB 1MB-32MB Capacity NAND NOR
  • 4. Backgrounds
    • Memory Device Characteristics
      • Mobile SDRAM
        • Good performance & price, but high power consumption
      • Low-power SRAM & Fast SRAM
        • Very good performance, but high cost
      • NOR & NAND
        • Cost, Power Consumption, Read/Write/Erase performance
  • 5. Backgrounds
    • Mobile Embedded System Architecture
      • Voice-centric 2G
        • Appropriate for low-end phones, which require medium performance & cost
        • Cannot accommodate the multi-media applications’ needs of high performance & huge storage
  • 6. Backgrounds
      • Data-centric 2.5G
        • NOR for code storage & NAND for data storage
        • Yet insufficient to 3G real-time applications
        • Increased number of components increases system cost
      • 3G & SmartPhones
        • NAND flash for code/data storage
        • Use Shadowing Technique
          • Code image is copied into systems’ RAM for execution during boot-time
          • High performance but slow boot process & high power consumption (SDRAM)
        • Adoption of demand paging is needed
          • But it cannot be applicable low or mid-end system
      • Needs NAND-XIP itself !
  • 7. NAND XIP
    • NAND flash characteristics
      • Structure
        • Fixed number of blocks & 32 pages in each blocks
        • Each pages consists of 512bytes data & 16 bytes spare data for auxiliary information (bad block id. or ECC data)
      • Read/Write/Erase
        • Read/write is performed in page unit
        • Erase is performed in block unit
      • Reliability
        • Bad block management
        • EDC/ECC for bit-flipping
  • 8. NAND XIP
    • Basic Implementation
      • NAND XIP is implemented using
        • Small size of buffer
        • I/O interface – Memory interface conversion
      • Limitation
        • Poor average access performance
        • Currently basic XIP area is limited to boot code
  • 9. NAND XIP
    • Obstacles of general NAND XIP
      • Average memory access time
        • Average access time of NAND flash should be comparable to that of other memories
      • Worst case handling
        • Cache miss handling is critical problem in real time environment
      • Bad block management
        • Must hide memory space discontinuity caused by bad block
    • Approach of this paper : Intelligent Caching
      • Highest cache hit ratio by Priority-based Caching
      • Reduced access latency by Profile-based Prefetching technique
      • Bad block management using PAT (page address translation)
  • 10. Intelligent Caching Architecture
    • Profile-guided static analysis
      • Profiling process gathers following information statically
        • Access pattern,
        • Prefetching information
      • Divide code pages into
        • High priority : OS code, system libraries, real-time applications
        • Mid priority : Normal application code
        • Low priority : sequential or boot strapping code
      • Page priority & Prefetching information is stored in spare area, and used by cache controller
  • 11. Intelligent Caching Architecture
    • Victim Cache
      • Small size of fully associated cache
      • blocks replaced from main cache are stored (swapping-operation)
      • Prevent unnecessary conflict miss
    • PAT(page address translation)
      • Bad block management
        • Remaps pages in bad blocks to pages in good blocks
      • Assist low priority pages management
        • by remapping requested pages to swapped pages in system memory
  • 12. Intelligent Caching Architecture
  • 13. Intelligent Caching Architecture
    • Scenario
      • Reqeust A
        • A is cached in main cache
      • Request B (conflict with A)
        • B is moved to system memory
        • PAT is updated to remap C
      • Request C (conflict with A)
        • C replaces A in main cache
        • A is swapped to victim cache
  • 14. Experimental Setup
    • Prototype NAND XIP board
      • 32MB NAND flash
      • 256KB main cache
      • 4KB victim cache
      • 10KB SRAM for Tag data
    • NAND Miss penalty (one page)
      • 35us : Latency(10us) + page_read(512 * 50ns)
  • 15. Experimental Results
    • Average Memory Access Time
      • SDRAM shadowing
      • NAND XIP(priority) : 32KB cache
      • NOR XIP
      • NAND XIP(basic) : 32KB cache
  • 16. Experimental Results
    • Energy Consumption
      • NOR XIP
      • NAND XIP(priority) : 32KB cache
      • NAND XIP(basic) : 32KB cache
      • SDRAM shadowing
  • 17. Experimental Results
    • Booting Time & Cost
      • NAND XIP shows reasonable booting time with low cost
  • 18. Conclusion
    • NAND XIP is feasible
      • Experiment shows the feasibility of proposed architecture in real-life mobile embedded environment
      • By applying highly optimized caching techniques geared to the specific features of NAND flash and its application
    • Yet, more system-wide approach is needed
      • Worst case handling is still not easy
      • A new task scheduling algorithm, considering NAND flash operations is helpful