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Constant charge erasing scheme for flash memories - Electron ... Constant charge erasing scheme for flash memories - Electron ... Document Transcript

  • IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 4, APRIL 2002 613 Constant Charge Erasing Scheme for Flash Memories Andrea Chimenton, Paolo Pellati, and Piero Olivo Abstract—This paper presents a new erasing scheme for stant gate-to-bulk amplitude is used, the CCES consists in a se- Flash memories based on a sequence of bulk to gate-box pulses quence of box pulses with increasing amplitude. As it will be with increasing voltage amplitude. It will be experimentally and mathematically and empirically demonstrated, an equilibrium analytically demonstrated that the erasing dynamics always reaches an equilibrium condition where each pulse induces a condition is soon reached for any cell so that , that is the constant and controllable injected charge and, therefore, con- threshold shift provoked by the th erasing pulse, is equal to the stant threshold shifts. The analytical study allows us to express bulk voltage step . In such a condition, it is guaranteed that both the final threshold voltage and the oxide electric field as a the charge injected from the floating gate by each pulse remains function of technological, physical, and electrical parameters. constant. Electrical parameters can be conveniently adapted to control both the threshold voltage and the oxide fields, thus reducing oxide The shape of the resulting erasing curves is so simple that stresses. Advantages with respect to the standard box erasing the final threshold voltage can be analytically expressed scheme are theoretically and experimentally demonstrated. as a function of physical, technological and electrical parame- Index Terms—Erasing operations, Flash memories, integrated ters. This allows the analytical control of through the elec- circuit reliability, reliability, semiconductor memories. trical parameters. The final threshold voltage can be easily mod- ified by acting on the number of pulses, each one producing a threshold shift that exactly equals the bulk voltage step. Fine I. INTRODUCTION tuning of is achievable varying the amplitude of the T HE MOST common schemes used for the erase operation in Flash memories are based on a sequence of box pulses with a constant amplitude applied to the bulk of the first pulse because of the one to one relation between variations. The evolution of the oxide electric field during an erase op- and sector/array [1], [2] until a target erased threshold is reached. eration can also be analytically expressed and it will be shown Erasing curves, i.e., the threshold voltage evolution for a single that, when equilibrium is reached, it can be confined in a fully cell versus erasing time during a single erase procedure, are controllable range of values. The use of a small amplitude for the nonlinear starting with a high initial threshold shift due to first pulses removes the problem of high initial encountered the first erasing pulse. The following pulses have a decaying with SBES. Consequently, because of the reduced oxide degra- influence on the threshold shift. Therefore, the erasing speed dation, CCES is experimentally found to guarantee a higher en- can be improved only by increasing the amplitude of the durance with respect to SBES. Besides the advantages related erasing pulses. Such an approach, however, may have harmful to the analytical expression of both and , the proposed consequences in terms of reliability. In fact, owing to the high method is particularly suitable for reliability studies. In fact, initial value of the programmed threshold voltage, the use of by considering physical parameters as constant during a nom- a high voltage implies a high electric field peak within the inal erase operation, any deviation from the expected behavior oxide at the beginning of erasing, that may be dangerous for caused by oxide degradation and/or erratic bits, can be analyzed the reliability and the performance of the memory since high in terms of variation of physical parameters. electric fields produce degradation in the oxide properties [3]–[5]. II. EXPERIMENTAL SETUP To overcome this problem and to reduce the reliability effects, some authors proposed erasing schemes that are based on a con- All measurements have been performed on 512k bits sectors stant tunneling current [6], [7] showing improvements in terms of Flash test chips, that are standard NOR Flash memories (cell of endurance. Such a method requires an additional current reg- array, decoders, read path) but the internal finite state machine ulator to be integrated. controlling writing algorithms and internal generators providing This paper presents and analyzes the Constant Charge Erasing programming and erasing waveforms. The cell’s nominal tunnel Scheme (CCES), based on the concept of injecting a constant oxide thickness was 10.2 nm. charge during erasing, which is similar to the constant tunneling By means of a dedicated automated test equipment (research current approach. Differently from the Standard Box Erasing instrument for flash evaluation [8] [RIFLE]), it has been pos- Scheme (SBES) where a sequence of erasing pulses with a con- sible to perform a set of experiments fully characterizing the impact of any modification in the writing procedures. Both erase (via FN tunnel) and program (via hot electron) Manuscript received Ocotber 15, 2001; revised December 19, 2001. This work was supported in part by CNR under the MADESS II Project. The re- operations have been performed applying a sequence of box view of this paper was arranged by Editor T. Skotnicki. pulses. In particular, during the erase operation, the cells’ con- The authors are with the Dipartimento di Ingegneria, University of Fer- trol gates were biased by pulses with a constant amplitude rara, Ferrara, Italy (e-mail: achimenton@ing.unife.it; pellati@ing.unife.it; olivo@ing.unife.it). V, while the common bulk was driven by a sequence on Publisher Item Identifier S 0018-9383(02)03050-2. pulses with increasing amplitude by steps of starting at 0018-9383/02$17.00 © 2002 IEEE
  • 614 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 4, APRIL 2002 Fig. 1. Shape of the erasing pulses applied to the bulk. Fig. 2. Erasing curves for the same cell obtained using two different erasing schemes: standard box (dotted line) and constant charge (solid line). The same (Fig. 1). Both control gate and bulk pulses have a constant number of pulses N = 15 1 = 10 of duration t ms have been applied. For the duration . The common source has been kept at V ramped box V =30 1 =03 : V, V : V. For the standard box V =63: V. In to avoid the source/bulk junction turn on, while the drains have 0 both cases, the control gate was biased at 8 V. been left floating. The alternative choice of a constant and of a varying does not produce different results in our test chips and the two possible CCES implementations are theoretically equivalent. In different architecture the limitations imposed by the internal de- sign can make one solution more convenient. The threshold voltage is here defined as the control gate voltage at which the metal–oxide–semiconductor (MOS) cell drains a predefined current. III. BASIC DEFINITIONS Floating gate cells are normally programmed via hot electron injection and erased via Fowler–Nordheim tunneling (FN). In Fig. 3. Oxide electric fields at the beginning and at the end of each pulse for this paper, we consider the simple FN model, valid for triangular the two erasing curves of Fig. 2. The dashed line refers to the SBES, where the barrier [9], where the injected current can be expressed as electric field at the end of the pulse coincides with that at the beginning of the following pulse. The solid lines refer to the CCES. (1) and and are defined as In (1) (6) (2) (7) and is the threshold value measured after UV erase, and and are the source to bulk voltage and the drain to bulk (3) voltage, respectively. is the total capacitance, and is the coupling coefficient where where represents the equivalent energy barrier [10], is the symbol indicates indifferently the control gate, the drain, the electron free mass, is the electron effective mass in the the source and the bulk. oxide, is the tunneling area, is the electron charge, is the The expressions for the electric field at the extremes of the normalized Plank constant, and is the oxide electric field. th pulse, also demonstrated in [11], are As demonstrated in [11] when CCES is applied, the threshold voltage after erasing pulses, i.e., , is (8) (9) (4) where is the threshold measured after pulse , for and . where As mathematically demonstrated in the Appendix, when the equilibrium condition has been reached, i.e., after a reasonable (5) number of pulses, the expressions of the electric field at the be-
  • CHIMENTON et al.: CONSTANT CHARGE ERASING SCHEME FOR FLASH MEMORIES 615 Fig. 4. Distribution of the erased thresholds for two different sectors of 512k cells erased using the SBES (full lines) and CCES (dotted lines). For each erasing scheme two distributions are shown: after one cycle and after 60k cycles. Erasing conditions have been selected to guarantee the same average threshold in virgin samples: N = 11 1 = 10 , t ms. For CCES, V = 3 15 : 1 =03 V and V : V; for SSEB, V = 5 25: V. ginning and at the end of each pulse can be calculated from the following equations: (10) (11) and their difference can be derived from (10) and (11) (12) Fig. 5. Erasing curves for the same cell and different initial thresholds V . After few pulses, the curves join together and begin to move on the same straight It is worth noticing that the use of CCES with a fixed line. instead of a fixed brings to similar equations. In partic- ular, in all equations must be replaced by , where using (8) and (9) with V. In the CCES the electric is the gate step voltage. field does not show any dangerous peak and after few pulses it oscillates between two almost constant values which are IV. EXPERIMENTAL RESULTS AND DISCUSSION well controlled by the electrical parameters and . In Fig. 2 shows two measured erasing curves for the same cell equilibrium conditions, any reduction in produces both an where each point represents the threshold voltage measured equal reduction of [see (12)], and proportional decreases after each pulse. The same pulse duration and total number of in and . A reduction in , instead, only produces an pulses have been used for both SBES and CCES. The same increase in and in without affecting . The other has been achieved adjusting the bulk voltage in SBES. electrical parameters and do not control the equilibrium It can be noticed that in CCES, after the first few pulses, the oxide fields. erasing dynamics reaches the expected equilibrium condition, The electrical control of the peak oxide field must take so that the slope is . into account the situation before the equilibrium condition is It is evident that in SBES the major contribution to the achieved. Assuming that a fixed must be reached in a threshold shift comes from the first pulses, the others producing fixed amount of time, then, if a small is chosen, the case only small threshold variations. This implies the existence of a of standard box erase is approached and an increase in the peak harmful oxide electric field peak at the beginning of the erasing value must be expected. On the contrary, a large produces procedure, as it can be seen in Fig. 3 showing the electric larger oxide fields at equilibrium. Hence, there is a value of field at the beginning and at the end of each pulse, calculated setting the optimal tradeoff for both the confinement of
  • 616 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 4, APRIL 2002 Fig. 6. (a) Erasing curves (left) for three cells selected among a set of 10 000 cells featuring almost the same V and erased by CCES. a) The highest, b) the median, and c) the lowest curves are shown. The V distribution for the entire set of cells is shown on the right-hand figure. (b) Erasing curves (left) for the same set of cells selected for Fig. 6(a) but erased by SBES. Again, a) the highest, b) the median, and c) the lowest curves are shown. The V distribution for the entire set of cells is shown on the right-hand figure. the electric field in a restricted range and the lowering of the initial electric field peak value. The absence of a dangerous electric field at the beginning of the erasing operation has a straightforward impact on the charge trapping and therefore on memory endurance. Fig. 4 in fact, shows the distribution shifts after 60K cycles induced by charge trapping in two different sectors of the same chip, the former erased by CCES, the latter by SBES. Erase conditions have been chosen to guarantee the same erased time and average threshold shift in virgin samples and kept constant throughout the experiment by deactivating the erase verify procedure. The lower average distribution shift observable with CCES is a clue of a reduced charge trapping guaranteed by a limited electric field. As can be seen in (4), depends on physical ( , ), Fig. 7. Erasing curves for the same cell erased with different V varying from technological ( , , , , , , ), and electrical 0 V up to 2.8 V with steps of 0.4 V. All other electrical parameters have been kept constant. ( , , , , , , ) parameters. Therefore, (4) provides a simple tool for the full electrical control and anal- ysis of erasing. As expected, the expression of does not regarded as a cell attribute for a given set of electrical parame- depend on the threshold voltage and this result is well con- ters. Hence, having a full control over the nominal erase opera- firmed by the experiments of Fig. 5 where the same cell pro- tion, any deviation from the reference behavior caused by erratic grammed at different has been erased using the same elec- bits [12] and/or charge trapping/detrapping within the tunneling trical parameters. oxide [4] can be experimentally observed by checking for a dif- The natural spread of technological parameters does not ferent constant slope of the erasing curves [11] and it can be allow, however, achieving the same for an entire sector. modeled in terms of physical parameter variation. Fig. 6(a) shows the erasing curves for three different cells with Fig. 7 shows the influence of the parameter on the erasing the highest, the median, and the lowest among a set of dynamics for the same cell. It is evident that the erasing curves 10 000 cells with the same and belonging to the same simply differ because of a translation in the asymptotic straight sector. The distribution for the same set of cells is also line. In fact, when the equilibrium conditions have been reached, shown in Fig. 6(a). It is important to notice that an equilibrium the threshold voltage shifts equal . Therefore does not condition characterized by a linear erasing curve and a well influence the slope of the asymptotic straight lines. defined value is always reached. A similar distribution is From (4) and (5), it is reasonable to expect also found with SBES [Fig. 6(b)], confirming that such a spread cannot be attributed to or controlled by the erasing scheme. (13) As a reference, the technological and physical parameters of any cell can be considered as constant and therefore can be as experimentally confirmed in Fig. 8.
  • CHIMENTON et al.: CONSTANT CHARGE ERASING SCHEME FOR FLASH MEMORIES 617 APPENDIX The expressions of the electric field at the beginning and at the end of each erasing pulse are [11] (14) (15) where the time series is defined as (16) for and . Fig. 8. Relative dependence of V 1V (solid line), on V (dotted line), is calculated as [11] 1 and t (dotted line). The nominal values are V = 1 5 1 = 0 225 V, : V, V : 1 = 55 and t : ms. (17) This result can be usefully applied to control : in partic- Here it is demonstrated that the electric field always con- ular, the entire erased threshold distribution can be shifted up verges toward a stable equilibrium value. This is true if and only and down simply adjusting the value of by the same desired if the time series always converges toward a stable equilib- quantity, while keeping constant all other electrical parameters. rium point hereafter denoted as . Then, its expression is given The experimental sensitivity of on and is also as a function of the other electrical and physical parameters. Fi- shown in Fig. 8. As it can be seen, produces nonlinear and nally, its stability when changing the starting value is shown. relatively small variations, while for , an almost linear de- a) Existence of an Equilibrium Point: For the time series pendence is found in the selected range. , it can be easily noticed that Summarizing the previous results, it can be stated that (18) can be directly controlled by acting on , and at the same time, on and to successfully limit the oxide electric field. Therefore, in equation (18), if an integer exists so that (19) V. CONCLUSION then for any and viceversa, i.e., In this paper, a new erasing scheme for Flash memories, is an equilibrium point for the time series (16). based on bulk to gate box pulses with increasing amplitude, has b) Equilibrium Expressions of the Electric Field and of the been presented and analyzed. It has been experimentally and Threshold Voltage: Using (17) and (19), the following expres- mathematically demonstrated that the erasing dynamics always sion for can be obtained: reaches an equilibrium condition where each pulse provokes a (20) constant charge injection corresponding to constant threshold shifts. With respect to an erasing scheme with constant ampli- Expressions (10) and (11) can be easily obtained from (20) using tude pulses, this method allows to control the erasing dynamics, (14)–(16). the final threshold voltage and the oxide electric field, thus c) Stability of the Equilibrium: Let us consider the function reducing oxide long-term wear out. defined as has been analytically expressed as a function of physical, technological, and electrical parameters, and its dependence on (21) electrical parameters has been deeply investigated. It has also been found that varies linearly with the amplitude of the first pulse, so that the entire threshold distribution can be shifted which describes the threshold voltage shift for any value by simply varying this parameter while keeping constant all the of the time series . others. is a decreasing function of with an oblique asymptote Analytical expressions for the oxide field at the beginning and whose slope is 1. at the end of each pulse have been provided, showing that the Considering the time series at a generic instant , and electric field can be usefully controlled by the duration of each supposing that it differs from by the positive quantity pulse and by the pulse amplitude increment. (22) The proposed erasing scheme can be also conveniently used for reliability studies, since any deviation from the nominal then, since is decreasing, we have linear behavior imposed to the erasing curves by a set of (23) electrical parameters can be modeled as a variation of physical parameters. where .
  • 618 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 4, APRIL 2002 Therefore, using (18), will be given by [10] P. Olivo, J. Suné, and B. Riccò, “On the determination of the Si–SiO barrier height from the Fowler–Nordheim plot,” IEEE Electron Device Lett., vol. 12, pp. 620–622, Nov. 1991. (24) [11] A. Chimenton, P. Pellati, and P. Olivo, “Analysis of erratic bits in Flash memories,” in Proc. Int. Rel. Phys. Symp., 2001, pp. 17–22. and increases without exceeding , i.e., [12] T. C. Ong et al., “Erratic erase in ETOX™ Flash memory array,” in Proc. VLSI Symp. Technology, 1993, pp. 83–84. (25) The same arguments apply when Andrea Chimenton received the degree in elec- tronic engineering from the University of Ferrara, (26) Ferrara, Italy, in 2000, where he is currently pursuing the Ph.D. degree. His scientific interests are in the area of non- i.e., volatile memory characterization and reliability and modeling of physical mechanisms controlling memory writing. (27) Therefore, for the generality of , always gradually ap- proaches . ACKNOWLEDGMENT Paolo Pellati received the degree in electronic engi- neering from the University of Ferrara, Ferrara, Italy, The authors would like to thank A. Modelli for helpful in 1997. He received the Ph.D. degree in information engineering from the University of Modena, Modena, discussions. Italy, in 2001. Since 2001, he has held a research contract REFERENCES with the University of Ferrara for the design of dedicated instrumentation. His scientific interests [1] J. T. Perk, J. Y. Chun, H. K. Kim, S. J. Jang, and C. G. Yu, “New program- are in the area of electronic instrumentation design, ming and erasing schemes for P-channel Flash memory,” IEEE Electron high-performance board design, nonvolatile memory Device Lett., vol. 21, pp. 491–493, Oct. 2000. characterization, and testing. [2] T. Endoh, K. Shimizu, H. Iizuka, and F. Masuoka, “A new write/erase method to improve the read disturb characteristics based on the decay phenomena of stress leakage current for Flash memories,” IEEE Trans. Electron Devices, vol. 45, pp. 98–104, Jan. 1998. [3] P. Olivo, T. N. Nguyen, and B. Riccò, “High-field-induced degradation Piero Olivo received the degree in electronic engi- in ultra-thin SiO films,” IEEE Trans. Electron Devices, vol. 35, pp. neering and the Ph.D. degree from the University 2259–2267, 1988. of Bologna, Bologna, Italy, in 1980 and 1987, [4] Y. B. Park and D. K. Schroeder, “Degradation of thin tunnel gate oxide respectively. under constant Fowler–Nordheim current stress for a Flash EEPROM,” In 1983, he joined the Department of Electronics IEEE Trans. Electron Devices, vol. 45, pp. 1361–1368, June 1998. and Computer Systems, University of Bologna, [5] P. Cappelletti and A. Modelli, “Flash memory reliability,” in where he became Associate Professor of electronic Flash Memories, P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni, instrumentation and measurements in 1991. In 1993, Eds. Amsterdam, The Netherlands: Kluwer, 1999, pp. 399–442. he became Full Professor of Applied Electronics, [6] R. Bez, D. Cantarelli, L. Moioli, G. Ortolani, G. Seravalli, C. Villa, University of Catania, Catania, Italy. In 1995, he and M. Dallabora, “A new erasing method for a single-voltage long- joined the University of Ferrara, Ferrara, Italy. endurance Flash memories,” IEEE Electron Device Lett., vol. 19, pp. From 1986 to 1987 and autumn 1989, he was a Visiting Scientist at the IBM 37–39, Feb. 1998. T. J. Watson Research Center, Yorktown Heights, NY. His scientific interests [7] M. Dallabora et al., “A 20MB/s data rate 2.5V Flash memory with cur- are in the area of: a) solid state devices and b) ICs design and testing. In rent controlled field erasing for 1M cycle endurance,” in ISSCC97, 1997, the field of solid state devices, he has worked on SiO physics, quantum pp. 396–397. effects, charge transport through thin SiO structures, charge trapping in SiO , [8] P. Pellati and P. Olivo, “Automated test equipment for research on oxide breakdown and reliability, MOS measurements techniques, thin-oxide nonvolatile memories,” IEEE Trans. Instrum. Meas., vol. 50, pp. properties, and nonvolatile memories characterization. In the field of ICs 1162–1166, Oct. 2001. design and testing, instead, he has worked on signature analysis testing, design [9] M. Lenzinger and E. H. Snow, “Fowler–Nordheim tunneling into ther- for testability techniques, fault modeling and fault simulation, IDDQ testing, mally grown SiO ,” J. Appl. Phys., vol. 40, p. 278, 1969. self-checking circuits, and nonvolatile memory testing.