614 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 4, APRIL 2002
Fig. 1. Shape of the erasing pulses applied to the bulk.
Fig. 2. Erasing curves for the same cell obtained using two different erasing
schemes: standard box (dotted line) and constant charge (solid line). The same
(Fig. 1). Both control gate and bulk pulses have a constant number of pulses N = 15 1 = 10
of duration t ms have been applied. For the
duration . The common source has been kept at V ramped box V =30 1 =03
: V, V : V. For the standard box V =63: V. In
to avoid the source/bulk junction turn on, while the drains have 0
both cases, the control gate was biased at 8 V.
been left floating.
The alternative choice of a constant and of a varying
does not produce different results in our test chips and the two
possible CCES implementations are theoretically equivalent. In
different architecture the limitations imposed by the internal de-
sign can make one solution more convenient.
The threshold voltage is here defined as the control gate
voltage at which the metal–oxide–semiconductor (MOS) cell
drains a predefined current.
III. BASIC DEFINITIONS
Floating gate cells are normally programmed via hot electron
injection and erased via Fowler–Nordheim tunneling (FN). In
Fig. 3. Oxide electric fields at the beginning and at the end of each pulse for
this paper, we consider the simple FN model, valid for triangular the two erasing curves of Fig. 2. The dashed line refers to the SBES, where the
barrier , where the injected current can be expressed as electric field at the end of the pulse coincides with that at the beginning of the
following pulse. The solid lines refer to the CCES.
and and are defined as
In (1) (6)
and is the threshold value measured after UV erase, and
and are the source to bulk voltage and the drain to bulk
voltage, respectively. is the total
capacitance, and is the coupling coefficient where
where represents the equivalent energy barrier , is the symbol indicates indifferently the control gate, the drain,
the electron free mass, is the electron effective mass in the the source and the bulk.
oxide, is the tunneling area, is the electron charge, is the The expressions for the electric field at the extremes of the
normalized Plank constant, and is the oxide electric field. th pulse, also demonstrated in , are
As demonstrated in  when CCES is applied, the threshold
voltage after erasing pulses, i.e., , is (8)
where is the threshold measured after pulse , for
where As mathematically demonstrated in the Appendix, when the
equilibrium condition has been reached, i.e., after a reasonable
(5) number of pulses, the expressions of the electric field at the be-
CHIMENTON et al.: CONSTANT CHARGE ERASING SCHEME FOR FLASH MEMORIES 615
Fig. 4. Distribution of the erased thresholds for two different sectors of 512k cells erased using the SBES (full lines) and CCES (dotted lines). For each erasing
scheme two distributions are shown: after one cycle and after 60k cycles. Erasing conditions have been selected to guarantee the same average threshold in virgin
samples: N = 11 1 = 10
, t ms. For CCES, V = 3 15
: 1 =03
V and V : V; for SSEB, V = 5 25: V.
ginning and at the end of each pulse can be calculated from the
and their difference can be derived from (10) and (11)
Fig. 5. Erasing curves for the same cell and different initial thresholds V .
After few pulses, the curves join together and begin to move on the same straight
It is worth noticing that the use of CCES with a fixed line.
instead of a fixed brings to similar equations. In partic-
ular, in all equations must be replaced by , where
using (8) and (9) with V. In the CCES the electric
is the gate step voltage.
field does not show any dangerous peak and after few pulses
it oscillates between two almost constant values which are
IV. EXPERIMENTAL RESULTS AND DISCUSSION well controlled by the electrical parameters and . In
Fig. 2 shows two measured erasing curves for the same cell equilibrium conditions, any reduction in produces both an
where each point represents the threshold voltage measured equal reduction of [see (12)], and proportional decreases
after each pulse. The same pulse duration and total number of in and . A reduction in , instead, only produces an
pulses have been used for both SBES and CCES. The same increase in and in without affecting . The other
has been achieved adjusting the bulk voltage in SBES. electrical parameters and do not control the equilibrium
It can be noticed that in CCES, after the first few pulses, the oxide fields.
erasing dynamics reaches the expected equilibrium condition, The electrical control of the peak oxide field must take
so that the slope is . into account the situation before the equilibrium condition is
It is evident that in SBES the major contribution to the achieved. Assuming that a fixed must be reached in a
threshold shift comes from the first pulses, the others producing fixed amount of time, then, if a small is chosen, the case
only small threshold variations. This implies the existence of a of standard box erase is approached and an increase in the peak
harmful oxide electric field peak at the beginning of the erasing value must be expected. On the contrary, a large produces
procedure, as it can be seen in Fig. 3 showing the electric larger oxide fields at equilibrium. Hence, there is a value of
field at the beginning and at the end of each pulse, calculated setting the optimal tradeoff for both the confinement of
616 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 4, APRIL 2002
Fig. 6. (a) Erasing curves (left) for three cells selected among a set of 10 000 cells featuring almost the same V and erased by CCES. a) The highest, b) the
median, and c) the lowest curves are shown. The V distribution for the entire set of cells is shown on the right-hand figure. (b) Erasing curves (left) for the same
set of cells selected for Fig. 6(a) but erased by SBES. Again, a) the highest, b) the median, and c) the lowest curves are shown. The V distribution for the entire
set of cells is shown on the right-hand figure.
the electric field in a restricted range and the lowering of the
initial electric field peak value. The absence of a dangerous
electric field at the beginning of the erasing operation has a
straightforward impact on the charge trapping and therefore on
memory endurance. Fig. 4 in fact, shows the distribution shifts
after 60K cycles induced by charge trapping in two different
sectors of the same chip, the former erased by CCES, the latter
by SBES. Erase conditions have been chosen to guarantee the
same erased time and average threshold shift in virgin samples
and kept constant throughout the experiment by deactivating
the erase verify procedure. The lower average distribution shift
observable with CCES is a clue of a reduced charge trapping
guaranteed by a limited electric field.
As can be seen in (4), depends on physical ( , ), Fig. 7. Erasing curves for the same cell erased with different V varying from
technological ( , , , , , , ), and electrical 0 V up to 2.8 V with steps of 0.4 V. All other electrical parameters have been
( , , , , , , ) parameters. Therefore, (4)
provides a simple tool for the full electrical control and anal-
ysis of erasing. As expected, the expression of does not regarded as a cell attribute for a given set of electrical parame-
depend on the threshold voltage and this result is well con- ters. Hence, having a full control over the nominal erase opera-
firmed by the experiments of Fig. 5 where the same cell pro- tion, any deviation from the reference behavior caused by erratic
grammed at different has been erased using the same elec- bits  and/or charge trapping/detrapping within the tunneling
trical parameters. oxide  can be experimentally observed by checking for a dif-
The natural spread of technological parameters does not ferent constant slope of the erasing curves  and it can be
allow, however, achieving the same for an entire sector. modeled in terms of physical parameter variation.
Fig. 6(a) shows the erasing curves for three different cells with Fig. 7 shows the influence of the parameter on the erasing
the highest, the median, and the lowest among a set of dynamics for the same cell. It is evident that the erasing curves
10 000 cells with the same and belonging to the same simply differ because of a translation in the asymptotic straight
sector. The distribution for the same set of cells is also line. In fact, when the equilibrium conditions have been reached,
shown in Fig. 6(a). It is important to notice that an equilibrium the threshold voltage shifts equal . Therefore does not
condition characterized by a linear erasing curve and a well influence the slope of the asymptotic straight lines.
defined value is always reached. A similar distribution is From (4) and (5), it is reasonable to expect
also found with SBES [Fig. 6(b)], confirming that such a spread
cannot be attributed to or controlled by the erasing scheme. (13)
As a reference, the technological and physical parameters of
any cell can be considered as constant and therefore can be as experimentally confirmed in Fig. 8.
CHIMENTON et al.: CONSTANT CHARGE ERASING SCHEME FOR FLASH MEMORIES 617
The expressions of the electric field at the beginning and at
the end of each erasing pulse are 
where the time series is defined as
for and .
Fig. 8. Relative dependence of V 1V (solid line),
on V (dotted line),
is calculated as 
and t (dotted line). The nominal values are V = 1 5 1 = 0 225 V,
: V, V :
1 = 55
and t : ms. (17)
This result can be usefully applied to control : in partic- Here it is demonstrated that the electric field always con-
ular, the entire erased threshold distribution can be shifted up verges toward a stable equilibrium value. This is true if and only
and down simply adjusting the value of by the same desired if the time series always converges toward a stable equilib-
quantity, while keeping constant all other electrical parameters. rium point hereafter denoted as . Then, its expression is given
The experimental sensitivity of on and is also as a function of the other electrical and physical parameters. Fi-
shown in Fig. 8. As it can be seen, produces nonlinear and nally, its stability when changing the starting value is shown.
relatively small variations, while for , an almost linear de- a) Existence of an Equilibrium Point: For the time series
pendence is found in the selected range. , it can be easily noticed that
Summarizing the previous results, it can be stated that
can be directly controlled by acting on , and at the same time,
on and to successfully limit the oxide electric field. Therefore, in equation (18), if an integer exists so that
V. CONCLUSION then for any and viceversa, i.e.,
In this paper, a new erasing scheme for Flash memories, is an equilibrium point for the time series (16).
based on bulk to gate box pulses with increasing amplitude, has b) Equilibrium Expressions of the Electric Field and of the
been presented and analyzed. It has been experimentally and Threshold Voltage: Using (17) and (19), the following expres-
mathematically demonstrated that the erasing dynamics always sion for can be obtained:
reaches an equilibrium condition where each pulse provokes a
constant charge injection corresponding to constant threshold
shifts. With respect to an erasing scheme with constant ampli-
Expressions (10) and (11) can be easily obtained from (20) using
tude pulses, this method allows to control the erasing dynamics,
the final threshold voltage and the oxide electric field, thus
c) Stability of the Equilibrium: Let us consider the function
reducing oxide long-term wear out.
has been analytically expressed as a function of physical,
technological, and electrical parameters, and its dependence on
electrical parameters has been deeply investigated. It has also
been found that varies linearly with the amplitude of the
first pulse, so that the entire threshold distribution can be shifted which describes the threshold voltage shift for any value
by simply varying this parameter while keeping constant all the of the time series .
others. is a decreasing function of with an oblique asymptote
Analytical expressions for the oxide field at the beginning and whose slope is 1.
at the end of each pulse have been provided, showing that the Considering the time series at a generic instant , and
electric field can be usefully controlled by the duration of each supposing that it differs from by the positive quantity
pulse and by the pulse amplitude increment. (22)
The proposed erasing scheme can be also conveniently used
for reliability studies, since any deviation from the nominal then, since is decreasing, we have
linear behavior imposed to the erasing curves by a set of
electrical parameters can be modeled as a variation of physical
parameters. where .
618 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 4, APRIL 2002
Therefore, using (18), will be given by  P. Olivo, J. Suné, and B. Riccò, “On the determination of the Si–SiO
barrier height from the Fowler–Nordheim plot,” IEEE Electron Device
Lett., vol. 12, pp. 620–622, Nov. 1991.
(24)  A. Chimenton, P. Pellati, and P. Olivo, “Analysis of erratic bits in Flash
memories,” in Proc. Int. Rel. Phys. Symp., 2001, pp. 17–22.
and increases without exceeding , i.e.,  T. C. Ong et al., “Erratic erase in ETOX™ Flash memory array,” in Proc.
VLSI Symp. Technology, 1993, pp. 83–84.
The same arguments apply when Andrea Chimenton received the degree in elec-
tronic engineering from the University of Ferrara,
(26) Ferrara, Italy, in 2000, where he is currently pursuing
the Ph.D. degree.
His scientific interests are in the area of non-
i.e., volatile memory characterization and reliability
and modeling of physical mechanisms controlling
Therefore, for the generality of , always gradually ap-
ACKNOWLEDGMENT Paolo Pellati received the degree in electronic engi-
neering from the University of Ferrara, Ferrara, Italy,
The authors would like to thank A. Modelli for helpful in 1997. He received the Ph.D. degree in information
engineering from the University of Modena, Modena,
discussions. Italy, in 2001.
Since 2001, he has held a research contract
REFERENCES with the University of Ferrara for the design of
dedicated instrumentation. His scientific interests
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 P. Olivo, T. N. Nguyen, and B. Riccò, “High-field-induced degradation Piero Olivo received the degree in electronic engi-
in ultra-thin SiO films,” IEEE Trans. Electron Devices, vol. 35, pp. neering and the Ph.D. degree from the University
2259–2267, 1988. of Bologna, Bologna, Italy, in 1980 and 1987,
 Y. B. Park and D. K. Schroeder, “Degradation of thin tunnel gate oxide respectively.
under constant Fowler–Nordheim current stress for a Flash EEPROM,” In 1983, he joined the Department of Electronics
IEEE Trans. Electron Devices, vol. 45, pp. 1361–1368, June 1998. and Computer Systems, University of Bologna,
 P. Cappelletti and A. Modelli, “Flash memory reliability,” in where he became Associate Professor of electronic
Flash Memories, P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni, instrumentation and measurements in 1991. In 1993,
Eds. Amsterdam, The Netherlands: Kluwer, 1999, pp. 399–442. he became Full Professor of Applied Electronics,
 R. Bez, D. Cantarelli, L. Moioli, G. Ortolani, G. Seravalli, C. Villa, University of Catania, Catania, Italy. In 1995, he
and M. Dallabora, “A new erasing method for a single-voltage long- joined the University of Ferrara, Ferrara, Italy.
endurance Flash memories,” IEEE Electron Device Lett., vol. 19, pp. From 1986 to 1987 and autumn 1989, he was a Visiting Scientist at the IBM
37–39, Feb. 1998. T. J. Watson Research Center, Yorktown Heights, NY. His scientific interests
 M. Dallabora et al., “A 20MB/s data rate 2.5V Flash memory with cur- are in the area of: a) solid state devices and b) ICs design and testing. In
rent controlled field erasing for 1M cycle endurance,” in ISSCC97, 1997, the field of solid state devices, he has worked on SiO physics, quantum
pp. 396–397. effects, charge transport through thin SiO structures, charge trapping in SiO ,
 P. Pellati and P. Olivo, “Automated test equipment for research on oxide breakdown and reliability, MOS measurements techniques, thin-oxide
nonvolatile memories,” IEEE Trans. Instrum. Meas., vol. 50, pp. properties, and nonvolatile memories characterization. In the field of ICs
1162–1166, Oct. 2001. design and testing, instead, he has worked on signature analysis testing, design
 M. Lenzinger and E. H. Snow, “Fowler–Nordheim tunneling into ther- for testability techniques, fault modeling and fault simulation, IDDQ testing,
mally grown SiO ,” J. Appl. Phys., vol. 40, p. 278, 1969. self-checking circuits, and nonvolatile memory testing.