Boot Issues Processor comparison TigerSHARC multi-processor system Blackfin single-core
Overview <ul><li>Had planned to spend 20 minutes on boot issues on processor systems </li></ul><ul><li>However, TigerSHARC...
Information can be found at Analog Web site <ul><li>Analog Devices Loader Manual and various Engineer to Engineer applicat...
Blackfin ADSP-BF533 “Conventional approach” <ul><li>What does “booting” the processor require and why is it necessary? </l...
How the processor “boots” is determined by “hard” settings Powers up as 0 Hard-wired
Here boot procedure starts with code from “on chip” boot rom
How do you “put” the information into the “Flash” <ul><li>Use VDSP to build an “executable” and “test” it </li></ul><ul><l...
How do you “put” the information into the “Flash” <ul><li>Once “.ldr” loader file built, you use “Tools | Flash Programmer...
Step 1 – set PC to 0xEF000000 and Jump (PC)
Step 2 <ul><li>On-board boot ROM, configures important registers </li></ul><ul><li>Performs DMA transfer from (8 or 16 bit...
Step 3 <ul><li>Boot code is used to examine the “10 –byte header” of downloaded block </li></ul>Block body (in most cases)
Step 4 – Handle block based on flag information
If zero fill block shown in flags – then boot ROM code does <ul><li>Set address register to address (first 4 bytes of head...
If non zero fill block shown in flags – then boot ROM code does <ul><li>Set DMA destination register  to address (first 4 ...
If init block shown in flags – then boot ROM code does <ul><li>Set DMA destination register  to address (first 4 bytes of ...
Problem – Catch 22 <ul><li>It is very likely that the application code is “too big” to fit into internal Blackfin Memory <...
Two stage boot-process – stage 1 “Init code” executes then returns to Boot ROM Init block runs and configures SDRAM
Make sure that you don’t destroy the boot ROM register values
This code configures the SDRAM Recover Boot ROM register values If change R0 (return value) then can cause loader to “sele...
Step 2 – Boot ROM code can now load code into SDRAM
Some issues – How do you handle BF561 – multi-core processor? <ul><li>Build 2 .dxe’s – one for each core </li></ul><ul><li...
Other boot approaches <ul><li>Flash memory </li></ul><ul><ul><li>16 bit data bus </li></ul></ul><ul><ul><li>32 bit address...
Other boot approaches
Speed of booting over 1 line 16 times slower than over 16 plus “clock speed issues” <ul><li>Flash memory </li></ul><ul><ul...
What type of SPI memory?
TigerSHARC Boot <ul><li>Multi-processor system, but only 1 boot FLASH </li></ul><ul><li>How do you handle bus contention? ...
Overview <ul><li>Had planned to spend 20 minutes on boot issues on processor systems </li></ul><ul><li>However, TigerSHARC...
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Boot Issues Processor comparison TigerSHARC multi-processor ...

  1. 1. Boot Issues Processor comparison TigerSHARC multi-processor system Blackfin single-core
  2. 2. Overview <ul><li>Had planned to spend 20 minutes on boot issues on processor systems </li></ul><ul><li>However, TigerSHARC boot involved so many different aspects of the processor and special instructions that decided to examine in more detail </li></ul><ul><li>You will be building a multi-core boot sequence as part of Lab. 4 </li></ul>
  3. 3. Information can be found at Analog Web site <ul><li>Analog Devices Loader Manual and various Engineer to Engineer application and technical notes </li></ul><ul><li>Manuals www.analog.com/processors/blackfin/technicalLibrary/manuals/index.html </li></ul><ul><li>Application Notes </li></ul><ul><li>www.analog.com/processors/blackfin/technicalLibrary/applicationNotes/index.html </li></ul><ul><li>Technical articles </li></ul><ul><li>www.analog.com/processors/blackfin/technicalLibrary/technicalArticles/index.html </li></ul>
  4. 4. Blackfin ADSP-BF533 “Conventional approach” <ul><li>What does “booting” the processor require and why is it necessary? </li></ul><ul><li>On power up, the processor “knows” nothing. </li></ul><ul><li>Need a systematic and reliable mechanism to “configure” the system. </li></ul><ul><ul><li>Essentially put registers into known state </li></ul></ul><ul><ul><li>Move code from an external (8-bit wide) EPROM or FLASH memory to faster memory for easier execution </li></ul></ul><ul><ul><li>Jump to the new code </li></ul></ul>
  5. 5. How the processor “boots” is determined by “hard” settings Powers up as 0 Hard-wired
  6. 6. Here boot procedure starts with code from “on chip” boot rom
  7. 7. How do you “put” the information into the “Flash” <ul><li>Use VDSP to build an “executable” and “test” it </li></ul><ul><li>Switch project option to be “loader”. </li></ul><ul><li>This “build” option breaks the “.dxe” into blocks – “.ldr” file (in Debug) </li></ul><ul><ul><li>Blocks for characters </li></ul></ul><ul><ul><li>Blocks for empty arrays (set to 0) </li></ul></ul><ul><ul><li>Blocks for full arrays (not set to 0) </li></ul></ul><ul><ul><li>Program code for “internal” memory </li></ul></ul><ul><ul><li>Program code for “external” memory (SDRAM) </li></ul></ul><ul><ul><li>Boot “block” – first section of code than runs </li></ul></ul>
  8. 8. How do you “put” the information into the “Flash” <ul><li>Once “.ldr” loader file built, you use “Tools | Flash Programmer” to download a special program into Blackfin (TigerSHARC) </li></ul><ul><li>This program, running on the Blackfin, burns the code into FLASH </li></ul><ul><li>Disconnect VDSP and “reset the processor” </li></ul><ul><li>The processor now boots </li></ul>
  9. 9. Step 1 – set PC to 0xEF000000 and Jump (PC)
  10. 10. Step 2 <ul><li>On-board boot ROM, configures important registers </li></ul><ul><li>Performs DMA transfer from (8 or 16 bit wide – slow speed) FLASH to on-board SCRATCH memory </li></ul><ul><ul><li>Must go to “scratch memory” otherwise the new downloaded code might over write old downloaded code </li></ul></ul>
  11. 11. Step 3 <ul><li>Boot code is used to examine the “10 –byte header” of downloaded block </li></ul>Block body (in most cases)
  12. 12. Step 4 – Handle block based on flag information
  13. 13. If zero fill block shown in flags – then boot ROM code does <ul><li>Set address register to address (first 4 bytes of header) </li></ul><ul><li>Set counter (second 4 bytes in memory) </li></ul><ul><li>Using pseudo-TigerSHARC syntax </li></ul><ul><li>LC0 = count </li></ul><ul><li>J0 = address </li></ul><ul><li>XR0 = 0 </li></ul><ul><li>Loop: </li></ul><ul><li>if nlco0e, jump Loop, [J0 += 1] = XR0 </li></ul><ul><li>Get next header </li></ul>
  14. 14. If non zero fill block shown in flags – then boot ROM code does <ul><li>Set DMA destination register to address (first 4 bytes of header) </li></ul><ul><li>Set DMA destination counter (second 4 bytes in memory) </li></ul><ul><li>Set DMA destination stride register to 4 </li></ul><ul><li>Set DMA source register to next address in FLASH </li></ul><ul><li>Set DMA source counter to count (bytes) </li></ul><ul><li>Set DMA source stride to 2 (if 16-bit flash) </li></ul><ul><li>Set up DMA interrupt routine to set “done-flag” </li></ul><ul><li>Activate DMA </li></ul><ul><li>Wait till “done” </li></ul><ul><li>Process next block </li></ul>
  15. 15. If init block shown in flags – then boot ROM code does <ul><li>Set DMA destination register to address (first 4 bytes of header) </li></ul><ul><li>Set DMA destination counter (second 4 bytes in memory) </li></ul><ul><li>Set DMA destination stride register to 4 </li></ul><ul><li>Set DMA source register to next address in FLASH </li></ul><ul><li>Set DMA source counter to count (bytes) </li></ul><ul><li>Set DMA source stride to 2 (if 16-bit flash) </li></ul><ul><li>Set up DMA interrupt routine to set “done-flag” </li></ul><ul><li>Activate DMA </li></ul><ul><li>Wait till “done” </li></ul><ul><li>Set PC to address (first 4 bytes of header) </li></ul><ul><li>and JUMP PC – system now boots </li></ul>
  16. 16. Problem – Catch 22 <ul><li>It is very likely that the application code is “too big” to fit into internal Blackfin Memory </li></ul><ul><li>But you can’t write “blocks” of code in SDRAM as the SDRAM is not “configured” to accept data after power up </li></ul><ul><li>You can’t put the configuration code in on-board ROM as you don’t know what SDRAM will be used by the system </li></ul>
  17. 17. Two stage boot-process – stage 1 “Init code” executes then returns to Boot ROM Init block runs and configures SDRAM
  18. 18. Make sure that you don’t destroy the boot ROM register values
  19. 19. This code configures the SDRAM Recover Boot ROM register values If change R0 (return value) then can cause loader to “select” which executable is to be downloaded “multi-code” boot return to boot loader
  20. 20. Step 2 – Boot ROM code can now load code into SDRAM
  21. 21. Some issues – How do you handle BF561 – multi-core processor? <ul><li>Build 2 .dxe’s – one for each core </li></ul><ul><li>Build a loader “file” with new boot loader.dxe as “init” block core A. dxe core B.dxe </li></ul><ul><li>On-chip boot rom – downloads “new loader” to special memory location, and then runs the code </li></ul><ul><li>New loader is responsible for putting code and data arrays as required </li></ul>
  22. 22. Other boot approaches <ul><li>Flash memory </li></ul><ul><ul><li>16 bit data bus </li></ul></ul><ul><ul><li>32 bit address bus </li></ul></ul><ul><ul><li>Various control logic lines </li></ul></ul><ul><li>Minimal approach – 4 wires -- SPI interface </li></ul><ul><ul><li>Chip select </li></ul></ul><ul><ul><li>Clock </li></ul></ul><ul><ul><li>Master out – Slave In </li></ul></ul><ul><ul><li>Master in – Slave out </li></ul></ul>
  23. 23. Other boot approaches
  24. 24. Speed of booting over 1 line 16 times slower than over 16 plus “clock speed issues” <ul><li>Flash memory </li></ul><ul><ul><li>16 bit data bus </li></ul></ul><ul><ul><li>32 bit address bus </li></ul></ul><ul><ul><li>Various control logic lines </li></ul></ul><ul><li>Minimal approach – 4 wires -- SPI interface </li></ul><ul><ul><li>Chip select </li></ul></ul><ul><ul><li>Clock </li></ul></ul><ul><ul><li>Master out – Slave In </li></ul></ul><ul><ul><li>Master in – Slave out </li></ul></ul>
  25. 25. What type of SPI memory?
  26. 26. TigerSHARC Boot <ul><li>Multi-processor system, but only 1 boot FLASH </li></ul><ul><li>How do you handle bus contention? </li></ul><ul><li>Does having “on-chip” boot ROM (like Blackfin) make any sense? </li></ul><ul><li>TigerSHARC not very good at handling the bit patterns in the “field” of the block header – need to understand special TigerSHARC bit pattern instructions (extract instructions </li></ul>
  27. 27. Overview <ul><li>Had planned to spend 20 minutes on boot issues on processor systems </li></ul><ul><li>However, TigerSHARC boot involved so many different aspects of the processor and special instructions that decided to examine in more detail </li></ul><ul><li>You will be building a multi-core boot sequence as part of Lab. 4 </li></ul>

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