Parallel Flash Programming
                                                                                  and FPGA Confi...
Parallel Flash Programming
Lattice Semiconductor                                                                   and FPG...
Parallel Flash Programming
Lattice Semiconductor                                                               and FPGA Co...
Parallel Flash Programming
Lattice Semiconductor                                                                          ...
Parallel Flash Programming
Lattice Semiconductor                                                              and FPGA Con...
Parallel Flash Programming
Lattice Semiconductor                                                            and FPGA Confi...
Parallel Flash Programming
Lattice Semiconductor                                                          and FPGA Configu...
Parallel Flash Programming
Lattice Semiconductor                                                            and FPGA Confi...
Parallel Flash Programming
Lattice Semiconductor                                                             and FPGA Conf...
Parallel Flash Programming
Lattice Semiconductor                                                          and FPGA Configu...
Parallel Flash Programming
Lattice Semiconductor                                                              and FPGA Con...
Parallel Flash Programming
Lattice Semiconductor                                                                   and FPG...
Parallel Flash Programming
Lattice Semiconductor                                                             and FPGA Conf...
Parallel Flash Programming
Lattice Semiconductor                                                                  and FPGA...
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Transcript of "AN8077 - Parallel Flash Programming and FPGA Configuration ..."

  1. 1. Parallel Flash Programming and FPGA Configuration August 2007 Application Note AN8077 Introduction SRAM-based FPGA devices are volatile and require configuration at power up, with the configuration data held in an external device. Systems often task an embedded microprocessor with FPGA configuration, transferring the data from an on-board ROM or Flash memory. However, on systems that require fast configurations, or systems that do not have microprocessor resources readily available, a dedicated PROM is commonly used. Such PROM devices are typically expensive and are usually sourced from a single vendor. An alternative solution is to use a Lattice non-volatile FPGA as an FPGA Loader. The FPGA Loader, coupled with a standard parallel Flash memory can perform the function of a PROM or microprocessor. This FPGA provides the JTAG programming interface to the Flash, as well as control of data to the other FPGAs for configuration. Figure 1 shows a diagram of the Flash and FPGA Loader device. Note: Unless described otherwise, the remainder of this document will use the following terminology: • “FPGA Loader” – The non-volatile FPGA device that provides the Flash interface. • “FPGA” – An FPGA to be configured by the FPGA Loader. Figure 1. Flash Programmer Interface Parallel Flash MachXO or Device LatticeXP A FLASH_ADDR DQ FLASH_DATA WE FLASH_WE FPGA OE FLASH_OE Configuration WE FLASH_CE RESET FLASH_RSTn BYTE FLASH_BYTE RY/BY# FLASH_RDY ispJTAG Port 1. Pullup resistors may be required on some Flash pins. Refer to the Flash data sheet. 2. Flash signal names may vary slightly from those used in the diagram. Supported Devices The following devices are supported for implementation of the Flash Programmer: • LatticeXP™ • MachXO™ Supported devices for configuration through this design include any Lattice FPGA with serial or parallel support for conventional SRAM configuration. This includes: © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 an8077_01.1
  2. 2. Parallel Flash Programming Lattice Semiconductor and FPGA Configuration • LatticeSC™ and LatticeSCM™ • LatticeECP2™ and LatticeECP2M™ • LatticeECP™ and LatticeEC™ • LatticeXP • ORCA® 4 FPGAs • ORCA 4 FPSCs Note: Configuration from encrypted bitstreams for LatticeECP2/M 'S' series devices is currently not supported using the methods in this application note. For a list of supported parallel Flash devices, please refer to the latest version of ispVM® System. ispVM System can be downloaded free of charge at www.latticesemi.com. Programming the Flash Unlike some dedicated configuration devices, which can be reprogrammed in-circuit via IEEE 1149.1 compliant JTAG programming tools, standard Flash memories typically do not support JTAG programming. This design, in order to provide greater capability, provides a method for updating the Flash memory while the device is still in-cir- cuit. Flash programming using ispVM System software allows a unified programming environment. ispVM System con- verts the configuration data file into a set of instructions that are executed through the ispJTAG™ port. A small amount of additional logic in the FPGA Loader device increments the address and provides the necessary control signals, shown in Figure 2. Figure 2. FPGA Loader Flash Programming Block Diagram FLASH_ADDR Address Register Load/Increment FLASH_DATA Data Register FLASH_WE Control Signal FLASH_OE State Machine FLASH_CE JTAG State Machine ispJTAG Port FPGA Configuration The FPGA device is configured automatically at power-up. While the power is ramping up to the device, a power- on-reset is triggered, external configuration mode pins are sampled, the DONE and INIT pins are driven low, and the internal SRAM cleared. Once the device reaches the proper voltage threshold, the INIT pin is released and 2
  3. 3. Parallel Flash Programming Lattice Semiconductor and FPGA Configuration must be pulled up externally to allow the start of configuration. This process can also be initiated at any time by tog- gling the PROGRAMn pin. The FPGA supports several options for configuration, which can be broken down into two categories: parallel and serial. Parallel mode provides a byte-wide interface, while serial mode is based on a bit-wide data stream. For more details on FPGA configuration, refer to the corresponding Lattice technical note for the FPGA device of interest. Serial Mode In serial mode, the FPGA obtains its configuration data one bit at a time on DIN at every rising edge of CCLK. If additional FPGA devices are present, serial data will flow out of the DOUT pin to form a configuration daisy chain. Figure 3 shows a diagram for this mode. Figure 3. Serial Mode FPGA Signals Lattice FPGA Slave Serial CCLK DI DOUT To additional Configuration Slave Serial Device DONE FPGAs INITN PROGRAMN Parallel Mode Parallel configuration mode operates with a byte-wide data bus and some additional control signals. To write to the parallel sysCONFIG™ port, the WRITEn, CSn, and CS1n pins must all be asserted low. To facilitate multiple FPGA configuration in parallel mode, the CSOn pin is used to assert the chip select input of the next device. The parallel configuration connections are shown in Figure 4. 3
  4. 4. Parallel Flash Programming Lattice Semiconductor and FPGA Configuration Figure 4. Parallel Mode FPGA Signals INITN DONE D[0:7] CCLK Lattice FPGA Lattice FPGA Slave Parallel Slave Parallel CCLK CCLK D[0:7] D[0:7] DONE DONE INITN INITN BUSY BUSY CSON CSON WRITEN WRITEN CSN CSN CS1N CS1N PROGRAMN PROGRAMN PROGRAM BUSY WRITEN Implementation The FPGA Loader design is implemented using Lattice Semiconductor’s ispLEVER® design software. The design uses approximately 220 registers and 230 LUT4s. The design source code can be compiled using the ispLEVER design software to target the desired device with custom pin assignments. Table 1. Device Resource Utilization Design Top-level File (*.vhd, *.v) FFs1 LUTs1 Programmer Only flash_prog 180 150 Programmer + Serial Configuration flash_prog_load16_ss 230 230 Programmer + Parallel Configuration flash_prog_load16_sp 230 210 1. Approximate utilization with default configuration. Table 2. Netlist Files Target Device1 Programmer IP Netlist File LatticeXP flash_programmer.ngo MachXO flash_programmer_xo.ngo 1. FPGA loader device Design Fit Process using ispLEVER Requirements • ispLEVER 6.1 or greater with a valid license Procedure Note: This procedure assumes familiarity with the Lattice design software. For more information on using ispLEVER, please see the tutorials included within the help system. 4
  5. 5. Parallel Flash Programming Lattice Semiconductor and FPGA Configuration 1. Extract the files from the distribution zip file for the intended implementation. 2. Launch the ispLEVER design tool and create a new project in the location of the files extracted in step 1. Select the project type according to the desired use of VHDL or Verilog. 3. Select a supported device as the target. 4. Import the top-level file, according to desired function and HDL preference. For VHDL designs, the design hierarchy will show the ‘flash_programmer’ module represented as a red question mark as shown in Figure 5. Figure 5. ispLEVER Design Hierarchy Note: For VHDL, the flash_programmer and flash_programmer_xo modules are displayed in the design hierarchy as unknown entities. Provided that the appropriate .ngo file exists in the project directory, the design flow will prop- erly link the logic. 5. Launch the Design Planner to assign I/O types and pins for each of the signals. Timing preferences are also recommended. For example timing preferences, refer to the accompanying ‘preferences.txt’. 6. Execute the ‘Place and Route’ process to run the design flow. 7. To generate a programming file, execute the ‘Generate Data File’ process. Implementation Notes • When using 8/16 bit selectable Flash devices, 16-bit mode must be used during programming. Such Flash devices typically have a dedicated input pin (i.e. BYTE#) that should be asserted to the correct polarity during programming. After programming, either mode may be used for read access to the Flash device. • When 8-bit only devices are supported, the lower 8 bits (FLASH_DQ[7:0]) should be connected to the Flash data bus. • Only Flash devices that have uniform sector sizes are supported with sector erase functionality. Non-uniform 5
  6. 6. Parallel Flash Programming Lattice Semiconductor and FPGA Configuration (boot) sector devices are supported with an entire chip erase function. Flash devices with uniform sectors are strongly recommended. • The fastest programming speeds are achieved using the USB version of the Lattice ispDOWNLOAD® cable with a PC supporting USB2.0. • The FLASH_PROGRAMMER core and the ispTRACY™ Logic Analyzer cannot exist simultaneously in the same device. Each of these functions can be implemented with two independent functional bitstreams. Using ispVM to Program the Flash Device ispVM16.2 and later provides support for the Parallel Flash Programmer. 1. Scan the chain or manually insert the devices representing the JTAG chain. Any non-Lattice devices should be appropriately handled by specifying instruction register lengths or importing a BSDL, SVF, or ISC file. An example chain is shown in Figure 6. Figure 6. ispVM System 2. Double-click the device that will function as the FPGA Loader to edit the properties. The resulting window should appear as shown in Figure 7. 6
  7. 7. Parallel Flash Programming Lattice Semiconductor and FPGA Configuration Figure 7. Device Information Dialog 3. From the ‘Device Access Options’ selection, choose “Parallel Flash Programming”. This will immediately open the ‘Flash Programmer’ dialog box, as shown in Figure 8. Figure 8. Flash Programmer Dialog 4. Within the ‘CPLD or FPGA Device’ page, shown in Figure 9, set the following options: 7
  8. 8. Parallel Flash Programming Lattice Semiconductor and FPGA Configuration Figure 9. CPLD or FPGA Device Page FPGA Loader Application Specific Data File – Browse to the JEDEC or bitstream file created by ispLEVER. Operation – Select the appropriate programming option for the FPGA Loader device. If the device has already been configured with the correct file, the ‘Bypass’ operation can be used to skip this step. 5. Change to the Configuration Data Setup page, as shown in Figure 10, and browse to the data file to pro- gram into the Flash device. If targeting a single Lattice FPGA, the bitstream (.bit) file may be used. Other- wise, choose the file as one of the supported PROM formats. Figure 10. Configuration Data Setup Page 8
  9. 9. Parallel Flash Programming Lattice Semiconductor and FPGA Configuration 6. In the ‘Flash Device’ page, shown in Figure 11, the following options are available: Figure 11. Flash Device Page Flash Device – Choose the target Flash device. Starting Address – By default, the data will be loaded starting at address zero. Press the Load From File button to acquire this address from the data file. Ending Address – By default, this field will be set automatically in order to fit the entire data file into the Flash device. Data File Size - This field will be set automatically when the configuration file is specified in the previous step. To force a recalculation of this value, press the Load From File button. Operation – The desired operation to be performed on the target Flash device. Output File – A user-specified output file when the Operation is set to Read and Save. ‘Read and Save’ will read the Flash device contents and store the results in this file. 7. After the Flash device is selected, be sure to press the Load From File button. This will ensure the starting and ending addresses are adjusted properly. 8. Once all of the settings are specified, click the OK button to exit the Flash Programmer dialog box. The ispVM System chain now reflects the changes, as shown in Figure 12. 9
  10. 10. Parallel Flash Programming Lattice Semiconductor and FPGA Configuration Figure 12. ispVM System Chain with Flash Programmer Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com Revision History Date Version Change Summary February 2007 01.0 Initial release. 01.1 Updated to support non-S version of LatticeECP2/M device family only August 2007 under device support. 10
  11. 11. Parallel Flash Programming Lattice Semiconductor and FPGA Configuration Appendix A. 16-bit Flash to Slave Serial Configuration VHDL toplevel file flash_prog_load16_ss.vhd Verilog toplevel file flash_prog_load16_ss.v Flash interface Standard, 16-bit asynchronous FPGA interface Slave Serial Figure 13. FPGA Loader Logic Diagram for Flash to Serial Configuration Address Counter FLASH_ADDR[25:0] CCLK Control Shift FLASH _DATA [15:0] DIN Register INITn FLASH_RSTn DONE FLASH_CE FLASH_OE 11
  12. 12. Parallel Flash Programming Lattice Semiconductor and FPGA Configuration Figure 14. FPGA Loader to Slave Serial FPGA Configuration Signal Connections FPGA Loader Lattice FPGA To Additional Device Slave Serial Slave Serial FPGAs CCLK CCLK Flash DIN DIN DOUT Interface DONE DONE INITn INITn PROGRAMn Note: Master mode may also be used with applicable devices, where the clock source is from the FPGA. Only one FPGA should be designated as master, while any others connected in a daisy chain should be slaves. Configuration Speed The maximum allowed configuration frequency is dependent upon the Flash device used and the setup and clock- to-output times of the FPGA Loader device: • Flash access time, or address-to-data time (tFLASH). Standard parallel Flash devices are typically available in speeds from 60ns to 120ns. • FPGA Loader data input setup time requirement (tSU_DATA) • FPGA Loader delay from the clock input to the F_ADDRESS output (tCO_ADDRESS) Note: tSU and tCO timing can be found using the TRACE or Timing Analyzer tools within ispLEVER after implement- ing the design. Since the FPGA Loader uses a word look-ahead scheme, accesses to the Flash do not impose register-to-register timing restrictions on every clock. The Flash access is absorbed over 16 clock cycles, as reflected in the calculation below: tCO_ADDRESS + tFLASH + tSU_DATA -1 CCLKmax = 16 12
  13. 13. Parallel Flash Programming Lattice Semiconductor and FPGA Configuration Appendix B. 16-bit Flash to Slave Parallel Configuration VHDL toplevel file flash_prog_load16_sp.vhd Verilog toplevel file flash_prog_load16_sp.v Flash interface Standard, 16-bit asynchronous read FPGA interface 8-bit Parallel Figure 15. FPGA Loader Logic Diagram for Flash to Parallel Configuration FLASH_DATA[15:8] WRITEn CE D[7:0] FLASH_DATA[7:0] CE Address Counter FLASH_ADDR CE CCLK INITn FLASH_RSTn WRITEn DONE CSn CS1n 13
  14. 14. Parallel Flash Programming Lattice Semiconductor and FPGA Configuration Figure 16. FPGA Loader to Slave Parallel FPGA Configuration Signal Connections FPGA Loader Lattice FPGA Device Slave Parallel CCLK CCLK D[0:7] D[0:7] To Additional Slave Parallel WRITEn FPGAs WRITEn Flash CSn CSn CSOn Interface CS1n CS1n DONE DONE INITn INITn PROGRAMn Configuration Speed The maximum allowed configuration frequency is dependent upon the Flash device used and the setup and clock- to-output times of the FPGA Loader device: • Flash access time, or address-to-data time (tFLASH). Standard parallel Flash devices are typically available in speeds from 60ns to 120ns. • FPGA Loader data input setup time requirement (tSU_DATA) • FPGA Loader delay from the clock input to the F_ADDRESS output (tCO_ADDRESS) Note: tSU and tCO timing can be found using the TRACE or Timing Analyzer tools within ispLEVER after implement- ing the design. Since the FPGA Loader uses a word look-ahead scheme, accesses to the Flash do not impose register-to-register timing restrictions on every clock. The Flash access is absorbed over two clock cycles, as reflected in the calcula- tion below: tCO_ADDRESS + tFLASH + tSU_DATA -1 CCLKmax = 2 14

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