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9.5 High Speed Flash Memory and 1T-DRAM on Dopant Segregated ...
9.5 High Speed Flash Memory and 1T-DRAM on Dopant Segregated ...
9.5 High Speed Flash Memory and 1T-DRAM on Dopant Segregated ...
9.5 High Speed Flash Memory and 1T-DRAM on Dopant Segregated ...
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9.5 High Speed Flash Memory and 1T-DRAM on Dopant Segregated ...


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  • 1. High Speed Flash Memory and 1T-DRAM on Dopant Segregated Schottky Barrier (DSSB) FinFET SONOS Device for Multi-functional SoC Applications Sung-Jin Choi1, Jin-Woo Han1, Sungho Kim1, Dong-Hyun Kim1, Moon-Gyu Jang2, Jong-Heon Yang2, Jin Soo Kim3, Kwang Hee Kim3, Gi Sung Lee3, Jae Sub Oh3, Myeong Ho Song3, Yun Chang Park3, Jeoung Woo Kim3, and Yang-Kyu Choi1 1 EECS, KAIST, Daejeon, Korea, 2ETRI, Daejeon, Korea, 3National Nanofab Center, Daejeon, Korea Email:, Phone: +82-42-350-5477, Fax: +82-42-350-8565 ABSTRACT DEVICE FABRICATION A novel dopant segregated Schottky barrier (DSSB) FinFET The process sequence is summarized in Fig. 4. The process SONOS device is demonstrated in terms of multifunctioning in flow of the DSSB FinFET SONOS device is the same as that a high speed NAND-type Flash memory and capacitorless of our previous work [2] except for the gate spacers and the 1T-DRAM. In addition, a novel program mechanism that uses silicided S/D formation. Using a shallow implantation of energy band engineered hot electrons (EBEHE) energized by arsenic (As) after formation of gate spacers, we effectively sharp energy band bending at the edge of source/drain (S/D) is modulated the SB height by using the segregated dopants. proposed for a high speed Flash memory programming During the formation of the gate spacers, the S/D regions are operation. A short program time of 100ns and a low program recessed so that they subsequently provide a uniform S/D voltage of 12V yield a Vth shift of 3.5V and a retention time along the fin depth (vertical direction). This task is challenging exceeding 10years. For multifunctioning, the operation of a with only an S/D implantation and activation. Finally, the capacitorless 1T-DRAM is also demonstrated with a partially DSSB S/D was formed by means of nickel silicidation (NiSi) silicided DSSB in the same device. in a two-step RTP, which can minimize the lateral diffusion of INTRODUCTION NiSi. The SEM photograph in Fig. 5(a) shows a bird’s-eye Ever since multifunctional devices with a high performance view of the fabricated DSSB FinFET SONOS device. Fig. and embedded memories were proposed for SoC applications, 5(b), 5(c), and 5(d) are cross-sectional TEM images from such as SOONO and Unified-RAM on a single transistor [1, 2], various points of view of the DSSB FinFET SONOS device. there have been expectations of a reduction in process The device has a gate length of 220nm and a fin that ranges in complexity and chip cost. A primary goal in this work is to width from 30nm to 100nm. For the control group, we propose a novel multifunctioning device based on a DSSB fabricated a conventional FinFET SONOS device with a FinFET SONOS device with a high speed NAND-type diffused p-n junction was also fabricated. nonvolatile memory and capacitorless 1T-DRAM. Fig. 1 RESULTS AND DISCUSSIONS shows the schematics of a DSSB FinFET SONOS device. Fig. 6 shows the Ids-Vgs characteristics of the DSSB FinFET In general, the increasing density and program speed of SONOS device with a gate length (Lg) of 220nm and a fin NAND Flash memory have been challenging tasks because the width (Wfin) of 30nm. As shown in Fig. 7, a low parasitic diffusion-based S/D and Fowler-Nordeim (FN) tunneling resistance is achieved due to the metallic silicided S/D in the needed for program obstructed aggressive scaling and fast DSSB FinFET device. The DSSB FinFET with low parasitic program speed. We therefore demonstrate a fast program for resistance at the S/D is therefore expected to be a promising Flash memory with superior short-channel immunity in the candidate for a high performance device, especially with a FinFET SONOS structure. As shown in Fig. 2, a hot carrier short gate length. Moreover, as shown in Fig. 8, even though with high kinetic energy triggered by a sharp energy band at the thickness of gate oxide is thick due to the O/N/O the S/D enhances the speed of the nonvolatile memory. triple-layered structure, the short-channel effects are On the other hand, the SB-MOSFET has not been used for a effectively suppressed in the DSSB FinFET device. capacitorless 1T-DRAM due to difficulty of hole accumulation A. Nonvolatile memory characteristics at the floating body [3]. To benefit from the superiority of the Fig. 9 shows the novel EBEHE program and the typical FN SB-MOSFET in a capacitorless 1T-DRAM, we used a dopant erase characteristics of the DSSB FinFET SONOS device. segregation technique to develop a partial silicidation process Excellent program efficiency is achieved. The Vth shift of 4.5V at the S/D, which, as shown in Fig. 3, allows hole storage at and 3.5V was achieved with 1μs/12V and 100ns/12V for the floating body. program, respectively. And 100μsec/-14V was used for erase. The difference in the Vth shift between the DSSB FinFET 1-4244-2377-4/08/$20.00 ©2008 IEEE 223
  • 2. SONOS device and the conventional one for programming is 50ns and 100ns, respectively. The P/E states are clearly approximately 2.5V at a program time of 100ns. This result is distinguished in the DSSB FinFET SONOS device with the attributed to the hot carrier injection triggered by the sharp partially silicided S/D, whereas the P/E states for the fully band bending at the DSSB S/D junction edge, which results in silicided S/D are not clearly distinctive. The reason for this a larger Vth shift than in the conventional FinFET SONOS difference is that the accumulated hole can easily leak out to device with the same program voltage. In contrast, there is no the fully silicided S/D. One of the advantages of a significant difference in the erase characteristics between the capacitorless 1T-DRAM is that excess holes are retained in the DSSB FinFET SONOS device and the conventional one floating body during the P/E states. Consequently, a because of the same FN erase operation. However, nondestructive readout is feasible and saves the refresh process, unimproved erase characteristics can be circumvented by which can be required in a conventional DRAM (1T/1C BE-SONOS technology [4]. As shown in Fig. 10, a parallel structure). Fig. 18 shows a 70ms nondestructive readout of the shift among programmed states was found in the DSSB device fabricated DSSB FinFET SONOS device. Fig. 19 shows the but not in the conventional device. This difference implies that schematics of the capacitorless 1T-DRAM cell array. Note that the two-sided charge injection at the S/D prevails in the DSSB the cell architecture of the capacitorless 1T-DRAM is exactly FinFET SONOS device. Note on the other hand that an the same as that of NOR-type Flash memory. This sameness unwanted non-uniform charge injection by FN tunneling shows the feasibility of multifunctions such as Flash memory occurs in the conventional FinFET SONOS device, resulting in and DRAM operations, without the risk of changing the cell an oblique shift and degradation of the slope. Fig. 11 shows architecture. This multifunctioning device can therefore be the Vth distribution of both the program/erase (P/E). The large extended to embedded memory and a hybrid CMOS through Vth window of almost 5V is attractive for multilevel cell integration with a FinFET, Flash memory, and DRAM, where applications with a short programming time. Fig. 12 shows a the integration is based on the DSSB structure of SoC novel divided bit-line (BL) NAND array architecture that was applications. Moreover, DC stresses were applied to evaluate designed for the implementation of the EBEHE program. The how the Vth stability depends on the writing time, especially selected cell is programmed by simultaneously applying the because the use of impact ionization can degrade device ground bias for the top BL and the bottom BL. The word-line reliability. The extrapolation results in Fig. 20 show that the (WL) disturbance window, as shown in Fig. 13, is determined Vth shift is smaller than 0.1V after a 108 sec of DC stress. by a disturbed Vth of 1.5V in unselected cells. This reference CONCLUSIONS value means that unselected cells can tolerate more than 100 We propose a multifunctional DSSB FinFET SONOS device times of program operation (tPGM=1μs). A positive BL voltage and demonstrate its multi-functional characteristics for high is used in unselected cells because it can reduce the hot speed Flash memory with a novel NAND Flash architecture electron generation due to the reduced electric field at the edge and capacitorless 1T-DRAM with the partially silicided as well of the S/D. Thus, the increased BL voltage in the unselected as dopant segregated S/D in a single transistor. cells can enlarge the WL disturbance window. Fig. 14 shows In a Flash memory operation, hot electrons energized by an data retention results after the 1k P/E cycling and endurance energy band engineered at the edge of the S/D are used for a behavior. For a program time of 100ns, we found that, in fast program. The DSSB FinFET SONOS device not only comparison with the conventional FinFET SONOS device, the inherits the merit of Schottky-barrier FinFET through high DSSB FinFET SONOS device had a more rapid degradation of immunity of short-channel effect but also endows the high the retention characteristics as a result of the charge loss; this programming speed. A capacitorless 1T-DRAM operation was output can be attributed to the fact that the hot carriers degrade also achieved by utilizing the dopant segregated region in the tunneling oxide quality. Nevertheless, we can extrapolate the same device. These results confirm that the DSSB FinFET Vth window to be 2V after 10 years because of the high SONOS device has great potential for multifunctional SoC efficiency programming. The Vth window is estimated to be applications. 4V after 107 P/E cycles for a program time of 1μs and an erase time of 100μsec. These values ensure sufficient reliability. ACKNOWLEDGEMENT B. Capacitorless 1T-DRAM characteristics This work was supported by the National Research Program In Fig. 15, as evidence of hole accumulation, the kink effect for the 0.1-Terabit Nonvolatile Memory Development, is only observed in the DSSB FinFET SONOS device with a sponsored by the Ministry of Knowledge Economy. partially silicided S/D. A partially silicided S/D can be easily REFERENCES achieved by adjusting the deposited metal thickness during the [1] C.-W. Oh et al., Proc. VLSI Tech., p. 573, 2006. silicidation process. The program, erase, and read conditions [2] J.-W. Han et al., IEDM Tech. Dig., p.929, 2007. for the 1T-DRAM operation are summarized in Fig. 16. Fig. [3] M. Nishisaka et al., Jpn. J. Appl. Phys., part 1 37, 1295, 1998. 17 shows the P/E characteristics set by the P/E voltages for [4] H. T. Lue et al., IEDM Tech. Dig., p.547, 2005 224
  • 3. 1.78 (a) 0 x (b) (c) 1.6 Electric field (MV/cm) Barrier thermal or tunneled 1.2 Energy (Arb. Unit) Gate Max E-field (MV/cm) Hard mask Height, Injection of electron 0.8 O/N/O Φ BN O/N/O 1.76 Wfin Lg NiSi Hot electron NiSi e- e- Efn 0.4 Source Drain injection 0.0 Gate length (Lg) NiSi recessed source/drain Dopant segregated region NiSi (source) Extra Channel direction (nm) Dopant segregated region Buried oxide kinetic energy 1.74 Si substrate Segregated region 1.72 <Fast programming NAND flash> 0 x 10 15 10 16 10 17 10 18 10 19 10 20 3 Segregation doping conc. (/cm ) Fig. 1 : Schematics of the DSSB Fig. 2 : Schematic of high speed NVM operation for multifunctioning. (a) The hot electrons energized by a DSSB are used FinFET SONOS device. For to program a NVM application. Because of the hot electrons energized by the energy band engineered DSSB, a new multifunctioning memory, an O/N/O programming method for Flash memory is possible with low voltage and high speed. (b) A simulated band diagram in the structure and a partially silicided S/D S/D edge. Electrons injected from the S/D have extra kinetic energy, enabling high-speed low-voltage programming for are used on an SOI substrate. Flash memory operation. (c) Simulation data of an electric field caused by a concentration of segregated doping. (1) (2) (a) (b) Dopant segregated (100) SOI wafer X-X’ Channel implantation Gate in Fig. 3(a) Si Hard mask Fin Fin patterning Silicon NiSi Buried oxide layer Buried oxide layer X NiSi Impact NiSi X’ O/N/O and n+ poly-Si deposition ionization (Source) + NiSi Si substrate Si substrate Y Y’ (Drain) Gate formation Partially silicided layer Leak out (3) (4) Spacer formation Buried oxide Y-Y’ Gate Recessed O/N/O layer Spacer Gate Arsenic (5keV) implantation Si substrate in Fig. 3(a) Silicon Fin NiSi S/D Ni Silicidation (RTP, 2step annealing) As Dopant segregation Segregation + As Buried oxide layer Buried oxide layer Unreacted metal removal by SPM <Capacitorless 1T DRAM> Accumulation Segregation Si substrate Si substrate Fig. 3 : (a) Holes generated by impact ionization accumulate on the floating Fig. 4 : Flowchart of the DSSB FinFET SONOS device. In the silicidation body due to partially dopant segregation layer. This accumulation can enable process, a two-step RTP is used to reduce any overgrowth of NiSi or severe the operation of an 1T-DRAM. (b) In 1T-DRAM operation, holes accumulate lateral diffusion. Since SB height is effectively modulated by the dopant in a partially segregated layer. concentration, a shallow implantation (5keV) of As was applied. Lg Spacer a-a’ b-b’ Source Control S Control Spacer (a) (b) gate (c) (d) gate O 4 nm Recessed S/D Hard mask O/N/O Gate a b’ N 6 nm NiSi Si O 3 nm Si Fin b a’ S Drain Gate 50 nm Buried oxide 5 nm Fin channel Buried oxide Fig. 5 : The fabricated DSSB FinFET SONOS device: (a) A SEM image of the DSSB FinFET SONOS device, (b) A TEM image across the a-a’ direction in Fig. 5(a). The sidewall spacers are observed as shown in Fig. 5(b). The fabricated fin widths vary from 30nm to 100nm and the height of the fin is 75nm. (C) A TEM image of the O/N/O layer for Flash memory. (d) A TEM image across the b-b’ direction in Fig. 5(a). The recessed S/D is feasible for making a uniform S/D along the fin depth 10 -4 3.0 300 DSSB FinFET SONOS (a) (b) Circle : Conv. FinFET Parasitic resistance (kΩ μm) @ Voverdrive=1V 0.0 Lg = 220 nm 2.5 W = 30 nm Square : DSSB FinFET Drain current, Ids (A) -6 10 fin 250 Wfin = 30 nm Vds = 0.05 V -0.1 Solid : Wfin = 100 nm 2.0 SS (mV/dec) -8 Open : Wfin = 50 nm 10 O/N/O thickness NiSi -0.2 200 ΔVth (V) Channel Circle : Conv. FinFET 3nm/6nm/4nm 1.5 O/N/O = 3nm/6nm/4nm Square : DSSB FinFET -10 -0.3 Vds = 0.05 V 10 Solid : Wfin = 100 nm 150 Vth = 0.14 V 1.0 RNiSi Rinterface Rch SS = 78.9 mV/dec -0.4 Open : Wfin = 50 nm 10 -12 Rinterface 100 Vds = 0.05 V 0.5 O/N/O = 3nm/6nm/4nm Vds = 1 V RNiSi = 135 Ω μm -0.5 Vds = 0.05 V 10 -14 0.0 50 -2 -1 0 1 2 DSSB FinFET Conv. FinFET 200 240 280 320 360 200 240 280 320 360 Gate voltage, Vgs (V) Gate length, Lg (nm) Gate length, Lg (nm) Fig. 6 : The Ids-Vgs characteristics of Fig. 7 : The measured parasitic Fig. 8 : (a) The Vth roll-off characteristics of the DSSB FinFET SONOS device. the DSSB FinFET SONOS device. resistance (Rpara), where Rpara is These characteristics are attractive in terms of applying the DSSB FinFET normalized by Wfin. SONOS device to a scaled memory due to the high immunity of short-channel 1 effects (SCEs). (b) The subthreshold swing versus the gate length. The SCEs of ( R para , DSSB FinFET < ⋅ R para ,conv.FinFET ) 3 the DSSB FinFET SONOS device are superior to those of a conventional device. 225
  • 4. -4 (a)6 V / V = GND (b) 5 10 Program : VPGM = 12 V VERS = -11 V Program Erase Number of cell (Arb. Unit) S D -5 Threshold voltage, Vth (V) τPGM 4 10 VPGM = 12 V 5 τ Drain current, Ids (A) -6 =1 μs 3 10 PGM =100 ns -7 Fresh 4 10 Program/erase condition 2 VERS = -14 V "Parallel shift" ΔVth (V) -8 Program VPGM = 12 V for 1μs 10 3 2.9 V 1 Erase VERS = -14 V for 100μs -9 10 2 2.5 V 0 -10 10 τPGM = 100 ns -1 DSSB FinFET SONOS -11 1 VPGM = 9 V FN erase 10 -2 10 -12 Square : DSSB FinFET Square : DSSB FinFET 100 μsec erase 0 Circle : Conv. FinFET Circle : Conv. FinFET -3 -8 -7 -6 -5 -4 -3 -2 10 -13 10 -8 10 -7 10 -6 10 -5 10 -4 -3 10 10 -2 10 10 10 10 10 10 10 -1 0 1 2 3 4 5 6 7 0 1 2 3 4 5 Program time (sec) Erasing time (sec) Gate voltage, Vgs (V) Threshold voltage, Vth (V) Fig. 9 : (a) The characteristics of the EBEHE-program. Excellent programming Fig. 10 : Comparison of the Ids-Vgs Fig. 11 : The Vth distribution of the efficiency compared to the control group is obtained due to high speed EBEHE shift among various programmed EBEHE program and FN erase of the programming. Fast programming (Vth >4.5V) is demonstrated even at 1μs. (b) states. A two-sided injected charge DSSB FinFET SONOS device in The FN erase characteristics with different erasing voltages. produces a parallel shift of I-V. NAND operation. VBL1=GND VBL2=Vcc 6 Solid : VPGM = 12 V (a) 4 Programmed, VPGM = 12 V (b) 5 Programmed Threshold voltage, Vth (V) Threshold voltage, Vth (V) Selected Open : VPGM = 9 V 5 τPGM = 100ns transistor 3 4 VS = VD = 0V Program/Erase condition VWL1=Vpass 0V 2V 4 τPGM = 1μs 3 VPGM = 12 V for 1μsec ΔVth (V) 2 VERS = -14 V for 100μsec 3 WL disturb VWL16=+12V ΔVth = 2 V Disturb ΔVth 2 ΔVth = 3.9 V 0V 2V 2 =1V Erased after 10 years VWL32=Vpass 1 VERS = -14V for 100μsec after 10 cycles 7 Disturbance 1 Selected 1 transistor VS = VD Square : DSSB FinFET Erased 0 0 0 Circle : Conv. FinFET For VBL1=GND VBL2=Vcc = 0V 0 1 2 3 4 5 6 7 8 programming 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 0 1 2 3 10 10 10 10 10 10 10 10 10 10 4 5 6 7 8 9 10 10 10 10 10 10 10 10 10 Program time (sec) Retention time (sec) Cycles (#) Fig. 12 : A novel divided bit-line Fig. 13 : A WL disturbance window Fig. 14 : (a) Data retention characteristics after 1k P/E cycles. Even for short NAND architecture for the EBEHE for the EBEHE programming. A program times (100ns), a large Vth window is obtained due to the EBEHE programming. The ground bias of the positive S/D voltage can reduce the hot program. (b) The measured endurance characteristics of the DSSB FinFET bit line is applied to the EBEHE electron generation because of a SONOS device in Flash memory operation. programming. reduced electric field. 0.7 32 Vgs=0.2~1.4V, 0.3V step τPGM=50ns, τERS=100ns Drain current, Ids (mA/μm) 0.6 O/N/O=3nm/6nm/4nm Gate voltage, Vgs (WL) 28 Program : V = 1.8V, V =2V Source current (μA) gs ds 1.8 V 24 Read : Vgs=1.8V, Vds=0.3V 0.5 Erase : Vgs=1.8V, Vds=-2V 0.4 Kink Drain voltage, Vds (BL) 20 Patially silicided S/D 16 Fully silicided S/D 0.3 2V 0.2 12 0.3 V 0.1 8 Sensing margin Circle : Fully silicided S/D -2 V 0.0 4 Line : Partially silicided S/D 50 ns 100 ns 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Program Read Erase 0 250 500 750 1000 1250 1500 Drain voltage, Vds (V) Time (μs) Fig. 15 : The measured Ids-Vds curve. The kink Fig. 16 : The program, erase, and read bias Fig. 17 : The P/E characteristics of the 1T-DRAM effect caused by the accumulated holes in the conditions. The program time is 50ns and the operation in the DSSB FinFET SONOS device for floating body is observable only in a partially erase time is 100ns. multifunctioning. Two separated states are clearly silicided device. distinguishable but only in the partially silicided case. 0 12 10 DSSB FinFET SONOS Vds DC stress at Vg=1.8V, Vd=2V 11 BL0 BL1 BL2 BL3 Source current, Is (μA) Program : 2V Read : 0.3V -1 10 Erase : -2V 10 9 Programmed WL0 ΔVth (V) 8 Sensing WL1 10 -2 margin of Vgs=1.8V 7 3.3 μA at 70msec WL2 -3 6 10 WL3 5 Erased -4 4 10 1 2 3 4 5 6 7 0 10 20 30 40 50 60 70 80 10 10 10 10 10 10 10 ON OFF CSL DC stress time (sec) Time (ms) Fig. 18 : Reading current characteristics. The Fig. 19 : The Cell layout for the 1T-DRAM Fig. 20 : The Vth shift after DC stress at the 1T-DRAM nondestructive readout ensures a sensing margin operation. This cell layout is exactly the same program voltage in the DSSB FinFET SONOS device. of 3.3 μA for 70ms. as that of the NOR Flash. No significant Vth shift is observed even after 104 s. 226