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© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
© 2001 ® Embedded Processor Solutions 2
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© 2001 ® Embedded Processor Solutions 2

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  • Updated – SPI, reference designs
  • *look
  • Is Mstep still enabled?
  • ref_32_system_quartus_ss.bmp - updated
  • Replace top screen shot with nios_cpu_select_ss.bmp or put it on the next page…
  • nios_cpu_select_ss.bmp
  • address_bus_size_ss.bmp - updated
  • reg_file_size_ss.bmp - updated
  • For shifter, see last slide. For multiplication operation stuff, use this screen shot: hardware_mult_ss.bmp - updated
  • Replace with ref_32_system_builder_ss.bmp or blank_system_builder_ss.bmp
  • uart_ss.bmp - updated
  • ext_ram_ss.bmp - updated
  • system_custom_sdk_ss.bmp
  • system_boot_rom_page_ss.bmp - updated
  • system_building_ss.bmp - updated
  • Updated – EPM 7064 We must speak Alterish
  • The Nios software development kit contains the components needed to do software development with a Nios system. The SDK contains the GNUPro toolkit for Nios, utilities that aid the developer in compilation, testing, and debug of code as well as extensive documentation for the GNUPro tools.
  • Transcript

    • 1. Embedded Processor Solutions
    • 2. Altera ® SOPC Innovation 2000 1999 High-Density, Feature-Rich SOPC Delivery Vehicle Methodology for SOPC Development Building Blocks & Design Reuse in SOPC Applications Processor Core & Compiler Licensees Wide-Open Royalty-Free Business Model Embedded Processor Solutions
    • 3. Altera ® SOPC Innovation 2001 Complete SOPC Design Environment ACEX TM 1K APEX TM 20K/E/C FLEX TM 10K Expansive Device Selection EXCALIBUR TM XA EXCALIBUR TM XM GNUPro Development Tools uCLinux
    • 4. Excalibur Nios Flexibility & Scalability ACEX™ EP1K100 APEX EP20K200E Excalibur XA10 Low-Cost Embedded Processor High-Performance Custom DSP Multi-Processor System 75K Gates Available 150K Gates Available 500K Gates Available DSP Excalibur ARM 922T + Memory ESB ESB ESB ESB ESB ESB ESB ESB ESB ESB ESB ESB
    • 5. Nios Soft Core Embedded Processor
    • 6. Excalibur Nios Embedded Processor Core <ul><li>Configurable Soft Core Processor </li></ul><ul><li>32-Bit Pipelined RISC Architecture </li></ul><ul><ul><li>16-Bit Instructions </li></ul></ul><ul><ul><li>Most Instructions Take 1 Clock </li></ul></ul><ul><li>Large Internal Register File </li></ul><ul><li>Configurable Data Path </li></ul><ul><ul><li>16-bit (1100 LEs) </li></ul></ul><ul><ul><li>32-bit (1700 LEs) </li></ul></ul><ul><li>Dynamic Bus Sizing </li></ul><ul><li>30 to 80 MIPS Performance </li></ul>Timer IRQ PBM CPU UART Your Design Here FLASH SRAM Serial Port Altera PLD Volume Price Point $5 for 50 MIPs 12% of EP20K200E
    • 7. Nios RISC Processor Block Diagram <ul><li>Standard RISC Components </li></ul><ul><li>Fully-Synchronous Interface </li></ul>
    • 8. Windowed Register File <ul><li>Common Technique Used by High-Performance CPUs </li></ul><ul><ul><li>Provides Fast Subroutine Calls </li></ul></ul><ul><li>Up to 512 General-Purpose Registers </li></ul><ul><li>Movable Window With Access to 32 Registers </li></ul><ul><ul><li>24 Register Window (Movable) </li></ul></ul><ul><ul><li>8 Global Registers (Fixed) </li></ul></ul><ul><li>Automatically Used by C Compiler </li></ul>
    • 9. Bit Shift Speed <ul><li>Provides Multiple Bit Shift in a Single Clock Cycle </li></ul><ul><ul><li>Increments of up to 3, 5, 7, 15, or 31 Bits Per Clock </li></ul></ul><ul><li>Example: </li></ul><ul><ul><li>Bit Shift Speed Set to 7: </li></ul></ul><ul><ul><li>i &lt;&lt; 9; /* Shift Left by 9 Bits */ </li></ul></ul><ul><ul><li>Executes in 2 Clocks </li></ul></ul>0 Clock 1 (Shift 7 bits) Clock 2 (Shift 2 bits)
    • 10. Multiplication Options <ul><li>Software </li></ul><ul><ul><li>Uses GNU Math Library for Multiply Operations </li></ul></ul><ul><li>MSTEP </li></ul><ul><ul><li>Hardware Multiplier - Option 1 </li></ul></ul><ul><ul><li>One-Bit Per Clock Multiply </li></ul></ul><ul><ul><li>Improvement of ~ 4X over Software Multiplication Routines </li></ul></ul><ul><li>MUL </li></ul><ul><ul><li>Hardware Multiplier - Option 2 </li></ul></ul><ul><ul><li>16 x 16  32 in 2 Clocks </li></ul></ul>Multiplier None (Software) MSTEP MUL Clock Cycles 16x16&gt;32 Clock Cycles 32x32&gt;32 Additional Logic Elements Used 80 18 2 0 +200 +400 250 80 16
    • 11. Development Tool Flow
    • 12. Nios System Builder Software <ul><li>Processor Design </li></ul><ul><ul><li>(Verilog / VHDL) </li></ul></ul><ul><li>Simulation Test Bench </li></ul><ul><li>C Header files </li></ul><ul><li>Custom Library </li></ul><ul><li>Boot monitor </li></ul>Synthesis Place &amp; Route Cygnus/Red Hat GNUPro JTAG Serial Ethernet <ul><li>User Design </li></ul><ul><li>Purchased IP </li></ul>Executable Code Hardware Configuration File Configure Processor Select Peripherals Generate Hardware Software Download &amp; Debug <ul><li>User Code </li></ul><ul><li>S/W Libraries </li></ul><ul><li>RTOS </li></ul>Peripheral Library Altera PLD
    • 13. Nios System Builder Software <ul><li>Generate: </li></ul><ul><ul><li>Hardware - HDL Files </li></ul></ul><ul><ul><li>Software - Custom Library </li></ul></ul><ul><ul><li>Simulation - Test Bench </li></ul></ul>Nios System Builder CPU Nios HDL Peripheral HDL Custom Library Peripheral Peripheral Routine
    • 14. Excalibur Development Kit <ul><li>Altera 32-Bit RISC CPU </li></ul><ul><li>Peripherals </li></ul><ul><ul><li>UART </li></ul></ul><ul><ul><li>Timer </li></ul></ul><ul><ul><li>Serial Peripheral I/F (SPI) </li></ul></ul><ul><ul><li>Parallel I/O (PIO) </li></ul></ul><ul><ul><li>Memory I/F </li></ul></ul><ul><ul><li>Generic Port I/F </li></ul></ul><ul><ul><li>On-Chip Bus </li></ul></ul><ul><li>Development Board </li></ul><ul><ul><li>Reference Designs </li></ul></ul><ul><li>Development Tools </li></ul><ul><ul><li>Quartus Excalibur Edition </li></ul></ul><ul><ul><li>LeonardoSpectrum </li></ul></ul><ul><ul><li>FPGA Express </li></ul></ul><ul><ul><li>Cygnus GNUPro </li></ul></ul>Excalibur Development Kit Featuring Nios $995
    • 15. Software Generation <ul><li>GNUPro C Development Kit </li></ul><ul><ul><li>Compiler </li></ul></ul><ul><ul><li>Assembler </li></ul></ul><ul><ul><li>Linker </li></ul></ul><ul><ul><li>Debugger </li></ul></ul><ul><ul><li>Nios Software Libraries </li></ul></ul><ul><li>Nios Development Utilities </li></ul><ul><ul><li>Compile, Assemble, Link </li></ul></ul><ul><ul><li>Download to SRAM and Flash </li></ul></ul><ul><ul><li>Disassemble Executable Code </li></ul></ul><ul><ul><li>Prepare Executable for Boot ROM </li></ul></ul><ul><li>Example Code (C &amp; Assembly) </li></ul><ul><ul><li>Peripheral I/O </li></ul></ul><ul><ul><li>Interrupt Service Routines </li></ul></ul>Cygnus GNUPro Toolkit
    • 16. System Reference Design
    • 17. Nios Development Board
    • 18. Reference Design Block Diagram
    • 19. Nios Software Development Utilities <ul><li>BASH: Standard UNIX-like Command Line Shell </li></ul><ul><li>Nios Development Utilities </li></ul><ul><ul><li>nios-build: Compile, Assemble &amp; Link </li></ul></ul><ul><ul><li>nios-run: Download Executable &amp; Run </li></ul></ul><ul><ul><li>srec2flash: Create Flash-bootable Code </li></ul></ul><ul><li>Generic UNIX Utilities Such As: </li></ul><ul><ul><li>Make: make </li></ul></ul><ul><ul><li>Concatenate: cat </li></ul></ul>
    • 20. Creating an SOPC Hardware Design
    • 21. Run Quartus <ul><li>Default Design: nios_reference32 </li></ul>
    • 22. Adding a Nios Processor <ul><li>Double-Click the Schematic </li></ul><ul><li>Choose: MegaWizard Plug-In Manager... </li></ul><ul><li>Create New Custom Megafunction Variation </li></ul>
    • 23. Configure a Nios Processor <ul><li>File Type: Verilog HDL </li></ul><ul><li>Output File Name: nios </li></ul>
    • 24. <ul><li>Processor Architecture </li></ul><ul><ul><li>ALU, Registers, Data &amp; Address Bus </li></ul></ul><ul><ul><ul><li>16-Bit </li></ul></ul></ul><ul><ul><ul><li>32-Bit </li></ul></ul></ul>Configure a Nios Processor
    • 25. <ul><li>Address Bus Width </li></ul>Configure a Nios Processor
    • 26. <ul><li>General-Purpose Register File Size </li></ul><ul><ul><li>128, 256, or 512 Registers </li></ul></ul><ul><ul><li>Uses Embedded System Blocks (ESB) </li></ul></ul><ul><li>Internal Shifter Speed </li></ul><ul><ul><li>Maximum Number of Bits </li></ul></ul><ul><ul><li>Shifted in a Single Clock </li></ul></ul>Configure a Nios Processor ESB Usage
    • 27. <ul><li>Multiplication Options </li></ul><ul><ul><li>None </li></ul></ul><ul><ul><ul><li>Software Math Library </li></ul></ul></ul><ul><ul><ul><li>No Additional Logic </li></ul></ul></ul><ul><ul><li>MSTEP </li></ul></ul><ul><ul><ul><li>1-bit per Clock </li></ul></ul></ul><ul><ul><ul><li>Adds ~200 LEs </li></ul></ul></ul><ul><ul><li>MUL </li></ul></ul><ul><ul><ul><li>16 x 16  32 in 2 Clocks </li></ul></ul></ul><ul><ul><ul><li>Adds ~400 LEs </li></ul></ul></ul>Configure a Nios Processor
    • 28. Nios System Builder <ul><li>Displays System Configuration </li></ul><ul><li>Add Peripheral Content </li></ul>
    • 29. UART Peripheral
    • 30. <ul><li>Peripheral Name: uart1 </li></ul><ul><li>Type of Peripheral: </li></ul><ul><ul><li>Inside Nios System Module </li></ul></ul><ul><ul><li>UART (RS-232 serial port) </li></ul></ul>Adding a UART Peripheral
    • 31. Timer Peripheral
    • 32. Timer Peripheral <ul><li>32-Bit Interval Timer </li></ul><ul><ul><li>Counts Down to 0 from Preset Value </li></ul></ul><ul><ul><li>16-Bit Peripheral (Compatible with Nios-16) </li></ul></ul><ul><ul><li>Two 16-Bit Registers (High / Low Half-Word) </li></ul></ul><ul><li>Polled Operation </li></ul><ul><ul><li>Periodically Read Coherent “Snapshot” of Counter Value </li></ul></ul><ul><li>Interrupt Operation </li></ul><ul><ul><li>Generate a Single (Mask-able) Interrupt on Time Out </li></ul></ul><ul><li>Uses Single Master Clock Input (Clk) </li></ul>
    • 33. Parallel I/O (PIO) Peripheral
    • 34. PIO Peripheral <ul><li>1 to 32-bit Parallel I/O Port </li></ul><ul><ul><li>Input Only </li></ul></ul><ul><ul><li>Output Only </li></ul></ul><ul><ul><li>Bi-directional Port </li></ul></ul><ul><ul><ul><li>On-chip: Separate Ports for Input &amp; Output </li></ul></ul></ul><ul><ul><ul><li>Off-chip: Tri-State Control </li></ul></ul></ul><ul><li>Edge Detection on Inputs </li></ul><ul><li>Interrupt Generation </li></ul><ul><ul><li>Mask-able </li></ul></ul><ul><ul><li>IRQ Source </li></ul></ul><ul><ul><ul><li>Input Level </li></ul></ul></ul><ul><ul><ul><li>Edge Detection Register </li></ul></ul></ul>
    • 35. On-Chip Memory
    • 36. On-Chip Memory <ul><li>Configure as ROM or RAM </li></ul><ul><li>Uses Embedded System Blocks (ESB) </li></ul><ul><li>Can Be Initialized With Boot Code </li></ul><ul><ul><li>GERMS Monitor Code Included (Source and Executable) </li></ul></ul><ul><ul><li>Boot Code Development Utility (srec2mif) </li></ul></ul><ul><ul><ul><li>Converts Compiler Output (srec) to APEX ROM Format (mif) </li></ul></ul></ul>
    • 37. Serial Peripheral Interface (SPI)
    • 38. SPI Port <ul><li>Full Duplex, Synchronous Serial Interface </li></ul><ul><ul><li>Interface to: </li></ul></ul><ul><ul><ul><li>A/D, D/A </li></ul></ul></ul><ul><ul><ul><li>Microcontrollers </li></ul></ul></ul><ul><ul><ul><li>Serial EPROM </li></ul></ul></ul><ul><li>3-Wire Serial Communications Bus With Slave Select </li></ul><ul><ul><li>Master Out Slave In - MOSI </li></ul></ul><ul><ul><li>Master In Slave Out - MISO </li></ul></ul><ul><ul><li>SPI Clock - SCLK </li></ul></ul><ul><ul><li>Slave Select - SS_n (Optional) </li></ul></ul><ul><li>Master or Slave Operation </li></ul><ul><li>Supports Up to 16 Slave Devices </li></ul><ul><li>Programmable Word Size (1 to 16 bits) </li></ul><ul><li>Programmable Delay Slot (Enable-to-Active) </li></ul>
    • 39. Ethernet Interface
    • 40. Ethernet Port <ul><li>10baseT External MAC/Phy Device </li></ul><ul><ul><li>ISA Bus Interface </li></ul></ul><ul><ul><li>Supports All Programmable Logic Device Families </li></ul></ul><ul><li>Includes TCP/IP Stack </li></ul><ul><ul><li>Library of C Routines </li></ul></ul>Nios CPU Avalon Bus ISA Bus Nios System Module External MAC/Phy I/O I/O I/O I/O Altera PLD
    • 41. User-Defined Interface
    • 42. User-Defined Interface <ul><li>Interface to Other Peripherals </li></ul><ul><ul><li>On-Chip &amp; Off-Chip </li></ul></ul><ul><li>Configures Busses and Timing </li></ul><ul><li>Adds Port Signals to Design </li></ul>Nios CPU Avalon Bus User I/F Nios System Module External Device I/O I/O I/O I/O Altera PLD
    • 43. External Memory Interface
    • 44. Adding a Memory Interface: SRAM <ul><li>Peripheral Name: sram </li></ul><ul><li>Type of Peripheral: </li></ul><ul><ul><li>Outside Nios System Module </li></ul></ul><ul><ul><li>32-Bit SRAM (256Kbytes In two IDT71V016 chips) </li></ul></ul>
    • 45. System Configuration
    • 46. System Configuration <ul><li>Main Program Memory </li></ul><ul><ul><li>Code Execution </li></ul></ul><ul><li>Main Data Memory </li></ul><ul><ul><li>Variables &amp; stack </li></ul></ul><ul><li>Host Communication </li></ul><ul><ul><li>Monitor STDIO </li></ul></ul><ul><li>Debug Communication </li></ul><ul><ul><li>GDB Port </li></ul></ul><ul><li>Boot ID Message </li></ul><ul><ul><li>Monitor Prints at Start-up </li></ul></ul>
    • 47. System Configuration <ul><li>Boot Device </li></ul><ul><ul><li>Optional Offset </li></ul></ul><ul><li>Interrupt Vector Table </li></ul><ul><ul><li>Optional Offset </li></ul></ul><ul><li>Highest Performance Bus </li></ul><ul><ul><li>Fastest Access </li></ul></ul><ul><li>Synthesis Target Family </li></ul><ul><ul><li>APEX </li></ul></ul><ul><ul><li>FLEX 10K </li></ul></ul><ul><ul><li>ACEX </li></ul></ul><ul><ul><li>Mercury </li></ul></ul><ul><ul><li>Excalibur ARM </li></ul></ul><ul><ul><li>Excalibur MIPS </li></ul></ul>
    • 48. Generate the Design <ul><li>Software Development Kit (SDK) </li></ul><ul><ul><li>Header File </li></ul></ul><ul><ul><ul><li>Address Map </li></ul></ul></ul><ul><ul><ul><li>Peripheral Structures </li></ul></ul></ul><ul><ul><li>Custom Library </li></ul></ul><ul><ul><li>Monitor Code </li></ul></ul><ul><li>Hardware Design </li></ul><ul><ul><li>HDL Source Files </li></ul></ul><ul><li>Synthesis </li></ul><ul><ul><li>EDIF Netlist With HDL “Wrapper” </li></ul></ul><ul><ul><li>Test Bench </li></ul></ul>
    • 49. Configuring The Development Board
    • 50. Nios Hardware Configuration Process <ul><li>Single Image Flash </li></ul><ul><ul><li>APEX Hardware Configuration </li></ul></ul><ul><ul><ul><li>Factory Image </li></ul></ul></ul><ul><ul><ul><li>User Image </li></ul></ul></ul><ul><ul><li>User Software </li></ul></ul><ul><li>APEX Configured from Flash </li></ul><ul><ul><li>EPM7064 Configures APEX from Flash </li></ul></ul><ul><ul><li>During Configuration, EPM7064: </li></ul></ul><ul><ul><ul><li>Loads “User” APEX Image </li></ul></ul></ul><ul><ul><ul><li>If Failure, Loads “Factory” APEX Image </li></ul></ul></ul>User APEX Image User Software 1Mb Flash APEX ROM Data Control 7064 Factory APEX Image Address
    • 51. Nios Processor Boot Process <ul><li>Boots from “Reset” Address </li></ul><ul><ul><li>Default Reset Address 0x0000 </li></ul></ul><ul><ul><ul><li>On-Chip ROM </li></ul></ul></ul><ul><ul><ul><li>512 16-Bit Instructions </li></ul></ul></ul><ul><ul><ul><li>Contains GERMS Monitor </li></ul></ul></ul><ul><li>During Boot </li></ul><ul><ul><li>Monitor Checks User Software Space </li></ul></ul><ul><ul><ul><li>Runs Code Found at Address 0x140000 </li></ul></ul></ul>SRAM 256Kb Data Address 1Mb Flash APEX ROM Factory APEX Image User APEX Image User Software 140000
    • 52. Software Development with GNUPro for Nios
    • 53. GERMS Monitor <ul><li>Monitor Program Runs from On-Chip ROM </li></ul><ul><li>Communicates to Host Via Serial Port (or Ethernet) </li></ul><ul><li>Basic Development Facilities: </li></ul><ul><ul><li>Download Code </li></ul></ul><ul><ul><li>Burn Flash </li></ul></ul><ul><ul><li>Examine/Modify Memory </li></ul></ul><ul><ul><li>Run Programs </li></ul></ul>Serial
    • 54. Nios SDK &amp; HDK Files and Folders
    • 55. Nios SDK Contents <ul><li>GNUPro Toolkit for Nios: &lt;drive:&gt;cygwin </li></ul><ul><ul><li>Compiler, linker, etc. </li></ul></ul><ul><li>Nios tools: usrAlteraExcaliburNios-SDKin </li></ul><ul><ul><li>nios-build </li></ul></ul><ul><ul><li>nios-run </li></ul></ul><ul><ul><li>nios-elf-gdb </li></ul></ul><ul><li>GNUPro Documentation: cygwinhtml… </li></ul><ul><ul><li>Extensive Documentation for: general, compiler, debug, libraries, and utilities </li></ul></ul><ul><ul><li>html format </li></ul></ul>
    • 56. GNU Debugger (GDB)
    • 57. GNU Debugger <ul><li>Code download </li></ul><ul><li>Run control </li></ul><ul><li>Break points </li></ul><ul><li>Watch points </li></ul><ul><li>Memory examination and modification </li></ul>
    • 58. GDB Operation Debug Monitor Serial Connection <ul><li>Debugger Runs on Host </li></ul><ul><ul><li>PC or UNIX Platform </li></ul></ul><ul><li>Debug Monitor Runs on Target </li></ul><ul><ul><li>Interprets Commands From Host </li></ul></ul><ul><ul><li>Controls the Target Application </li></ul></ul><ul><li>Serial Link to Between Host and Target </li></ul><ul><ul><li>RS-232 and Ethernet </li></ul></ul>Debugger
    • 59. Nios Development Kit Add-On Packages
    • 60. Ethernet Development Kit <ul><li>Supports Wide Range of Applications </li></ul><ul><ul><li>Factory Floor Automation </li></ul></ul><ul><ul><li>Basic Ethernet Connectivity </li></ul></ul><ul><ul><li>Internet Upgradeable Hardware </li></ul></ul><ul><li>Supports All PLD Families </li></ul><ul><li>Development Board </li></ul><ul><ul><li>External 10Mbyte MAC/Phy </li></ul></ul><ul><ul><li>Support for 2 Ports </li></ul></ul><ul><li>Software </li></ul><ul><ul><li>TCP/IP Stack </li></ul></ul><ul><li>Reference Design </li></ul><ul><ul><li>Hardware (Quartus™ Development Tool Project) </li></ul></ul><ul><ul><li>Software (Web Server Application) </li></ul></ul><ul><li>Available July 2001 </li></ul><ul><li>Price $495 </li></ul>
    • 61. Linux Development Kit <ul><li>Open-Source uCLinux Operating System </li></ul><ul><li>Development Kit Contents </li></ul><ul><ul><li>uCLinux Source Code </li></ul></ul><ul><ul><li>Host Daughter Board </li></ul></ul><ul><ul><li>SDRAM Controller Core </li></ul></ul><ul><ul><li>SDRAM / Flash Memory Module </li></ul></ul><ul><ul><li>Ethernet Development Kit </li></ul></ul><ul><ul><li>Reference Design </li></ul></ul><ul><ul><ul><li>Hardware (Quartus Project) </li></ul></ul></ul><ul><ul><ul><li>Software (Web Server Application) </li></ul></ul></ul><ul><li>Available July 2001 </li></ul><ul><li>Price $2,495 </li></ul>

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