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SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
SW Synthesis from UML/MARTE
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SW Synthesis from UML/MARTE

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System-level specifications are the key entry point to many design flows, as well as the golden reference model throughout the design lifecycle. As such, their quality dramatically impacts the …

System-level specifications are the key entry point to many design flows, as well as the golden reference model throughout the design lifecycle. As such, their quality dramatically impacts the potential quality of the designed product. Specifications have to expose sufficient parallelism and orthogonally capture computation and communication to allow exploring a wide range of target platforms. On top of functional accuracy to capture the designer’s intent, they have to be expressive enough to allow extracting performance requirements and describe system-wide constraints (e.g. application quality metrics).
In this presentation at the ASP-DAC 2014 Tutorial "High-Level Specifications to Cope With Design Complexity", organized by Prof. Gunar Schirner, opportunities and methods to describe, simulate and automatically generate the SW stacks on heterogeneous platforms using UML/MARTE are highlighted.

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  • 1. Modeling and SW Synthesis for Heterogeneous Embedded Systems in UML/MARTE Tutorial SD1: High-Level Specifications to Cope With Design Complexity Hector Posadas, Pablo Peñil, Alejandro Nicolás, Eugenio Villar University of Cantabria Spain p
  • 2. Motivation  Design D i productivity gap d ti it  Raising the abstraction level  Multi-Processing & Heterogeneous platforms H t l tf  Increasing SW content  SW centric SW-centric design methodologies Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 2
  • 3. Usual SW development flow A M  Architectural Design  HW/SW platform  Architectural mapping  Ad/Hoc SW development N1  System calls  Communication functions  I/O functions & drivers B N2 OS2 OS1 GPU  Verification & Debug  DSP Costly fixing of wrong design decisions Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 3
  • 4. Usual SW development flow  Lack of reusability  Ad hoc Ad-hoc  Large code A M N1 B N2 re-engineering effort OS3 Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore OS2 OS1 GPU DSP January 20, 2014 4
  • 5. Outline    Introduction I t d ti State of the Art The PHARAON approach  Design g Flow  Modeling Methodology  SW Synthesis  Conclusions Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 5
  • 6. Introduction  Model-Driven Architecture (MDA)  High-abstraction High abstraction level  Mature SW engineering methodology  UML language  Application to embedded systems design Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 6
  • 7. Introduction  Why UML?  Natural way to capture system architecture  Standard way M B N2 N1 N.P Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore A N.O January 20, 2014 7
  • 8. Introduction  Why UML?  Natural way to capture system architecture  Standard way  UML language  Semantics   lacks What is each component? What kind or interaction each link actually means?  Domain-specific p  p profiles UML/MARTE Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 8
  • 9. Introduction  MARTE  Standard    UML profile for real time embedded systems real-time Platform-Independent Model (PIM) Platform Description Model (PDM) Platform-Specific Model (PSM)  Rich semantics content  Single-source approach Analysis Simulation Verification Parallelization Performance Analysis Optimization Architectural Mapping Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore System Synthesis January 20, 2014 Design-Space g p Exploration 9
  • 10. State of the Art State-of-the-Art  Discussion  System  Methods based on specific MoCs and/or profiles    SW     modeling in MARTE Requiring additional semantics q g Non-standard Synthesis Commercial code generation available Limited support for heterogeneity Limited flexibility for different architectural mappings Limited support for the MARTE semantics Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 10
  • 11. PHARAON Single Source Design Flow Single-Source Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 11
  • 12. PHARAON Single Source Design Flow Single-Source S i Scenarios C/ C++ C PIM (App) Architectural Mappings HW/SW Platform M2T Tools SW Synthesis ( y (SWSyn) y ) + Compilers Linkers SW stacks HW HW Accelerators HW Accelerators HW Accelerators Accelerators CPUs/DSPs/ASIPs GP-GPUs Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 12
  • 13. PHARAON Modeling Methodology  Main features M i f t  MDD  concepts Separation of Concerns  CBE: Component-Based Engineering approach  SW centric i  Standard  MARTE profile fil Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 13
  • 14. PHARAON Modeling Methodology  Data T D t Types for Communication Interfaces f C i ti I t f  Primitive Types    Data Bit Arrays Arrays Structures Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 14
  • 15. PHARAON Modeling Methodology  Component model  Hierarchical functional encapsulation  Ports  provided or required C2 C2.1 C2.2 C2.3 Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 15
  • 16. PHARAON Modeling Methodology  Component Interfaces C2 C2.1 C2.2 C2.3 Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 16
  • 17. PHARAON Modeling Methodology  Component model  Interfaces   sequential, guarded or concurrent, Max. threads available argument sizes (data splitting), Num. of incoming channels C2 C2.1 C2.2 C2.3 Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 17
  • 18. PHARAON Modeling Methodology  Component model  Channels    manage communications BlockingFunctionCall, BlockingFunctionReturn, both or none Timeout Priority C2 C2.1  C2.2 Buffer Size  ResMult Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore C2.3 January 20, 2014 18
  • 19. PHARAON Modeling Methodology  The Platform Description Model  HW/SW  Software Components   Components using MARTE stereotypes OS, HdS, Drivers, … Hardware Components  Processors, Memories, Buses, Custom HW, I/O Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 19
  • 20. PHARAON Modeling Methodology  Platform-Specific Model  Memory spaces mapped to platform resources  Mapping of functional components  to memory spaces and/or platform resources Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 20
  • 21. PHARAON Modeling Methodology  Architectural Design  Code reuse and/or development p  platform independent  HW/SW platform  Architectural mapping  SW Synthesis  Fast design optimization Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 21
  • 22. SW Synthesis   System heterogeneity Full support for  any architectural mapping decided for each component  any specific processing resource selected  any processing resource type  any memory space  any OS used by the processing resource  any communication i f i ti infrastructure t t Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 22
  • 23. SW Synthesis  Functional synthesis  One executable per memory-space memory space  Platform-Independent (C/C++) code   Highest reusability Non-recommended explicit calls to platform services     communication, concurrency, etc. Platform services should derived from the UML/MARTE model POSIX and/or OpenMP as alternatives Static execution flows  <<SwSchedulableResource>> Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 23
  • 24. SW Synthesis  Functional synthesis  Platform-Specific Platform Specific    code PlatformIndependent C code OpenCL/GL code for GPU Optimized C code for DSPs OpenCL/GL for GPUs OpenMP for SMPs… Configuration Original 908.28 sec 572.92 sec ARM-NEON 325.81 sec 255.28 sec ARM+DSP blocking call 206.01 206 01 sec 193.45 193 45 sec ARM+DSP non-blocking call 895.98 sec 431.68 sec ARM-NEON+DSP ARM NEON+DSP non-blocking call 247.93 sec 215.96 sec C3 Optimized Code ARM DSP optimized C code Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore Memory Space OS SMP node GPU DSP Communication Infrastructure January 20, 2014 24
  • 25. SW Synthesis  Communication synthesis  Essential activity in heterogeneous SW synthesis  Client-Server paradigm  Dependent on the architectural mapping Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 25
  • 26. SW Synthesis  Communication synthesis  Architectural    Same memory space Same OS Different processing nodes  Benefits      mapping / Drawbacks Communication Speed Memory protection Memory/cache use Scheduling g Parallelism… Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 26
  • 27. SW Synthesis  Communication synthesis 3 Layers automatically inserted in service calls  Layer 1: communication semantics   Layer 2 management f allocation-dependent communications L 2: t for ll ti d d t i ti   Allocation independent Thread generation, data splitting, synchronization Layer 3: Low-level communications y  Inter-thread, Inter-process, distributed communication Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 27
  • 28. SW Synthesis  Communication synthesis  Layer1: Independent  Channel properties  of architectural mapping RPC BlockingFunctionCall (T) BlockingFunctionReturn (T) T M Ta T Ta M Tb Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore Tb January 20, 2014 28
  • 29. SW Synthesis  Communication synthesis  Layer1: Independent  Channel properties  of architectural mapping Pipeline BlockingFunctionCall (F) BlockingFunctionReturn (T) T M Ta T Ta M Tb Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore Tb January 20, 2014 29
  • 30. SW Synthesis  Communication synthesis  Layer1: Independent  Channel properties  of architectural mapping Pipeline & Parallel BlockingFunctionCall (F) BlockingFunctionReturn (F) T M Ta T Ta Tb M Tb Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 30
  • 31. SW Synthesis  Communication synthesis  Layer1: Independent  Interface properties  T of architectural mapping Data splitting M Ta Ta Tb M1 M2 Tb Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 31
  • 32. SW Synthesis  Communication synthesis  Layer1: Independent  Interface properties  T of architectural mapping Data splitting M Ta Ta Tb M1 M2 Tb Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 32
  • 33. SW Synthesis  Implementation alternatives  Channel  semantics can be implemented in multiple ways Different OS services     shared memory message queue socket file... file  Performance is highly dependent on platform and OS  Synthesis enables fast exploration  optimal channel implementation for specific platform and code Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 33
  • 34. SW Synthesis  MultiCore Association APIs  Standard APIs for communication and synchronization  Closely distributed embedded systems    MCAPI - communication MRAPI - synchronization MTAPI - task generation  Independence from OS  OS-agnostic channel implementation   Components treated as MCAPI nodes Ports treated as MCAPI endpoints Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 34
  • 35. SW Synthesis  Platform Inputs & Outputs  Drivers associated to environmental components Camera Test-Bench code Camera 1 driver PLC Test-Bench code PLC driver Environment Model System Model P1 P2 Camera 2 driver Memory Space OS1 SMP Node PLC Communication Infrastructure Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 35
  • 36. Conclusions  UML/MARTE  Powerful modeling methodology  Single-Source approach  Platform-Independent Modeling Platform Independent  Maximizing reusability Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 36
  • 37. Conclusions  SW Synthesis  Functional modeling  Functional synthesis  Communication synthesis  Platform Inputs & Outputs  Actually enables platform-independent code  Reduces in depth knowledge of platforms in-depth  Support shorter design optimization cycles   wider design exploration shorter code generation on heterogeneous platforms Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 37
  • 38. Additional Information      http://www.teisa.unican.es/gim/en/proyecto?id=95 H. Posadas, P. Peñil, A. Nicolás, E. Villar "Automatic synthesis of embedded SW for evaluating p y y g physical implementation alternatives p from UML/MARTE models supporting memory space separation“ Microelectronics Journal, in press, doi: 10.1016/j.mejo.2013.11.003. H. Posadas, E. Villar, et al. "EU FP7-288307 PHARAON project: Parallel and heterogeneous architecture for real-time O f applications“ Euromicro Conference on Digital System Design, DSD 2013, IEEE, doi: 10.1109/DSD.2013.47. 10 1109/DSD 2013 47 H. Posadas, P. Peñil, A. Nicolás, E. Villar "System synthesis from UML/MARTE models: The PHARAON approach“, Electronic System Level Synthesis Conference, ESLsyn, 2013, IEEE. P. Peñil, H. Posadas, A. Nicolás, E. Villar "Automatic synthesis from UML/MARTE models using channel semantics“ International Workshop on Model-Based Arquitecting and Construction of Embedded S t E b dd d Systems, ACES MB 2012 d i 10 1145/2432631 2432640 ACES-MB 2012, doi: 10.1145/2432631.2432640. Tutorial SD1: High-Level Specifications to Cope With Design Complexity ASP-DAC 2014, Singapore January 20, 2014 38

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