In this presentation UML/MARTE is proposed as the language for a singe-source approach to the design of complex, heterogeneous, HW/SW embedded systems. The language improves reusability and from the model of the system all the design tasks such as architectural mapping, simulation, performance analysis, verification and SW synthesis can be supported.
Single-Source approach to the design of HW/SW Embedded Systems
1. Eugenio Villar
Pablo Peñil
University of Cantabria
Spain
Schedulablity
Analysis
Simulation
Verification
Performance
Analysis
Design-Space
Exploration
Architectural
Mapping
Optimization
Reusability
HW
Synthesis
SW
Synthesis
Aproximación de Código Único
para la mejora del Diseño de
Sistemas Embebidos HW/SW
2. Motivation
Modeling of HW/SW Embedded Systems
Simulation & Performance Analysis
SW Synthesis
Verification
Conclusions
Who are we?
Agenda
2Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
3. Microelectronics Engineering Group
Prof. Eugenio Villar
Ing. Pablo Peñil
University of Cantabria
4th Spanish University in Research Quality (BBVA-IVIE)
GIM
Who we are
3Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
4. Design Languages
Hardware (HDLs)
VHDL, Verilog,…
Embedded SW
ADA, C, C++, ASM (ARM, openrisc, etc…)
Specification and Design
SystemC, SystemC-AMS, AADL, UML, MARTE, …
Interchange format
IP/XACT
Hardware Design
RTL and Behavioral synthesis (Mentor, Synopsys, ISE, Quartus)
System-Level synthesis: Catapult-C, Gaut, …
HW/SW Co-Design, Embedded Systems and ESL design
Development Environments: Quartus, XPS, Eclipse, Papyrus
RTOS: ELinux, uC-Linux, eCos, uCO-II, xilkernel,
Embedded processors: ARM, Microblaze, Nios, Leon, Openrisc, …
Main Know-How
4Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
5. System-Level Specification
SystemC (HetSC)
UML/MARTE
AADL (AADS)
Verification of Embedded Systems
Assertion-based verification
Automatic Test Pattern Generation
Model-Checking
System-Level Performance Estimation
SCoPE→SCoPE+
VIPPE
Automatic Implementation
Automatic SW Generation from SystemC (SWGen) and UML/MARTE (eSSYN)
HW/SW interfaces
Main research Areas
5Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
6. Artemis SCALOPES
ESTEC HWSWCo
FP7 COMPLEX
FP7 Pharaon
Artemis CopCams
Artemis Crafters
FP7 Contrex
Artemis EMC2
Recent and on-going projects
6Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
7. Agenda
7Seminario de “Metodología de Diseño de SEs HW/SW de código único”
Who are we?
Motivation
Modeling of HW/SW Embedded Systems
Simulation & Performance Analysis
SW Synthesis
Verification
Conclusions
TASE, Tres Cantos, July 17, 2014
8. Motivation
Design productivity gap
Raising the abstraction level
Multi-Processing &
Heterogeneous platforms
Increasing SW content
SW-centric design methodologies
8Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
9. HW/SW platform
OS1
OS2
GPU DSP
Ad/Hoc SW development
System calls
Communication functions
I/O functions & drivers
Verification & Debug
Costly fixing of wrong design decisions
Architectural Design
Usual SW development flow
N2 BN1
M A
Architectural mapping
9Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
10. Lack of reusability
Ad-hoc code
Partial performance analysis
Large re-engineering effort
Usual SW development flow
N2 BN1
M A
OS3
OS1
OS2
GPU DSP
10Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
11. Agenda
11Seminario de “Metodología de Diseño de SEs HW/SW de código único”
Who are we?
Motivation
Modeling of HW/SW Embedded Systems
Simulation & Performance Analysis
SW Synthesis
Verification
Conclusions
TASE, Tres Cantos, July 17, 2014
12. Introduction
Model-Driven Architecture (MDA)
High-abstraction level
Mature SW engineering methodology
UML language
Application to embedded systems design
12Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
13. Introduction
Why UML?
Natural way to capture system architecture
Standard way
N2 BN1
M A
N.P N.O
13Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
14. Introduction
Why UML?
Natural way to capture system architecture
Standard way
UML language
Semantics lacks
What is each component?
What kind or interaction each link actually means?
Domain-specific profiles
UML/MARTE
14Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
15. Introduction
MARTE
Standard UML profile for real-time embedded systems
Platform-Independent Model (PIM)
Platform Description Model (PDM)
Platform-Specific Model (PSM)
Rich semantics content
Single-source approach
Schedulablity
Analysis
Simulation
Verification
Performance
Analysis
Design-Space
Exploration
Architectural
Mapping
Optimization
Reusability
HW
Synthesis
SW
Synthesis
15Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
16. State-of-the-Art
Discussion
System modeling in MARTE
Methods based on specific MoCs and/or profiles
Requiring additional semantics
Non-standard
SW Synthesis
Commercial code generation available
Limited support for heterogeneity
Limited flexibility for different architectural mappings
Limited support for the MARTE semantics
16Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
17. PHARAON Single-Source Design Flow
17Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
18. PHARAON Single-Source Design Flow
HW/SW
Platform
Architectural
Mappings
C/
C++
Scenarios
PIM
(App)
HW
Accelerators
HW
Accelerators
HW
AcceleratorsHW
Accelerators
SW stacks
Compilers
Linkers
SW Synthesis (eSSYN)
+
M2T Tools
CPUs/DSPs/ASIPs GP-GPUs
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19. PHARAON Modeling Methodology
Main features
MDD concepts
Separation of Concerns
CBE: Component-Based Engineering approach
SW centric
Standard
MARTE profile
19Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
20. TASE, Tres Cantos, July 17, 2014 20Seminario de “Metodología de Diseño de SEs HW/SW de código único”
PHARAON Modeling Methodology
Modeling Methodology
Separation of Concerns
21. Bit Arrays
Arrays
PHARAON Modeling Methodology
Data Types for Communication Interfaces
Primitive Types
Data Structures
21Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
22. PHARAON Modeling Methodology
Functional View
Classes implement Interfaces and require services
Internal Interfaces
External Interfaces
22Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
23. PHARAON Modeling Methodology
Communication & Concurrency View
System components and their non-functional properties
Two different kinds of components
Components with their own execution thread
Stereotyped with the MARTE::HLAM RtUnit
Passive components
Stereotyped with the MARTE::HLAM PpUnit
Representation
Composite diagrams
23Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
24. PHARAON Modeling Methodology
Component model
Hierarchical functional encapsulation
Ports
provided or required
C2
C2.3
C2.1 C2.2
24Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
25. PHARAON Modeling Methodology
Component Interfaces
C2
C2.3
C2.1 C2.2
25Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
26. PHARAON Modeling Methodology
Component model
Interfaces
sequential, guarded or concurrent, Max. threads available
argument sizes (data splitting), Num. of incoming channels
C2
C2.3
C2.1 C2.2
26Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
27. PHARAON Modeling Methodology
Component model
Channels manage communications
BlockingFunctionCall, BlockingFunctionReturn, both or none
Timeout
Priority
Buffer Size
ResMult
C2
C2.3
C2.1 C2.2
27Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
28. PHARAON Modeling Methodology
SW Platform
Declares High-level SW Components
RTOS, Drivers, HdS
Class Diagram
can be shared with HW platform diagram
Each SW Component
A UML Component + MARTE stereotype
RTOS: <<scheduler>>
Drivers: <<DeviceBroker>>
HdS: <<HwPLP>>
Stereotypes for very high-level modeling could be a
MARTE improvement
28Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
29. PHARAON Modeling Methodology
HW Platform
Declares HW Components
Processors, Memories, Buses, IO Peripherals
Processor: <<HwProcessor>>
Memory: <<HwMemory>>, <<HwRAM>>, <<HwROM>>
Bus: <<HwBus>>, etc…
29Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
30. PHARAON Modeling Methodology
The Platform Description Model
HW/SW Components using MARTE stereotypes
Software Components
OS, HdS, Drivers, …
Hardware Components
Processors, Memories, Buses, Custom HW, I/O
30Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
31. PHARAON Modeling Methodology
Platform-Specific Model
Mapping of functional components
to memory spaces and/or platform resources
Memory spaces mapped to platform resources
31Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
32. Architectural Design
PHARAON Modeling Methodology
HW/SW platform
Architectural mapping
Code reuse and/or
development
platform independent
32Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
33. Verification View
COMPLEX stereotype
<<VerificationView>>
Environment component
Separated from system components
Homogeneous style
composite diagram
Enables extraction of the
test bench SystemC
code (structural code)
PHARAON Modeling Methodology
verification
<<VerificationView>>
33Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
34. 34Seminario de “Metodología de Diseño de SEs HW/SW de código único” 2011-01-19
Interaction “Behavior”
between an environment component
and the System Component
A sequence Diagram
Includes synchronization and
communication semantics
Extraction of code for the behavior of
environment component
PHARAON Modeling Methodology
Verification View
TASE, Tres Cantos, July 17, 2014
35. 35Seminario de “Metodología de Diseño de SEs HW/SW de código único” 2011-01-19
A single sequence diagram can cover the
interaction of more than one environment
component
Synthetic description of a “scenario”
Interaction “Behavior”
Eventually, a single sequence diagram
PHARAON Modeling Methodology
Verification View
TASE, Tres Cantos, July 17, 2014
36. 36Seminario de “Metodología de Diseño de SEs HW/SW de código único”
Scenario1
<<Scenario>>
2011-01-19
Scenario: A tuple of interactions covering
the interaction of the system with the whole
environment
A package within the Verification View with
the <<Scenario>> stereotype
Several scenarios are possible
Synthetic: import of sequence diagrams
PHARAON Modeling Methodology
Verification View
Scenario2
<<Scenario>>
TASE, Tres Cantos, July 17, 2014
37. Agenda
37Seminario de “Metodología de Diseño de SEs HW/SW de código único”
Who are we?
Motivation
Modeling of HW/SW Embedded Systems
Simulation & Performance Analysis
SW Synthesis
Verification
Conclusions
TASE, Tres Cantos, July 17, 2014
38. 38Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
HW/SW Embedded Systems Design Flow
UML/MARTE
MDA
Functional
design
C
VHDL
Verilog
SystemC
HW/SW Implementation
RTL
Synthesis
Compilation
IP
Reuse
Behavioral
Synthesis
HW
Platform
Embedded
SW
Co- Design
Executable
Specification
Requirements
HW/SW Simulation
Performance Analysis
• avoiding slow design
iterations
Design Verification
• At the different abstraction
levels
Context
Context
39. Computing needs Time
Edward A. Lee
Communications of the ACM, 52(5):70-79, May 2009
Motivation
Motivation
Computing needs Energy
Eugenio Villar
Still to be published
39Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
40. Motivation
Why SW performance analysis
Software Simulation Technologies in Virtual Platforms
Simulation Technologies at different abstraction levels
SCoPE: SW performance analysis for DSE
• Native simulation
• After architectural mapping
SCoPE+: SW performance analysis for DSE
• Compositional Native simulation
• Before architectural mapping
• Direct PSM from the same PIM
VIPPE: Parallel simulation
Agenda
Agenda
40Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
41. The MPSoC
Multi-processing platform
• ASIC
• FPGA
• Commercial multi-processing platform
SW-centric design methodology
• Most of the functionality implemented as Embedded SW
• With ‘some’ application-specific HW
Motivation
Motivation
41Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
42. TASE, Tres Cantos, July 17, 2014
Embedded SW simulation
Functional Simulation
Native & Trace-based co-simulation
Accurate Computation&Communication
estimations
Virtual Models
ISS Discrete-Time Models
HDL Discrete-Event Models
Native & Trace-based code simulation
Fast Computation&Communication
estimations
SW Simulation Technologies
42
UML/MARTE
MDA
Functional
design
C
VHDL
Verilog
SystemC
HW/SW Implementation
RTL
Synthesis
Compilation
IP
Reuse
Behavioral
Synthesis
HW
Platform
Embedded
SW
Co- Design
Executable
Specification
Requirements
Seminario de “Metodología de Diseño de SEs HW/SW de código único”
43. VHDL
Verilog
HDL simulation
Very detailed Model
Very accurate
Very slow
Node i
Application Code
Task n...Task 1
NoC if.
NoC
Other Nodes
Bus
caches …
memory DMAASHW
CPU1
caches
CPUp
HdS API
HdSOS
OS API HdS API
HdSOS
OS API
HDL Model
Embedded System Architecture
Other Nodes
Node i
Bus model
NoC model
NoC if.DMA ASHW memory
Cache models …
CPU1 model
Cache models
CPUp model Compilation
SW Simulation Technologies
43Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
44. ISSs
ISS simulation
Very detailed Model
Very accurate
Very slow
Node i
HdS API
Application Code
Task n...Task 1
Bus
HdSOS
caches …
NoC
NoC if.memory DMAASHW Other Nodes
CPU1
OS API HdS API
HdSOS
caches
CPUp
OS API
ISS Model
Node i
Bus (TLM/RTL) model
NoC model
NoC if.DMA ASHW memory
Cache models …Cache models
CPU1
Instruction
Set
model
CPUp
Instruction
Set
model Compilation
SW Simulation Technologies
44
Embedded System Architecture
Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
45. Virtualization
Target virtual model on host
Node i
HdS API
Application Code
Task n...Task 1
Bus
HdS
caches …
NoC
NoC if.memory DMAASHW Other Nodes
CPU1
HdS API
HdSOS
caches
CPUp
OS API
Node i
TLM Bus model
NoC model
NoC if.DMA ASHW memory
OS
OS API
Compilation
Binary Binary
…
CPUp
virtual model
CPU1
virtual model
SW Simulation Technologies
45
Embedded System Architecture
Virtual Model
Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
46. Virtualization (QEMU)
Detailed model
• High modeling cost
• Late design steps
Faster than ISS
# movl_T0_r1
# ebx = env->regs[1]
mov 0x4(%ebp),%ebx
# addl_T0_im -16 # ebx = ebx -
16 add $0xfffffff0,%ebx #
movl_r1_T0
# env->regs[1] = ebx
mov %ebx,0x4(%ebp)
Intel Core i5 (2.40 GHz)
# r1 = r1 - 16
addi r1,r1,-16
PowerPC (200 MHz)
SW Simulation Technologies
46Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
47. Virtualization
Functional emulation
Rough timed simulation
• i.e. 1 cycle per instruction
Additional effort needed for more accurate modeling
• Execution times
• Power consumption
• Caches
• …
Requires a specific Virtual Model for each processor
Commercial tools
OVP, FastModels, Cadence, Carbon, Synopsys (CoWare), etc.
SW Simulation Technologies
47Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
48. Native & Trace-based simulation
Embedded code directly executed by the host
Good accuracy
• Native back-annotation
• Trace analysis
Fast execution time
SW Simulation Technologies
48Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
49. Native simulation based on HAL API
Abstraction of the HW platform
Node i
Bus
caches …
NoC
NoC if.memory DMAASHW Other Nodes
CPU1
caches
CPUp
Virtual Model
Node i
TLM Bus model
NoC model
NoC if.DMA ASHWOther Nodes memory
HdS API
Application Code
Task n...Task 1
HdSOS
OS API HdS API
HdSOS
OS API
Parsing
…Abstract
CPU1 model
Abstract
CPUp model
HAL HAL
Annotation
HdS API
Application Code
Task n...Task 1
HdSOS
OS API HdS API
HdSOS
OS API
SW Simulation Technologies
49
Embedded System Architecture
Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
50. Native simulation based on OS API
Abstraction of the SW platform
Node i
TLM Bus model
NoC model
NoC if.DMA ASHWOther Nodes
Node i
Bus
caches …
NoC
NoC if.memory DMAASHW Other Nodes
CPU1
caches
CPUp
memory
HdS API
Application Code
Task n...Task 1
OS API HdS API
HdSOS HdSOS
OS API
…
HdS APIOS API HdS API
Abstract
model of
OS & CPU
OS API
HdS
Abstract
model of
OS & CPU
HdS
Parsing
Annotation
Application Code
Task n...Task 1
SW Simulation Technologies
50
Embedded System ArchitectureVirtual Model
Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
51. Basic code annotation in native simulation
…
Overflow = 0;
s = 1L;
for (i = 0; i < L_subfr; i++) {
Carry = 0;
s = L_macNs(s, xn[i], y1[i]);
if (Overflow != 0) {
break; }}
if (Overflow == 0) {
exp_xy = norm_l(s);
if (exp_xy<=0)
xy = round(L_shr (s, -exp_xy));
else
xy = round(L_shl (s, exp_xy)); }
mq_send(queue1, &xy, p, t);
…
Global variable
int Sim_Time = 0;
Sim_Time += 20;
Sim_Time += 25;
Sim_Time += 15;
Sim_Time += 10;
Sim_Time += 10;
Sim_Time += 10;
wait
included
SW Simulation Technologies
51Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
52. ISSs
Trace-based simulation
Activity traces from detailed models
Node i
HdS API
Application Code
Task n...Task 1
Bus
HdSOS
caches …
NoC
NoC if.memory DMAASHW Other Nodes
CPU1
OS API HdS API
HdSOS
caches
CPUp
OS APINode i
Bus (TLM/RTL) model
NoC model
NoC if.DMA ASHW memory
Cache models …Cache models
CPU1
Instruction
Set
model
CPUp
Instruction
Set
model Compilation
SW Simulation Technologies
52
Embedded System Architecture
Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
53. ISSs
Trace-based simulation
Node i
Bus (TLM/RTL) model
NoC model
NoC if.DMA ASHW memory
Cache models …Cache models
CPU1
Instruction
Set
model
CPUp
Instruction
Set
model
SW Simulation Technologies
53
Traces
Simulation
Traces
Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
54. Trace-based simulation
Difficult scheduling in complex multi-processing systems
SW Simulation Technologies
54
Traces
Node i
TLM Bus model
NoC model
NoC if.DMA ASHWOther Nodes memory
Virtual Model
Scheduler
Application Code
Task n...Task 1
Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
55. Basic code execution in trace-based simulation
…
Overflow = 0;
s = 1L;
for (i = 0; i < L_subfr; i++) {
Carry = 0;
s = L_macNs(s, xn[i], y1[i]);
if (Overflow != 0) {
break; }}
if (Overflow == 0) {
exp_xy = norm_l(s);
if (exp_xy<=0)
xy = round(L_shr (s, -exp_xy));
else
xy = round(L_shl (s, exp_xy)); }
mq_send(queue1, &xy, p, t);
…
SW Simulation Technologies
55
Traces
T1
T2
T3
T4
T5
T6
Sim_Time += 20;
Sim_Time += 25;
Sim_Time += 15;
Sim_Time += 10;
Sim_Time += 10;
Sim_Time += 10;
Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
56. Functional simulation based on code
Fastest but least accurate
Work-load analysis
Node i
Bus
NoC
NoC if.memory DMAASHW Other Nodes
TLM Bus model
NoC model
NoC if.DMA ASHWOther Nodes memory
Application Code
caches …
CPU1
caches
CPUp
HdS APIOS API HdS API
HdSOS HdSOS
OS API
…
Abstract
model of
OS, HdS
& CPU
Modeling API
Abstract
model of
OS, HdS
& CPU
Modeling API
Node i
Task n...Task 1Task n...Task 1
SW Simulation Technologies
56
Embedded System Architecture
Virtual Model
Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
57. Performance/Error comparison
Rough approximate figures
Technology
Time
Estimation
Time & Power
Estimation
Performance 5,000 N.A.
Error N.A. N.A.
Performance 1,000 500
Error 1.3 1.4
Performance 200 T.B.M.
Error 1.5 T.B.M.
Performance 10 1
Error 1.1 (DT) 1.1
Performance 1 0.1
Error 1 (DE) 1
Functional
Native
Trace-based
Virtualization
ISS
(cycle-accurate)
HDL
SW Simulation Technologies
57Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
58. Key features
Abstract OS modeling
Instruction cache modeling
Data cache modeling
Level-X memory model
Bus model
System power estimation
SCoPE:
SW Performance Estimation for DSE
58Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
59. Novel features
Physical memory accesses
Separate memory spaces
Configurability for Design-Space Exploration
Dynamic Voltage-Frequency Scaling
Thermal modeling
System composition from IP-XACT components
Win32 API
SCoPE:
SW Performance Estimation for DSE
59Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
60. System power estimation
Application code
• Instruction counting from binary
SCoPE:
SW Performance Estimation for DSE
60
Bus
NoC
NoC if.memory DMAASHW Other Nodes
Application Code
caches …
CPU1
caches
CPUp
HdS APIOS API HdS API
HdSOS HdSOS
OS API
Node i
Task n...Task 1
OS & HW-dependent SW
• Function power estimation
Caches
• Counting memory accesses
• Cache misses
Bus
• Actual bandwidth
• Cache misses
• DMA accesses
• HW accesses
HW & NoC
• SystemC power models
Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
61. Node i
TLM Bus model
NoC model
NoC if.DMA ASHWOther Nodes memory
…
HdS API
Application Code
Task n...Task 1
OS API HdS API
Abstract
model of
OS &
CPU
OS API
HdS
Abstract
model of
OS &
CPU
HdS
Node i
TLM Bus model
NoC model
NoC if.DMA ASHWOther Nodes memory
…
HdS API
Application Code
Task n...Task 1
OS API HdS API
Abstract
model of
OS &
CPU
OS API
HdS
Abstract
model of
OS &
CPU
HdS
Node i
TLM Bus model
NoC model
NoC if.DMA ASHWOther Nodes memory
…
HdS API
Application Code
Task n...Task 1
OS API HdS API
Abstract
model of
OS & CPU
OS API
HdS
Abstract
model of
OS & CPU
HdS
Design-Space Exploration
Configurable model
Metrics
Design
parameters
Pareto points
Design-Space
Exploration
Tool
(M3Explorer)
SCoPE:
SW Performance Estimation for DSE
61Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
62. Dynamic Voltage-Frequency Scaling
Node i
TLM Bus model
NoC model
NoC if.DMA ASHWOther Nodes memory
Node i
Bus
caches …
NoC
NoC if.memory DMAASHW Other Nodes
CPU1
caches
CPUp
HdS API
Application Code
Task n...Task 1
OS API HdS API
HdSOS HdSOS
OS API
…
HdS APIOS API HdS API
Abstract
model of
OS & CPU
OS API
HdS
Abstract
model of
OS & CPU
HdS
Parsing
Application Code
Task n...Task 1
Annotation
T0(F0,V0)
E0(F0,V0)
F,VF,V
E/TP
V
V
.EE
F
F
.TT
2
0
2
0
0
0
=
=
=
SCoPE:
SW Performance Estimation for DSE
62Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
63. Key features
Abstract OS modeling
Instruction cache modeling
Data cache modeling
System power estimation
Novel features
Physical memory accesses
Separate memory spaces
Configurability for Design-Space Exploration
Dynamic Voltage-Frequency Scaling
Thermal modeling
System composition from IP-XACT components
Win32 API
SCoPE:
SW Performance Estimation for DSE
63Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
64. SCoPE+: Compositional
Native Performance Estimation
64
Implementation-Agnostic Platform Independent Frontend
CFAM-CM API
Fulfilling COMPLEX UML/MARTE executive semantics
System-Level Modeling of Multi-OS execution
SW/SW-HW/SW-HW/HW communications
Architectural mapping agnostic
Taking advantage of the native simulation speed*accuracy
Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
65. Macros and functions
Concurrent Functional Application & Component Model
Component Based PIM
CFAM API
Platform services required by functional code
Hide RTOS specific calls
SCoPE+: Compositional
Native Performance Estimation
65Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
66. Platform-Dependent Estimations directly on the PIM
PIM
PDM
ARM9
annotation
ARM9
annotation
ARM7
annotation
HW
annotation
SW/SW
SW/SW
HW/SW
SCoPE+: Compositional
Native Performance Estimation
66Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
67. VIPPE: Parallel Simulation
& Performance Analysis
67
...
...tbus 1
tbus b
tmem 1
tcore 1 tcore i
tcore n...
tmem mCluster 0
Target Multi-/Many-core HW platform
Target Real-Time Operating Systems (tRTOS)
Increasing number of cores
Non-Uniform Memory Access (NUMA)
Heterogeneous: different types of cores,
HW accelerators, …
• 4 x Cortex A15
• 4 x Cortex A7
• 1 x MALI GPU
Embedded Software
...
Embedded system
t-thread 1 t-thread t
Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
68. ...
...tbus 1
tbus b
tmem 1
tcore 1 tcore i
tcore n...
tmem mCluster 0
Target Multi-/Many-core HW platform
Target Real-Time Operating Systems (tRTOS)
Embedded Software
...
Embedded system
t-thread 1 t-thread t
VIPPE: Parallel Simulation
& Performance Analysis
68
Host Computer
Simulation / Virtual Platform
Software
h-thread 1 ... h-thread h
Host SMP Operating System (h-OS)
Multi-core HW Platform
(hcore 1,...,hcore h)
Source-code instrumentation/annotation
• Model embedded RTOS (tRTOS)
• Abstract hardware details
• Parallelization
oT-thread i h-thread i
Simulation of target cores
• Main techniques
o ISS (Instruction Set Simulation)
o Virtualization (i.e.QEMU)
o SystemC TLM models
• Parallelization
oTcore i h-thread i
Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
69. VIPPE: Performance results
69
Host platform: 64 cores with SMP capability at 3.10GHz, 64Gb of RAM and 20Mb of cache.
Benchmark: Video codec x264
PARSEC (Princeton Application Repository for Shared-Memory Computers )
Configurable number of threads
Native (PC code) execution is 64,7 times faster than VIPPE simulation
Both provide similar speed up
Speed-up with the number of target threads Speed-up with the number of host cores
Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
70. VIPPE: Performance results
70
Benchmark: Video codec x264
PARSEC (Princeton Application Repository for Shared-Memory Computers )
Configurable number of threads
Impact of number of target cores
in the simulation
Performance analysis result:
Impact of target bus bandwidth on
application execution time
Host platform: 64 cores with SMP capability at 3.10GHz, 64Gb of RAM and 20Mb of cache.
Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
71. Estimation of HW implementations
71
Application C/C++ code
…
ThreadI
Threadi+1
….
ThreadjCore i Hw module
Heterogeneous Target
Many-core platform
VIPPE Virtual Platform
…
ThreadI(SW)
Threadi+1(SW)
….
Threadj(HW)
….
Kernelprocess
Only 1 thread is allocated in a “hardware module”
Two new HW-oriented estimation techniques have been defined
Estimation of the minimum execution time: dynamic scheduling
Estimation of the maximum execution time: basic block execution time
Include HW register and memory management
Similar to SW caches
Estimate data transfer requirements (bus and memory access estimation)
Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
72. Extension to networked
embedded system simulation
72
Node i
HdS API
Application Code
Task n...Task 1
Bus
HdSOS
caches …
NoC
NoC if.memory DMAASHW Other Nodes
CPU1
OS API HdS API
HdSOS
caches
CPUp
OS API
Multi/Many core Embedded Systems
Wireless Sensor Network
(WSN)
Networked Embedded Systems
Application
RTOS (OS)
HW: CPU,…
RF trans.
Node i
Other Nodes
Wireless channel
Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
73. Extension to networked
embedded system simulation
73
Network Model
Application
HW Model
70
10
70
70
Wireless Sensor Network
(WSN)
Node-i ModelNetworked Embedded Systems
Application
HW Model
Node-j Model
VIPPE: WSN Virtual PlatformDeployment information
Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
74. Extension to networked
embedded system simulation
74
Network Model
Application
HW Model
70
10
70
70
Wireless Sensor Network
(WSN)
Node-i ModelNetworked Embedded Systems
Application
HW Model
Node-j Model
VIPPE: WSN Virtual Platform
•Execution time
•Power consumption
Battery lifetime
• Network traffic
Tx/Rx packets
Estimations
Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
75. Security evaluation
75
Network Model
Application
HW Model
70
10
70
70
Node-i ModelNetworked Embedded Systems
Application
HW Model
Node-j Model
VIPPE: WSN Virtual Platform
Jammer
Attack
Interrogation
Attack
• Attack effects:
• Power consumption
• Battery lifetime
• Network traffic
Estimations
Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
76. Security evaluation example
76
Attack
Node 1: HW crypto
+ attack-aware firmware
Node 2: SW crypto
+ insecure firmware
Not
Attacked
2.67 mWh
Replication
attack
HW crypto versus SW crypto: Software crypto increase 33% power
consumption compared to the Hardware crypto
Attack-aware WSN firmware: Insecure firmware increase 132% power
consumption compared to the Attack-aware firmware in case of attack
Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
77. Safety evaluation
77
Node i
HdS API
Application Code
Task n...Task 1
Bus
HdSOS
caches …
NoC
NoC if.memory DMAASHW Other Nodes
CPU1
OS API HdS API
HdSOS
caches
CPUp
OS API
Multi/Many core Embedded Systems
Fault effects:
• Functionality
• Execution time
• Power consumption
Estimations
Virtual Platform: VIPPE
Safety Certification
Fault Injection
* Hardware faults
- Memory faults
- Cache Faults
- Bus faults
Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
78. Agenda
78Seminario de “Metodología de Diseño de SEs HW/SW de código único”
Who are we?
Motivation
Modeling of HW/SW Embedded Systems
Simulation & Performance Analysis
SW Synthesis
Verification
Conclusions
TASE, Tres Cantos, July 17, 2014
79. Reusability
79Seminario de “Metodología de Diseño de SEs HW/SW de código único”
Texas Instruments OMAP Evolution Time
Freescale IMX Evolution Time
Stereovision
N2 BN1
M A
Application Evolution Time
N2’ B’N1’
M’ A’
TASE, Tres Cantos, July 17, 2014
80. PHARAON Single-Source Design Flow
HW/SW
Platform
Architectural
Mappings
C/
C++
Scenarios
PIM
(App)
HW
Accelerators
HW
Accelerators
HW
AcceleratorsHW
Accelerators
SW stacks
Compilers
Linkers
SW Synthesis (eSSYN)
+
M2T Tools
CPUs/DSPs/ASIPs GP-GPUs
80Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
81. SW Synthesis
System heterogeneity
Full support for
any architectural mapping decided for each component
any specific processing resource selected
any processing resource type
any memory space
any OS used by the processing resource
any communication infrastructure
81Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
82. SW Synthesis
Functional synthesis
One executable per memory-space
Platform-Independent (C/C++) code
Highest reusability
Non-recommended explicit calls to platform services
communication, concurrency, etc.
Platform services should derived from the UML/MARTE model
POSIX and/or OpenMP as alternatives
Static execution flows
<<SwSchedulableResource>>
82Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
83. SW Synthesis
Functional synthesis
Platform-Specific code
Optimized C code for DSPs
OpenCL/GL for GPUs
C/C++ & OpenMP for SMPs… C3
DSP
optimized
C code
OpenCL/GL
code for
GPU
Platform-
Independent
C code
Communication Infrastructure
Memory Space
OS
GPU
SMP
node
DSP
83
Configuration Original Optimized Code
ARM 908.28 sec 572.92 sec
ARM-NEON 325.81 sec 255.28 sec
ARM+DSP
blocking call
206.01 sec 193.45 sec
ARM+DSP
non-blocking call
895.98 sec 431.68 sec
ARM-NEON+DSP
non-blocking call
247.93 sec 215.96 sec
Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
84. Communication synthesis
Architectural mapping
Same memory space
Same OS
Different processing nodes
Benefits / Drawbacks
Communication Speed
Memory protection
Memory/cache use
Scheduling
Parallelism…
SW Synthesis
84Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
85. Communication synthesis
3 Layers automatically inserted in service calls
Layer 1: communication semantics
Allocation independent
Layer 2: management for allocation-dependent communications
Thread generation, data splitting, synchronization
Layer 3: Low-level communications
Inter-thread, Inter-process, distributed communication
SW Synthesis
85Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
86. Communication synthesis
Layer1: Independent of architectural mapping
Channel properties
RPC
SW Synthesis
T M Ta
M
Tb
BlockingFunctionCall (T)
BlockingFunctionReturn (T)
Ta
Tb
86Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
87. Communication synthesis
Layer1: Independent of architectural mapping
Channel properties
Pipeline
SW Synthesis
Ta
M
Tb
T M
BlockingFunctionCall (F)
BlockingFunctionReturn (T)
Ta
Tb
87Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
88. Communication synthesis
Layer1: Independent of architectural mapping
Channel properties
Pipeline & Parallel
SW Synthesis
Ta
MTb
T M
BlockingFunctionCall (F)
BlockingFunctionReturn (F)
Ta
Tb
88Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
89. Communication synthesis
Layer1: Independent of architectural mapping
Interface properties
Data splitting
SW Synthesis
Ta
M1Tb
M2
T M
Ta
Tb
89Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
90. Communication synthesis
Layer1: Independent of architectural mapping
Interface properties
Data splitting
SW Synthesis
Ta
Tb
T M
Ta
Tb
M1 M2
90Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
91. Implementation alternatives
Channel semantics can be implemented in multiple ways
Different OS services
shared memory
message queue
Socket
file...
Different middleware APIs
Performance is highly dependent on platform and OS
Synthesis enables fast exploration
optimal channel implementation for specific platform and code
SW Synthesis
91Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
92. MultiCore Association APIs
Standard APIs for communication and synchronization
Closely distributed embedded systems
MCAPI - communication
MRAPI - synchronization
MTAPI - task generation
Independence from OS
OS-agnostic channel implementation
Components treated as MCAPI nodes
Ports treated as MCAPI endpoints
SW Synthesis
92Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
93. 93
Platform Inputs & Outputs
Drivers associated to environmental components
SW Synthesis
Communication Infrastructure
OS1
PLCSMP
Node
Environment Model
P1
System Model
P2
Memory Space
PLC
Test-Bench
code
Camera
Test-Bench
code
PLC
driver
Camera 1
driver
Camera 2
driver
Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
94. Agenda
94Seminario de “Metodología de Diseño de SEs HW/SW de código único”
Who are we?
Motivation
Modeling of HW/SW Embedded Systems
Simulation & Performance Analysis
SW Synthesis
Verification
Conclusions
TASE, Tres Cantos, July 17, 2014
95. Verification: Main research lines
Test Framework definition
Test Methodology for embedded systems
Extension of commonly used software test framework
Google Test
Test models are integrated in the MARTE model
Automatic test generation
Model checking
Improve test set
Coverage and SIL (safety) improvement, Security validation
Checking non-functional parameters with VIPPE
WCET determination
95Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
96. Test Framework
This tree will be modelled in UML MARTE
Test Program
Test case (“TC1”)
Test
Assertions
Test 1 (T1) Test
Test case i
Assertions Assertions Assertions
Test Project
TEST(TC1,T1) {
EXPECT_EQ(1, Function_under_test(1));
}
A test project integrates all the
embedded system test
A test program verifies a unit
(function/class/component) or a system
(integration test). It could have different
test cases.
Each test case can be composed of
many different tests.
Each test can be composed of different
conditions to be checked (assertions).
96Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
97. Testing view in UML MARTE
Test case 1
Assertion 1
Test 1
Assertion 2
97Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
98. Test types:
Functional test
Based on Google TestRandom Test
Insert random values in test unit inputs.
Boundary Test
Use as inputs the maximum and minimum inputs values
Automatically generated test (directed test)
Use an UC ATPG (“Forest”) to generate tests that comply an specific requirement (for
example, cover a condition for code coverage improvement).
Assertion types
Tests could verify functional parameters (e.g. function results) or
non-functional parameters (e.g. execution time limit or power consumption)
Test results
Failed tests
Code coverage
98Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
Verification methodology
99. Verification methodology
SYSTEM REQUIREMENTS
UML/MARTE
PIM PDM
PSM
XML GENERATOR
xml platform
file
xml mapping
& concurrency
files
User source
code functions
(c/c++)
Application
code (c/c++)
CONCURRENCY SW
GENERATOR
TESTING
FRAMEWORK (i.e. Google test)
CODE TEST
GENERATOR
xml test
configuration
SIMULATION
FRAMEWORK (i.e. VIPPE)
Test
Model
99Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
100. Automatic Test Generation
FOREST
FramewORk for Embedded System VerificaTion
FOREST
SMT (Satisfiability Modulo Theory) checker to verify
properties
FOREST
C/C++
code
Property
Test that
verify the
property
100Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
101. Code coverage improvement
Generate additional test to cover code that has not
been covered by functional/random/boundary tests
Safety certification
Generate tests that improve SIL (Safety Integrity Level)
i.e. improving MC/DC coverage (Modified Condition/Decision
coverage)
Checking non-functional parameters
Identify the input sequence that requires the maximum
execution time (WCET)
101Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
FOREST applications
102. FOREST applications
Security validation
Verification of concurrent program
i.e. identify an input sequence that produces deadlock
FOREST generates a test
that overflows “password_buffer”
array and accesses the system.
The test (*argv=111111111110)
does not verify the password
condition.
102Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
103. Agenda
103Seminario de “Metodología de Diseño de SEs HW/SW de código único”
Who are we?
Motivation
Modeling of HW/SW Embedded Systems
Simulation & Performance Analysis
SW Synthesis
Verification
Conclusions
TASE, Tres Cantos, July 17, 2014
104. UML/MARTE
Powerful modeling methodology
Single-Source approach
Reusability
MDD concepts
Separation of Concerns
CBE: Component-Based Engineering approach
SW centric
DSE-oriented
M2T generation of simulation & verification models
SW synthesis
Conclusions
104Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
105. SW simulation and performance analysis
Essential Design Technology
HW/SW Embedded Systems
At different design steps
Different modeling and simulation technologies
Various performance*accuracy products
Native simulation
Optimum performance*accuracy for system-level DSE
Conclusions
105Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
106. SW Synthesis
Functional modeling
Functional synthesis
Communication synthesis
Platform Inputs & Outputs
Reusability support
www.essyn.com
Conclusions
106Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014
107. Verification
extension of Goggle-test for ES verification
Integration of the test framework inside UML/MARTE
Automatic test-pattern generation based on SMT
Forest
Conclusions
107Seminario de “Metodología de Diseño de SEs HW/SW de código único” TASE, Tres Cantos, July 17, 2014