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Nowak NVSMW-ICMTD'08

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Presentation done at IEEE NVSMW-ICMTD conference in June 2008

Presentation done at IEEE NVSMW-ICMTD conference in June 2008

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  • 1. On the Influence of Fin Corner Rounding in 3D Nanocrystal Flash Memories E. Nowak , L. Perniola, G. Ghibaudo*, C. Jahan, P. Scheiblin, G. Reimbold, B. De Salvo, F. Boulanger CEA/LETI-Minatec, 38054 Grenoble, France * IMEP/INPG Grenoble, France [email_address]
  • 2. Outline
    • Introduction
    • Model motivations
    • Corner region vs. planar region
    • Comparison with 3D TCAD simulations
    • Comparison with experimental data
    • Conclusion
  • 3. Nanocrystal FinFlash
    • Tri-gate FinFET advantages
      • Increased drive current and improved access time in NAND
      • Reduced Short Channel Effects
      • Ultra-small cell area (NAND)
      • Compatibility with multigate CMOS for complex SoC
      • SOI cells can be integrated in 3D vertical architectures
    • Nanocrystal memory advantages
      • Strong immunity to oxide defects
      • Improved scalability
      • Lower operating voltages
    BOX source Control Gate Fin
  • 4. Modeling Fowler-Nordheim operation
    • Issue
      • Corners in 3D structure appears critical
      • Not available simple models for Fowler-Nordheim operation in complex 3D structures taking corner curvature radius into account
    • Our approach
      • Physics-based modeling of FN write/erase for trigate FinFLASH with Si-NCs
    BOX source Control Gate Fin V G
  • 5. Outline
    • Introduction
    • Model motivations
    • Corner region vs. planar region
    • Comparison with 3D TCAD simulations
    • Comparison with experimental data
    • Conclusion
  • 6. 3D TCAD Simulations +
    • 3D tunneling simulation  charge trapping depends on local fin curvature radius
    • 3D transport simulations  fin current density locally dependent on planar/corner regions
    + ATLAS user guide, www.silvaco.com
  • 7. Model presentation (1/2)
    • 1D potential & capacitance calculation for planar and corner regions
      • top/side  planar geometry
      • corner  cylindrical geometry
    planar geometry corner geometry
  • 8. Model presentation (2/2)
    • Tunneling module: WKB approximation on the real barrier shape
    • Transport module: total programming window
    • with
  • 9. Present model vs. IEDM’07 model *
    • Previous model* based on Green function approach for NC FinFLASH tailored for SOI vs. Body-Tied
    • Present model does not need any Green function solution  lighter computationally
    • Present model implements tunneling through high-k stacks
    * L. Perniola et al., Tech. Dig of IEDM, pp.943-946, 2007.
  • 10. Outline
    • Introduction
    • Model motivations
    • Corner region vs. planar region
    • Comparison with 3D TCAD simulations
    • Comparison with experimental data
    • Conclusion
  • 11.
    • Flash need a coupling ratio [ITRS]
    • Better control on the floating gate voltage thanks to corner
    Coupling ratio: planar vs corner regions 1 10 20 30 40 50 0 0.2 0.4 0.6 0.8 1 Curvature radius (nm) Coupling ratio  g planar geometry cylindrical geometry Si/SiO2(5nm)/dots Si/SiO2(13nm)/PolySiN+
  • 12. Programming window: planar vs. corner regions
    • Corner regions show:
    • Bigger programming windows
    • Faster dynamics during program and erase operations
     Vt cylin  Vt plan Rc=5.8nm planar No charge stored 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 0 1 2 3 0 5 10 15 20 -14 -12 -10 -8 -6 -4 -2 0 2 4 (b) (a) Programming windows  Vt [V] Pulse Time t [s] Si HfO2 SiO2 dots Si SiO2 Si Conduction Band Energy [eV] x [nm]
  • 13. Outline
    • Introduction
    • Model motivations
    • Corner region vs. planar region
    • Comparison with 3D TCAD simulations
    • Comparison with experimental data
    • Conclusion
  • 14. Model vs. 3D TCAD simulation
    • Reproduce accurately both
      • The trapped charge of each dot
      • Programming window
    Dot A Dot C Dot B Dot D Dot A Dot C Programming windows Δ Vt[V] 10 -7 10 -6 10 -5 10 -4 0 1 2 3 4 Model Simulation Rc=15nm Rc=25nm Pulse Time t [s] 10 -7 10 -6 10 -5 10 -4 -5,0x10 -2 0 Model Simulation Rc=15nm Rc=25nm planar Trapped Charge density Q [C.m -2 ] Pulse Time t [s]
  • 15. Outline
    • Introduction
    • Model motivations
    • Corner region vs. planar region
    • Comparison with 3D TCAD simulations
    • Comparison with experimental data
    • Conclusion
  • 16. Program/Erase Dynamics of LETI devices
    • Good fit obtained on devices with high-k in top dielectrics
    10 -6 10 -4 10 -2 0,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 1,6 1,8 10 -6 10 -4 10 -2 Programming windows  Vt [V] Data Model Vg=8V Vg=10V Vg=12V Vg=14V 0,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 1,6 1,8 Data Model Vg=-5V Vg=-7V Vg=-9V Vg=-11V Pulse Time t [s] Pulse Time t [s]
  • 17. Fin Width & Height impact on Δ VT
    • Δ VT increases when the width and height decrease due to enhanced corner impacts
    [2] K. Yanagidaira et al., Jpn. J. Appl. Phys., pp.2608-2611, 2005. H=6 nm 0,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 0,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 Programming windows  Vt [V] H=60 nm 0 20 40 60 80 0 20 40 60 80 Fin Width W [nm] Fin Width W [nm] ref. [2] model planar component cylindrical component
  • 18. Curvature radius impact on Δ VT
    • Δ VT balance from the quantity of injected charge and the area coverage over the fin
    • Hemispherical devices behave better than trigate devices
    Hemispherical R= W/2 6 8 10 12 14 16 18 Curvature radius R [nm] Trigate R  0 10 μ s 100 μ s 10ns  1 s 100ns H=18nm W=36nm Vg=14V 0,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 1,6 1,8 2,0 2,2 Programming windows  Vt [V]
  • 19. Outline
    • Introduction
    • Model motivations
    • Corner region vs. planar region
    • Comparison with 3D TCAD simulations
    • Comparison with experimental data
    • Conclusion
  • 20. Conclusion
    • On the model
      • Quantitatively fitting dynamics under FN operation for 3D nanocrystal flash memories employing high-k dielectrics
      • Approach suitable for compact modeling
      • Perspectives:
        • Easily extended to various 3D memory device architectures (3G, Ω G , GAA)
        • Can be extended to SONOS FinFet devices
    • On corner rounding
      • Appears to be a critical design parameter
      • Hemispherical devices show a higher Δ VT than trigate devices
  • 21. Device Fabrication
    • SOI wafers, Tsi=30 nm
    • Fins patterning with Ebeam lithography and resist trimming
    • Sidewall sacrificial oxidation
    • Boron implantation for VTH adjustment
    • Gate stack deposition process:
    • Gate patterning: Ebeam lithography, resist trimming and combined dry and wet etching
    • Extension implants + 950°C RTA anneal
    • 50 nm nitride spacers + 20 nm S/D Si SEG
    • S/D implants + 1050°C Spike anneal
    • Ni Silicidation + classical Back-end process
    Buried oxide Si fin Gate C. Jahan et al., NVSMW-ICMTD ‘08 Poly-Si N + SiO2 Si-ncs HTO Si Poly
  • 22. The evaluation of access resistance allows to calculate the potential drop along the series of on-pass SOI cells in the NAND string, during write/erase steps V* G-stress V D-inhibit V D-inhibit V G-HIGH V G-HIGH Solution : Write/erase operation for SOI arrays at a cell-by-cell or wordline level Purpose : Source/drain of selected cell must be pinned at ground for efficient write/erase Write/Erase of SOI cells in NAND arrays Problem : Efficient W/E operations for NAND arrays of SOI FD FinFlash.
  • 23.
    • The access resistance for the single cell is around 1 – 100 k Ω range
    • In NAND string, the potential drop through the on-pass gates is estimated to be of the order of µV
    • FN write/erase performance of single cell can be extrapolated to the selected cell included in the NAND string
    Access resistance
  • 24. Scaling limits of Fin Flash devices Thanks to C. Gerardi – STMicroelectronics Y pitch not a concern: L G =30 nm functional devices X pitch is a concern: Enough space to accommodate fin/gate stack/control gate X pitch x = fin + 2d + m = 10nm + 30nm + 5nm = 45 nm F = x/2 = 20-22 nm From ITRS 2007 : 2014 in production
  • 25. Vt dependence with Radius of curvature
    • Simulation shows:
      • Change of Vt with R is of the order of 100mV for GAA device
      • A better electrostatic control is obtained for higher curvature radius
    C.W. Lee et al., Solid State Electronics 51 (2007) pp. 505-510