Nowak IEDM'08

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Presentation done at IEEE IEDM in December 2008

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  • Thanks Mr. Chairman for the presentation. My name is Etienne Nowak and I will present you a work done at CEA-Leti Minatec, France. This work is entitled New Physical Model for ultra-scaled 3D Nitride Trapping Non Volatile Memories.
  • Nowak IEDM'08

    1. 1. New Physical Model for ultra-scaled 3D Nitride-Trapping Non-Volatile Memories E. Nowak , M. Bocquet, L. Perniola, G. Ghibaudo*, G. Molas, C. Jahan, R. Kies, G. Reimbold, B. De Salvo, F. Boulanger CEA-LETI, MINATEC
    2. 2. Outline <ul><li>Context and issues </li></ul><ul><li>Tri-Gate memory cells </li></ul><ul><li>Model for FN write/erase </li></ul><ul><li>Data vs. model </li></ul><ul><li>Scaling </li></ul><ul><li>Conclusion </li></ul>E.Nowak et al. IEDM 2008
    3. 3. Outline <ul><li>Context and issues </li></ul><ul><li>Tri-Gate memory cells </li></ul><ul><li>Model for FN write/erase </li></ul><ul><li>Data vs. model </li></ul><ul><li>Scaling </li></ul><ul><li>Conclusion </li></ul>E.Nowak et al. IEDM 2008
    4. 4. Nitride Tri-Gate devices <ul><li>Tri-Gate advantages: </li></ul><ul><ul><li>Increased Drive Current </li></ul></ul><ul><ul><li>Reduced Short Channel effects </li></ul></ul><ul><li>Nitride-trapping advantages: </li></ul><ul><ul><li>Lower operating voltages </li></ul></ul><ul><ul><li>Strong immunity to oxide defects </li></ul></ul><ul><ul><li>Improved scalability </li></ul></ul><ul><li>Improved Program/ Erase characteristics </li></ul>E.Nowak et al. IEDM 2008
    5. 5. Literature <ul><li>Few recent models on the subject </li></ul><ul><ul><li>Si nanocrystal Tri-Gate [Perniola L., IEDM 07] </li></ul></ul><ul><ul><li>BE-SONOS Tri-Gate [Hsu T.-H.,IEDM 07] </li></ul></ul><ul><ul><li>Si nanocrystal Tri-Gate [Nowak E., NVSMW 08] </li></ul></ul>E.Nowak et al. IEDM 2008
    6. 6. Issue <ul><li>Corners in 3D structure appear critical </li></ul><ul><li>Our approach </li></ul><ul><li>Physics-based modeling of FN write/erase for Nitride-trapping Tri-Gate </li></ul>E.Nowak et al. IEDM 2008
    7. 7. Outline <ul><li>Context and issues </li></ul><ul><li>Tri-Gate memory cells </li></ul><ul><li>Model for FN write/erase </li></ul><ul><li>Data vs. model </li></ul><ul><li>Scaling </li></ul><ul><li>Conclusion </li></ul>E.Nowak et al. IEDM 2008
    8. 8. Fabricated Devices <ul><li>SOI Charge-Trapping Tri-Gate non volatile memory </li></ul><ul><ul><li>W FIN ~ 15 nm </li></ul></ul><ul><ul><li>H FIN ~ 20 nm </li></ul></ul><ul><li>SONOS / THiONOS stack </li></ul>E.Nowak et al. IEDM 2008 SONOS THiONOS
    9. 9. Outline <ul><li>Context and issues </li></ul><ul><li>Tri-Gate memory cells </li></ul><ul><li>Model for FN write/erase </li></ul><ul><ul><li>1D modeling </li></ul></ul><ul><ul><li>Transmission factor </li></ul></ul><ul><ul><li>Trapping modeling </li></ul></ul><ul><li>Data vs. model </li></ul><ul><li>Scaling </li></ul><ul><li>Conclusion </li></ul>E.Nowak et al. IEDM 2008
    10. 10. 1D Model <ul><li>1D potential & capacitance calculation for planar and corner regions </li></ul><ul><li>Total programming window is weighted sum of each regions </li></ul>E.Nowak et al. IEDM 2008 planar geometry cylindrical geometry [Nowak E., NVSMW 08] V G V D V S R C
    11. 11. Cylindrical Tunneling transmission factor <ul><li>WKB approximation correct down to 3 nm radius </li></ul>E.Nowak et al. IEDM 2008 R C R C
    12. 12. Cylindrical Tunneling enhancement <ul><li>Transparency enhancement for small curvature radius </li></ul><ul><li>Mandatory to use the exact shape of the barrier </li></ul>E.Nowak et al. IEDM 2008 R C R C
    13. 13. Trapping model <ul><li>Current fluxes: </li></ul><ul><ul><li>Tunneling Currents </li></ul></ul><ul><ul><li>Electrons and holes included </li></ul></ul><ul><ul><li>Capture/Emission with SRH and Poole-Frenkel electric field activation term </li></ul></ul><ul><li>Charge is solution of the differential system </li></ul>E.Nowak et al. IEDM 2008 Q n Q p Traps Electron currents Hole currents Channel Trapping layer Control Gate SiO 2 Si 3 N 4 SiO 2 HfO 2 Si TiN Δ E TRAP Channel Trapping layer Control Gate SiO 2 Si 3 N 4 SiO 2 HfO 2 Si TiN Δ E TRAP Q n Q p
    14. 14. Outline <ul><li>Context and issues </li></ul><ul><li>Tri-Gate memory cells </li></ul><ul><li>Model for FN write/erase </li></ul><ul><li>Data vs. model </li></ul><ul><ul><li>SONOS vs. THiONOS </li></ul></ul><ul><ul><li>Width dependence </li></ul></ul><ul><ul><li>Temperature dependence </li></ul></ul><ul><li>Scaling </li></ul><ul><li>Conclusion </li></ul>E.Nowak et al. IEDM 2008
    15. 15. Experimental Results <ul><li>Better programming performances for THiONOS </li></ul><ul><li>Due to better coupling ratio thanks to HfO2 </li></ul>E.Nowak et al. IEDM 2008
    16. 16. Width dependence <ul><li>Δ V T increases when reducing fin width </li></ul><ul><li>Model predicts an higher impact of trapped charges at corners for smaller devices </li></ul>E.Nowak et al. IEDM 2008 V G =8V V G =12V V G =10V SONOS W FIN
    17. 17. Temperature impact on Write (1/2) <ul><li>Similar write dynamics for different temperatures </li></ul><ul><li>Lower saturation Δ V T level at high temperature </li></ul>E.Nowak et al. IEDM 2008 V G =8V V G =12V V G =10V SONOS
    18. 18. Temperature impact on Write (2/2) <ul><li>J in-n identical at both temperatures </li></ul><ul><li>Δ V T saturation at high temperature due to enhanced electron emission in nitride </li></ul>E.Nowak et al. IEDM 2008 T=25°C J in-n T=150°C J e-n J out-n SiO 2 Si 3 N 4 SiO 2 Si
    19. 19. Temperature impact on Erase (1/2) <ul><li>Faster erase dynamics at high temperature </li></ul>E.Nowak et al. IEDM 2008 SONOS V G = -12V V G = -8V
    20. 20. Temperature impact on Erase (2/2) <ul><li>Electron and hole currents must be considered during erase at high temperature </li></ul>E.Nowak et al. IEDM 2008 T=25°C SiO 2 Si 3 N 4 SiO 2 Si T=150°C J out-n J e-n J c-n J in-n
    21. 21. Outline <ul><li>Context and issues </li></ul><ul><li>Tri-Gate memory cells </li></ul><ul><li>Model for FN write/erase </li></ul><ul><li>Data vs. model </li></ul><ul><li>Scaling perspectives </li></ul><ul><li>Conclusion </li></ul>E.Nowak et al. IEDM 2008
    22. 22. Scaling perspectives: HC-FET <ul><li>Reducing cell size  smaller Δ V T at saturation </li></ul><ul><li> faster dynamics </li></ul>E.Nowak et al. IEDM 2008 <ul><ul><li>[D. Kwak et al, VLSI 07] </li></ul></ul>// // // // //
    23. 23. Outline <ul><li>Context and issues </li></ul><ul><li>Tri-Gate memory cells </li></ul><ul><li>Model for FN write/erase </li></ul><ul><li>Data vs. model </li></ul><ul><li>Scaling </li></ul><ul><li>Conclusion </li></ul>E.Nowak et al. IEDM 2008
    24. 24. Conclusion <ul><li>Physical model reproduces FN program/erase data of 3D nitride memory devices </li></ul><ul><ul><li>Corners modelled in cylindrical geometry </li></ul></ul><ul><ul><li>Electron and hole currents considered </li></ul></ul><ul><li>Highlights: </li></ul><ul><ul><li>Write dynamics does not depend on temperature </li></ul></ul><ul><ul><li>Erase performance is strongly dependent on temperature </li></ul></ul><ul><li>Scaling down HC-FET induces: </li></ul><ul><ul><li>Lower Δ V T at saturation </li></ul></ul><ul><ul><li>Strongly enhanced write dynamics </li></ul></ul>E.Nowak et al. IEDM 2008

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