Focal Plane Engineering Challenges
Upcoming SlideShare
Loading in...5
×
 

Focal Plane Engineering Challenges

on

  • 3,511 views

 

Statistics

Views

Total Views
3,511
Slideshare-icon Views on SlideShare
3,505
Embed Views
6

Actions

Likes
1
Downloads
12
Comments
0

3 Embeds 6

http://www.linkedin.com 4
http://www.slideshare.net 1
http://www.health.medicbd.com 1

Accessibility

Categories

Upload Details

Uploaded via as Microsoft Word

Usage Rights

© All Rights Reserved

Report content

Flagged as inappropriate Flag as inappropriate
Flag as inappropriate

Select your reason for flagging this presentation as inappropriate.

Cancel
  • Full Name Full Name Comment goes here.
    Are you sure you want to
    Your message goes here
    Processing…
Post Comment
Edit your comment

    Focal Plane Engineering Challenges Focal Plane Engineering Challenges Presentation Transcript

    • FOCAL PLANE ENGINEERING CHALLENGES
    • Eric F. Schulte Focal Plane Engineering Consultant Indium Bump Bonding Hybrid Focal Plane Layout Mission Statement: FPA packaging Capitalize on 30+ years of R&D experience to save my and Stress Control Contact clients time and money by providing rapid, cost-effective, Metallization knowledgeable solutions to engineering challenges in: Compound - Design Semiconductor Plasma Etching - Materials Detector - Process Processing Resume and - Yield, throughput, and cost Specific Process - Reliability Experience Patents, of infrared, visible, and UV focal plane detectors, hybrid Publications, and assemblies, MEMS, and 3-D stacked structures. Awards Contact Eric: See last page
    • Indium Bump Bonding Is THE Lead-Free, High-density Interconnect Solution. High-yield in-house indium bump bonding capability requires integrated proficiency in the following process areas: - Under-bump metallization deposition – CTE matched, diffusion barrier, ohmic contact, metallurigically compatible. - Bump photolithography process – Thick photoresist for efficient clean liftoff, dimensional uniformity. - Indium deposition – Parameters optimized for minimum grain growth, confined directionality, lateral uniformity; in-situ pre-deposition surface clean. - Indium liftoff capability – special techniques to minimize damage to bumps, contain indium, eliminate cross- contamination. - Pre-hybridization oxidation removal – to ensure bump-to-bump adhesion, minimize force and slip. - Hybridization process – Appropriate selection of bonding equipment and options, vacuum tooling design, bonding parameters (thermo-compression vs. reflow, temperature profiles, compression profiles, scrubbing, slip prevention) - Post-hybrid measurement – gap, parallelism, alignment, mechanical integrity, electrical integrity. Correct choices for all of the above capabilities are essential to first-pass success Contact Eric: See last page
    • Hybrid Focal Plane Layout Design considerations for successful FPA layout: - Minimum die length and width for handling and stability during bonding. - Die flatness requirements. - Detector & ROIC die thickness tradeoffs. - ROIC bulk wafer resistivity and backside surface finish for IR transparency (for post-bond metrics) - ROIC and detector backside surface finish requirements for vacuum hold on bonder tooling. - Detector size vs. RIOC size - Saw lane dimensions, border widths, saw lane fiducials. - Circumferential guard devices and ground plane. - Single-sided or double-sided indium bump configuration. - Indium bump dimensions, shape, spacing, and bump count for optimal yield, minimum bond force, maximum mechanical integrity. - Under-bump metallization choices for optimal adhesion, conductivity, CTE matching, and diffusion resistance. - Hybridization fiducial design and location for optimal precision of alignment, parallelism, post-hybrid metrics. Correct choices for all of the above parameters are essential to first-pass success Contact Eric: See last page
    • FPA packaging and Stress Control Focal plane die flatness is essential for high performance, high yield, and reliability. - Not only must the materials stack be balanced in theory, but one must also take into account the process sequence and thermal excursions during processing to achieve a flat final product. Additionally, if the stack contains fragile layers (i.e. compound semiconductors) one must consider transient stresses during processing to avoid residual damage to those delicate components. - Thin film stress is the #1 contributor to FPA failure during production, testing, and in the field. o Incorrect choices of metallization, insulators, and substrate material can lead to bowing/warpage of the focal plane with subsequent failures in hybrid interconnect, semiconductor device responsivity, or loss of focus. - Adhesive failures are the #2 contributor to FPA failure. These failures are usually due to incorrect choice of adhesive and/or incorrect adhesive curing and/or inadequate surface preparation. o Some bondlines call for very rigid adhesives to withstand high stress, others require flexible adhesives to avoid thermal mismatch bowing. The trick is in knowing which to use in a particular situation. o Adhesive cure cycles are critical to proper performance of the bondline. The manufacturer’s recommended cure cycle is not necessarily the best choice in unique situations/unusual materials combinations. o Removal of organics, adsorbed water, and silicones is essential to reliable bondlines. Numerous wet and dry processes are available to give an ideal surface, depending on the materials involved and the process history. Correct choices for all of the above parameters are essential to first-pass success Contact Eric: See last page
    • Contact Metallization “Simple” metal contacts are ANYTHING BUT simple! Considerations include: - Selection of the proper metal(s) to achieve the optimum balance of: o Ohmic contact. o Thermal expansion match to substrate. o Series resistance. o Barrier to diffusion. o Metallurgical compatibility with underlying and overlying materials (reliability). - Selection of proper deposition technique (evaporation, sputtering, reactive sputtering) to control: o Static (as-deposited) stress. o Dynamic stress due to thermal expansion issues. o Step coverage (or not). o Damage to underlying semiconductor material due to deposition energetics. - Pre-deposition surface preparation to achieve: o Good adhesion. o Barrier-free ohmic contact. - Selection of patterning technique o Liftoff vs. etchback patterning. o Photoresist selection: positive vs. negative tone, viscosity. o Photoresist spin and bake parameters. o Photoresist sidewall profile for optimal liftoff. o Critical dimension monitoring and control. Correct choices for all of the above parameters are essential to first-pass success Contact Eric: See last page
    • Compound Semiconductor Plasma Etching Eric Schulte was the first to develop reactive ion etching (RIE) of HgCdTe for infrared detectors, and the first to successfully fabricate spec. HgCdTe focal plane arrays using the technique. He received the prestigious IRIS (InfraRed Industry Symposium ) “Best Paper Award” in 1993 for his pioneering work in the field. Key to the success of this development was finding the correct etch chemistry and plasma parameters which could produce a high etch rate with controllable sidewall angle, good surface morphology, and minimal damage to the remaining HgCdTe material. This process is now routinely used in the HgCdTe IR detector industry where high aspect ratio etching is required. Contact Eric: See last page
    • Device Processing Through the years, Eric has led development projects in virtually every aspect of HgCdTe, InSb, and Si device processing including: - Starting wafer specification, measurement, and cleanup. - Photolithography: resists, spin, spray, bake, exposure, development, profile control, liftoff, strip. - Metal deposition: Thermal evap, e-beam evap, sputtering, reactive sputtering; adhesion, stress, conductivity. - Insulator deposition: Thermal evap, e-beam evap, sputtering, reactive sputtering, CVD; adhesion, stress, dielectric strength. - Dry etching: Semiconductors, metals, insulators, plasma surface prep., resist compatibility, damage control and mitigation. - Wet etching and surface preparation: Static, agitated, manual spray, automated spray, spin, surfactants, rinsing. - Implant and diffusion: species, profiles, characterization, stability, effect on performance. - Annealing: open-tube and closed-tube, vacuum, vapor, inter-diffusion. - Yield improvement: Test data analysis, physical analysis, correlation of performance defects to physical defects to processing parameters, techniques, contamination, particulates, handling, etc. - Cost and thruput improvement: Creative application of equipment and processing techniques to simplify and integrate processes, reduce touch labor, reduce queue dwell, improve process flow. - Reliability: failure analysis, performance degradation tracking, thermal cycling, vibration testing, bond strength measurement, accelerated shelf life testing, stress analysis and mitigation. Contact Eric: See last page
    • RESUME OF ERIC F. SCHULTE FOCAL PLANE ENGINEERING CONSULTANT Permanent residence: Santa Barbara, Ca. Contact Eric: See last page EDUCATION BSEE, Michigan Technological University, 1970 MSEngSci, University of Texas at Dallas, 1982 2004-Present (as a part-time consultant) - U.S. Army Night Vision Laboratories – Project to develop small-pitch indium bump deposition and hybridization techniques for high-density focal plane arrays. (Ongoing) - Lockheed-Martin Santa Barbara FocalPlane – Advanced process development in hybridization, array fabrication, backend processing, and packaging. (Ongoing) - Teledyne Imaging Systems – 2-color HgCdTe detector processing, yield, and performance, with concentration on contact metallization, stress control, passivation, dry etch, and hybridization. (Ongoing) - Judson Technologies – Technical assistance in all aspects of large IR focal plane production: detector processing, hybridization, packaging (Ongoing) - NASA GSFC Microshutter Project – Indium bump bonding capability setup, thin film stress management, MEMS process development, array handling and packaging design. (Completed in 2006) 1985-2004 (retired) - Raytheon Vision Systems, Goleta, Ca. Senior Principal Engineer, 2nd Gen Array Production Dept., responsible for conception, development, and implementation of novel processing techniques and equipment for the manufacture of infrared detectors. Numerous key developments in device design, semiconductor processing, equipment design, hybridization, process monitoring and control, failure analysis, and product reliability have resulted in 9 US patents, as well as company and industry awards.
    • 1982-85 - Texas Instruments, Central Research Labs, Dallas Tx. Member Technical Staff, IR Focal Plane Project. Developed advanced processing techniques for the fabrication of IR focal plane arrays. Also responsible for the design, mask generation, process development, fab. supervision, and internal delivery of a family of novel vertically integrated IR focal plane devices. 3 U.S. patents in this period. 1979-82 - Texas Instruments, Central Research Labs, Dallas Tx. Member Technical Staff, Solar Energy Project. Conceived and implemented laser processing steps in fabrication of photovoltaic solar arrays, including laser-induced diffusion, laser redistribution of dopants, laser patterning of metallization, and laser metallurgy of fuel cell electrode surfaces for electro-chemical activation. 2 U.S. patents in this period. 1977-79 - Texas Instruments, Consumer Products Group, Dallas Tx. Special Project Engineer. Successfully designed and produced a magneto-resistive sensor component for use in a consumer product application. Also interfaced with 3-M Corp. on proprietary magnetic materials. 1 U.S. patent in this period. 1976-77 - Texas Instruments, Government Equipment Group, Dallas, Tx. Maintainability Engineer. Successfully performed all maintainability engineering support for man-portable infrared imaging systems. Efforts included design support, maintenance procedure definition, and support equipment definition. 1972-75 - U.S. Navy - Missile Radar Officer, USS Oklahoma City, Western Pacific. Direct supervisor and administrator for 45 radar technicians and computer technicians. Responsible for maintenance and operation of shipboard tracking and guidance radars, and associated computer system. Vietnam Veteran. 1970-72 - U.S. Naval Air Engineering Center, Philadelphia, Pa. Ground Support Equipment Engineer. Evaluated contractor-proposed ground support equipment for Navy and Marine Corps aircraft. Interfaced directly with contractors and military end-users to evaluate electronic function, ease of operation, validity of operation manuals, and cost of support equipment. TECHNICAL PAPERS: Authored or co-authored eleven technical papers, including a pioneering paper in plasma etching of II-VI compounds which received quot;Best Paperquot; award for the 1993 Infra-Red Industry Symposium. PATENTS: Holder of fifteen US patents, three international patents, mainly in the fields of semiconductor processing and novel semiconductor devices. Received 1993 Hughes Aircraft Aerospace Sector patent award for a novel multi-band IR detector which has created a new multi-million $ market for infrared detectors. AFFILIATIONS: Institute of Electrical and Electronic Engineers Materials Research Society American Vacuum Society Surface Mount Technology Association PERSONAL: Age 60, excellent health.
    • Very happily married One son (age 28) Hobbies: automobiles, world travel, digital photography, skiing, golf, guitar, philosophy, language. Have traveled extensively in Europe and the Far East; speak “survival” German, French, Spanish, and Japanese. SPECIFIC TECHNICAL EXPERIENCE BASE IN THIN-FILM PROCESSING (33 year period) INDIUM BUMP HYBRIDIZATION: - Indium bump photolithography - Indium evaporation and liftoff - Pre-hybridization indium surface preparation - Flip-chip hybridization (with specialization in Suss/SET flip-chip bonders) - FPA mounting and packaging SPUTTER DEPOSITION: - R.F. & D.C. sputter deposition of metals & insulators. - Magnetron-enhanced sputtering. - Reactive sputtering to form metal oxides and nitrides. - Indirect sputtering by ion beam impact and transfer. - Stress control, thermal expansion coefficient control. - Diffusion barrier metallization. VACUUM EVAPORATION: - Automatic controller implementation. - Thermal evaporation by boat, basket, wire sources. - E-beam evaporation of metals and insulators. ION BEAM MILLING: - Accelerated argon ion etching. - Chlorine/Argon reactive ion beam etching of SiO2 - Photoresist compatibility. PLASMA DEPOSITION: - Parallel plate deposition of SiO2, Si3N4, SiOxNy. - quot;Downstreamquot; magnetron-excited plasma dep. of SiO2, Si3N4. PHOTOLITHOGRAPHY: - Positive and negative resists. - Contact and projection aligners.
    • - Multi-layer techniques. - Plasma resist deposition and development. - Excimer laser projection exposure. PLASMA ETCHING: - ECR/RIE of II-VI materials. - ECR/RIE of Si, SiO2, Si3N4, and metals with CF4/O2 and SF6. - Deep RIE of Silicon using the Bosch process. CLUSTER TOOLING: - Specified and purchased two multi-chamber cluster tools for in-situ etch and deposition of semiconductor thin films. OTHER SKILLS: - Excellent mechanical aptitude. - Strong capabilities in processing equipment selection and set-up. - Computer-versatile. - Innovative problem-solver. - Functionally versed in solid state physics, chemistry, and materials science. - User familiarity with SEM, STEM, Auger, XPS, SIMS, ESCA. Contact Eric: See last page
    • Patents Issued U.S. Patents: 5,880,510 Graded layer passivation of group II-VI infrared photodetectors 5,646,426 Contact metal diffusion barrier for semiconductor devices 5,401,986 Bake-stable HgCdTe photodetector with II-VI passivation layer 5,296,384 Bake-stable HgCdTe photodetector and method for fabricating same 5,113,076 Two terminal multi-band infrared radiation detector 4,970,567 Method and apparatus for detecting infrared radiation 4,956,304 Buried junction infrared photodetector process 4,865,245 Oxide removal from metallic contact bumps formed on semiconductor devices to improve hybridization cold-welds 4,783,594 Reticular detector array 4,729,003 Configuration of a metal insulator semiconductor with a processor based gate 4,616,403 Configuration of a metal insulator semiconductor with a processor based gate 4,447,291 Method for via formation in HgCdTe 4,413,020 Device fabrication incorporating liquid assisted laser patterning of metallization 4,388,517 Sublimation patterning process 4,369,498 Photoluminescent powered calculator Also, three international patents and several new U.S. patents pending. Contact Eric: See last page
    • Contact Eric Please note: Due to my affiliation with the U.S. Infrared Focal Plane Industry, I am prohibited by United States ITAR (International Traffic in Arms Regulations) from consulting for non-U.S. governments and institutions on technology directly related to past and current Focal Plane design and manufacturing processes. This limitation does NOT apply to MEMS, hybrid assembly, 3-D integration projects, future Focal Plane Technology, or other technology areas. Phone: 805-637-5723, 805-965-5022 FAX: 805-965-5022 Email: EricFSchulte@yahoo.com Location: Santa Barbara, CA, USA