Service Density By Xelerated At Linley Seminar

Service Density for Carrier Ethernet Beyond 2010  Carrier Ethernet Design, Linley Tech Seminar  San Jose January 28, 2010  Thomas Eklund  Founder  VP Business Development  Slide 1  4 mars 2010  Copyright Xelerated 2010. All rights reserved. 

Agenda    Service Density    What It Is    Can we measure it?    Xelerated Service Density EvoluNon    The HX 100 Gbps Network Processor  Slide 2  4 mars 2010  Copyright Xelerated 2010. All rights reserved. 

Leader in Carrier Ethernet Network Processing    Global Semiconductor Company    Stockholm, Beijing, Santa Clara and Tel Aviv    Programmable Chips for Growing  Carrier Ethernet Market    Network Processors &   Programmable Ethernet Switches    Data plane soWware    Technology Leadership    Patented Dataﬂow Architecture     Wirespeed by Design    Customer AYracNon    8 out 10 of top Carrier Ethernet   system vendors  Outstanding Financial   Performance 2009  Slide 3  4 mars 2010  Copyright Xelerated 2010. All rights reserved. 

More Services – Greater Demands  Video Transport  ProtecNon Switching  MPLS‐TP  Y.1731  VPLS  Synchronous Ethernet  Mirroring  Link and Service OAM  PPPoE,   DHCP Proxy Relay  PTPv1 & v2  PBB, PBT  Session Processing  L3 VPN   DPI  L2VPN  L2VPN  IPv6  IPv6  MPLS   MPLS   VLAN  VLAN  VLAN  ACL  ACL  ACL  ACL  MAC Learning  MAC Learning  MAC Learning  MAC Learning  IPv4  IPv4  IPv4  IPv4  Ethernet Forwarding   Ethernet Forwarding   Ethernet Forwarding   Ethernet Forwarding   1996           1998           2000           2002           2004           2006           2008           2010           2012  Slide 4  4 mars 2010  Copyright Xelerated 2010. All rights reserved. 

Service Density DefiniNon   “The amount of network services  simultaneously supported by the packet  processing device at wirespeed operaNon.”  But it is hard to measure:    Every service requires unique set of processing and  classificaNon/memory lookup resources    Device architecture and instrucNon set differs    Subject to implementaNon variaNons and opNmizaNon skills  Slide 5  4 mars 2010  Copyright Xelerated 2010. All rights reserved. 

The Two Components of Service Density    Service Processing   # Processor Cores   x Clock frequency   x Opera4ons per clock cycle 1   x Synchroniza4on and VLIW factor 2  x Instruc4on efficiency 3  1.  VLIW instrucNons enables   4 or 5 operaNons per    Service ClassificaNon,   2.  instrucNon  Raw capacity is less       # Lookups per second 4  interesNng than realisNc  scenarios     x Raw Memory Bandwidth  3.  Network opNmized  instrucNons, e.g. bit field     x Lookup opera4on factor  operaNons, addressing,   x Instruc4on efficiency  switching    4.  Depend on memory BW,  type and operaNon type  Slide 6  4 mars 2010  Copyright Xelerated 2010. All rights reserved. 

Service Density and Service Efficiency  Power dissipaNon  (Energy Efficiency)    Keeps cost down (OPEX)    Higher density systems    Increasingly important  Service Processing Efficiency = ”MOPS per WaY @Wirespeed”  Slide 7  4 mars 2010  Copyright Xelerated 2010. All rights reserved. 

Xelerated Service Density EvoluNon  Million Lookups per second   8,000  HX  6,000  100 Gbps NPU  4,000  X11  X11  X11  New GeneraNon    d240t  d200d240  InstrucNon  factor  48 Gbps NPU  2,000  X10q  X10q  X10q  ‐e  ‐m  ‐w  40 Gbps NPU  25 000   50,000   100,000   150,000  Processing   (RealisNc MOPS)  Slide 8  4 mars 2010  Copyright Xelerated 2010. All rights reserved. 

The Industry Benchmark for Service Processing Density   Service Eﬃciency (RealisNc MOPS/W)  5,000  HX330  4,000  3,000  Please do the maths  X11  (This is at least twice as good  2,000  as for any compeNtor)   1,000  25 000   50,000   100,000   200,000   Service Density (RealisNc MOPS)  Slide 9  4 mars 2010  Copyright Xelerated 2010. All rights reserved. 

The Industry Benchmark for Service ClassiﬁcaNon Density   Million Lookups/s  8,000  High number of lookups enable  greater service density and  HX320  increased ﬂexibility  HX330  6,000  Please do the maths…   4,000  2,000  200   400   600  800   External Memory BW (Gbps)  Slide 10  4 mars 2010  Copyright Xelerated 2010. All rights reserved. 

HX Under the Hood  Slide 11  4 mars 2010  Copyright Xelerated 2010. All rights reserved. 

Carrier Ethernet 2.0   Metro, Unified Access and Mobile Backhaul   ”a pefect fit for dataflow architecture”  Unified Fiber Access  Metro   Core   Data Center  Enterprise   Enterprise  Backbone Gigabit  Data Center   VirtualizaNon  Deep Packet Processing  Switch  Access  Virtualisation in Datacenter Cloud CompuNng  Router  Virtualized Servers  Unified Fiber Access  vNIC GPON, EPON, 10 G PON and AE  MDU  FTTH VEPA Point‐to‐Point  Applicances Metro Ethernet  Triple Play, VoD, IPTV  Business and ResidenNal Services  Dataflow = Carrier Ethernet  FTTB  Ethernet  Switch/Router  ONU/ONT  GPON  OLT  Fiber Access EPON  GPON, EPON, 10 G PON and AE Dataflow Card Integration MSPP  Edge Router  Line = Carrier Ethernet Core   Triple Play, VoD, IPTV FTTN  Router  VDSL  Business and Residential Services Mobile Backhaul  Mobile Backhaul   MAC Processor PHY Packet Service Router  Eth TM Switch 3/4G  PTP & Synchronous Ethernet   X10q PTN, MEF22  WiMAX  X11 Video Router  AX/HX LTE, WiMAX, Microwave  Metro Ethernet  Packet   Copper‐DSL  Transport  AggregaNon Switch  Cable  Slide 12  4 mars 2010  Copyright Xelerated 2010. All rights reserved. 

Under the Hood: The HX Family of Network Processor   – 100 Gbps with Integrated Traffic Manager  The HX Family   of Metro Ethernet NPUs  HX330 & HX230  HX320 & HX326  Integrated Traffic Manager  Deep‐buffer  Product  Processing Performance  Interfaces  Processors  Traffic Manager  100 Gbps  56xGE, 12x10GE  HX330  Yes  512  150 Mpps  10/20/50G Interlaken  100 Gbps  56xGE, 12x10GE  HX320  ‐  512  150 Mpps  10/20/50G Interlaken  100 Gbps  56xGE, 12x10GE   HX326  Yes  512  150 Mpps  100G Interlaken  50 Gbps  28xGE, 6x10GE   HX230  ‐  256  75 Mpps  10/20G Interlaken  Slide 13  4 mars 2010  Copyright Xelerated 2010. All rights reserved. 

The HX NPU Block Diagram  ’Line‐Card‐On‐a‐Chip’  TCAM  DDR2+, QDR2+  DDR3  DDR3  NSE i/f  SRAM i/f  DRAM i/f  DRAM i/f  Line Interfaces  MACs  Programmable Look‐aside Engines  100/1000 Base‐X  10/100/  /GE/2.5GE  2500 Base‐X  Hash  SRAM  TCAM  Status  Drop  SGMII, QSGMII  Engine  Engine  Engine  Engine  Engine  1.25‐6.25 Gbaud SerDes  XAUI  XG MACs  Interlaken  10G/20G  Programmable Pipeline  EAP  EAP  Interlaken  10/25/50G  System Interfaces  Packet  Generator  XAUI  Interlaken  XAUI+  100G   SPAUI  Shared Memory Switch  Interlaken  Flow Ctrl  PCIe  CPU i/f  Traﬃc Manager  CPU  DDR  CPU i/f  Slide 14  4 mars 2010  Copyright Xelerated 2010. All rights reserved. 

Key New Features    Hiearchical Traﬃc Manager    Shared Memory Switch    Stacking/Meshing    Precision Time SoluNons    Increased Service Density  Slide 15  4 mars 2010  Copyright Xelerated 2010. All rights reserved. 

Wirespeed HX330 TM Features    Single Scheduler    Queues freely allocated between ports and ingress/egress    5 levels Scheduling Hierarchy    Propagated priority scheduling and deficit shaping    Hierarchical scheduling nodes flexibly configured     RR, DWRR and SPQ scheduling at all levels     Dual Rate Shaping     Packet Buffer     Guaranteed BW using 4 or 2 LA Interfaces DDR3    33M packets    Dynamic bandwidth sharing between read/write     WRED and drop precedence watermarks     Buffer ReservaNon   Slide 16  4 mars 2010  Copyright Xelerated 2010. All rights reserved. 

TM Service Mapping Example  1 x ’Private’ Subscriber with 4 – 8 Services SPQ /WFQ Shaping Scheduling Voice HP1 Shaping Backpressure IPTV HP2 VOD MP2 Best Effort TCP To  LP1 Ports  ”Surfing” Service  Subscribers  User Classes  E.g.  Ports  Queues  Queues  Provider  Per Service SPQ CIR/EIR /WFQ shaping Scheduling Per User CIR/EIR Voice HP1 shaping IPTV HP2 VOD MP2 Best Effort TCP LP1 ”Surfing” Flows   VLANs   Service levels  Hierarchy Interfaces   Flows   Services   CoS  Users   Interfaces   ApplicaNons   Users   User Groups   Tunnels   Interfaces   Slide 17  4 mars 2010  Copyright Xelerated 2010. All rights reserved. 

Integrated Traffic Manager  No Trade‐off Between Performance and Cost  800 700 600 Xelerated’s TM is equally   cost‐effecNve for small and   500 large packet sizes.  Cost (USD) 400 AlternaNve Designs tend to be   non‐wirespeed, sNll at a higher   300 cost level   DRAM+SRAM TM  200 Xelerated DRAM TM  100 0 8 192 4 096 2 048 1 024 512 256 128 64 Packet size (bytes) Slide 18  4 mars 2010  Copyright Xelerated 2010. All rights reserved. 

Pointer Storage in DRAM   Wirespeed Performance for Internet Services  500 450 400 350 Packet buﬀer  required to  300 support Internet  Packet buffer (ms) round trip  250 delays  200 150 2 million pointers  100 50 Xelerated  0 8192 4096 2048 1024 512 256 128 64 Packet size (bytes) Slide 19  4 mars 2010  Copyright Xelerated 2010. All rights reserved. 

Integrated Shared Memory Switch  High‐bandwidth Switching     Single Main Packet Buffer    Shared Memory Switch (SMS)  EAP    Fine‐grained programmable  TI  resource reservaNon for e.g.  asymmetric configuraNons   Programmable Pipeline  PP  Input    3‐level hierarchical shaping/scheduling    TM  Arbiter    MulNple watermarks for   Traffic  Schedulers  Schedulers  Schedulers  drop presedence  Inter‐  Faces    400 Mpps read/write performance    Supports over‐speed transit traffic in  stacked configuraNons  Main Packet Buffer  TI  (Shared Memory)  PP  EAP    Logical and SpaNal MulNcast  TM  Traffic Manager  Slide 20  4 mars 2010  Copyright Xelerated 2010. All rights reserved. 

The HX and Service Density …  “The Proof Is in the Pudding”  Slide 21  4 mars 2010  Copyright Xelerated 2010. All rights reserved. 

Single Chip Service Density Example:  Xelerated’s Metro Ethernet ApplicaNon    Shipping since 2003  Simultaneously supported features @ wirespeed    Robust C API  FuncTons  MEA Key Features    Data structures in ANSI C for  L2 forwarding   L2 switching, IEEE 802.1Q  consistency between control  PB IEEE 802.1ad  and data planes  Provider Bridging  PBB, IEEE 802.1ah  PBB‐TE, IEEE 802.1ay    Test Suites  L3 forwarding  IPv4/IPv6  PWE3  MPLS    DiagnosNc SW  MPLS LER/LSR  Tunneling  IP‐IP, GRE, MPLS, VPLS    Aricent CP integrated  L2/L3 mulNcast  MulTcast  IGMP snooping  RestoraTon  RSPT, MSTP (IEEE 802.1w/IEEE 802.1s)  Filtering  ACL  Sole data plane MAC learning, distributed MAC learning  OAM  CFM 802.1ag   DiagnosNcs  Metering  Single and dual rate metering (MEF & IETF)  Counter and StaTsTcs  MIB2, RMON, SMON  Precision Time SoluTon  PTP v1, v2, Synchronous Ethernet  Slide 22  4 mars 2010  Copyright Xelerated 2010. All rights reserved. 

100 Gbps Is Just A Good Start  Service Density is What Makes The Diﬀerence     Meet the ever‐increasing demand for processing    Improved ROI for Service Providers    Longer LifeNme    Support real producTon NPU applicaNons    Not limited to lab test    Future headroom    Increased ﬂexability (easier to add new funcNonality in a producNon  code base)  Avoid Being Caught by Service Density LimitaNons   12 months Into the Engineering Project  Slide 23  4 mars 2010  Copyright Xelerated 2010. All rights reserved. 

Thomas Eklund  thomas.eklund@xelerated.com  Slide 24  4 mars 2010  Copyright Xelerated 2010. All rights reserved. 

Service Density By Xelerated At Linley Seminar

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Service Density By Xelerated At Linley Seminar — Presentation Transcript