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All the verilog which will cover all the interview question.

All the verilog which will cover all the interview question.
cover complete knowledge of verilog.
cover vlsi question.
vlsi Interview question.

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verilog code verilog code Document Transcript

  • Verilog Test Code
  • Check the following code with input is unknown and what is the mathematical precedence `timescale 1ns/1ps module abc; reg [3:0]a=4'b101X; reg [3:0]b=4'b1010; reg [3:0]c,d; integer e; initial begin c=a+b; d=a^b; e=3+3-6/3*2; end initial $monitor(c[0],c[1],c[2],c[3]," " ,d[0],d[1],d[2],d[3]," ",e); endmodule Check the triggering of the always with changing value of sensitivity list `timescale 1ns/1ps
  • module always_test(); reg x,y a; initial begin $monitor("%d %d %d",x,y,a,$time); x=1'bx; #10 x=1'b0; #10 x=1'b1; #10 x=1'b0; #10 x=1'b1; #10 x=1'b0; #10 x=1'b1; #10 x=1'b0; #20 x=1'b1; #10 x =1'b0; #10 x=1'b1; #10 x=1'b0; #10 $finish;end always @(x) y = #20 x; always @(x) #20 a = x; Initial begin $recordfile("always_block.trn"); $recordvars("depth= 0"); end endmodule `timescale 1ns/1ps module always_test(); reg x,y; integer a=0; initial begin $monitor("%d %d %d",x,y,a,$time); x=1'bx; #10 x=1'b0; y=1'b0; #10 x=1'b1;
  • #10 y=1'b1; #10 $finish; end always @(x&&y) a <= a + 10; initial begin $recordfile("always_testee.trn"); $recordvars("depth = 0"); End endmodule `timescale 1ns/1ps module always_test(); reg x,y; reg a; initial begin $monitor("%d %d %d",x,y,a,$time); x=1'bx; #10 x=1'b0; #10 x=1'b1; #10 x=1'b0; #10 x=1'b1; #30 x=1'b0; #10 x=1'b1; #10 x=1'b0; #20 x=1'b1; #10 x =1'b0; #10 x=1'b1; #10 x=1'b0; #10 $finish; end always @(x)
  • y <= #20 x; always @(x) #20 a <= x; Initial begin $recordfile("always_testee.trn"); $recordvars("depth = 0"); end endmodule Check the followingcode with different inertial delay `timescale 1ns/1ns module assign_delay_test; reg clk; initial begin clk =1'b0; forever #10 clk = ~clk; end assign #5 clk1 = clk; assign #6 clk2 = clk; initial $monitor(clk, " ", clk1 ," " ,clk2 ,$time); initial #50$finish; endmodule
  • Check the following code with different intra assignment delay `timescale 1ns/1ns module assign_delay_test; reg clk; initial begin clk =1'b0; forever #10 clk = ~clk; end assign clk1 = #4clk; assign clk2 = #6 clk; initial $monitor(clk,clk1,clk2 ,$time); initial #200 $finish; endmodule Check the output with mixed case assignment `timescale 1ns/1ns module block_nonblock_test; reg a,b,c,d; initial begin $monitor("a=%b b=%b c=%b d=%b ",a,b,c,d,); c=1'b0; a=1'b0; b=1'b1; c<=a|b;
  • d<=c; end endmodule muticase with single assignment `timescale 1ns/1ns module case_test; localparam MON=0,TUE=1,WED=2,THU=3,FRI=4,SAT=5,SUN=6; reg [0:2] today; integer pocket_money; always @* begin case (today) TUE: pocket_money=6; MON,WED : pocket_money=2; FRI,SAT,SUN: pocket_money=0; default : pocket_money=1; endcase end initial begin $recordfile("case_test.trn"); $recordvars("depth = 0"); end initial begin $display("today pocket_money time");
  • $monitor(today,pocket_money,$time); today=3'b000; #10 today=3'b001; #10 today=3'b010; #10 today=3'b011; #10 today=3'b001; #10 today=3'b111; #10 today=3'b101; #10 today=3'b110; end endmodule Check the triggering of the always with changing value of sensitivity list `timescale 1ns/1ns module clk_test(); reg clk,OP1; reg OP2; initial begin $display("clk, OP1 OP2"); $monitor("%d %d %d",clk,OP1,OP2,$time); #100 $finish; end initial clk=1'b0; always
  • #10 clk= ~clk; always@(clk) OP1= #20 clk; always @(clk) #20 OP2 = clk; Initial begin $recordfile("clk_test.trn"); $recordvars("depth = 0"); end endmodule fork Join Delay check all statement inside fork join run parallel and begin end sequentialy `timescale 1ns/1ns module delay_test(); reg x,m; parameter [2:0]delay=-1; initial fork begin x=1'b0; #5 x=1'b1; #1 x= 1'b1; End #5 x=1'b0;
  • #2 x=1'b1; #1 x=1'b0; //delayspecefied in terms of x and z does not take ERROR #delay$finish; // the delayis specefied in terms of negativeis not taking join initial fork m=1'b1; m= #1 1'b1; m = #1 1'bx; m= #2 1'b0; join initial begin $recordfile("delay_test.trn"); $recordvars("depth = 0"); end endmodule Check the code for Logical operator in regular statement `timescale 1ns/1ps module logical_test; reg [3:0]A,B,C,D,E,F; //reg [3:0] C,D,E,F;
  • always @* begin C=A&B; D=A&&B; E=A|B; F=A||B; end initial //$monitor("%b",D,"%b ",A); $monitor("A = %b B = %b C = %b D = %b E = %b F = %b ",A,B,C,D,E,F); initial begin A=4'b101Z; B=4'b11Z1; end endmodule Frequency multiplier `timescale 1ns/1ns module freq_div_2; reg clk,a; initial begin clk=1'b0; forever #10 clk =~clk; end always @(clk) begin
  • a=0; #5 a=1; end initial $monitor("clk= ", clk," a=",a,$time); initial #30$finish; endmodule Task calling function module func_task_test; integer x,y,z,re; initial fork y=8; task_test(y,z); join function integer fun(input integer y); begin fun =y; end endfunction task task_test(input integer y,output integer z); begin z=fun(y);end endtask initial $monitor("x= %2d Y = %2d Z = %2d", x,y,z); initial begin $recordfile("fun_task.trn");
  • $recordvars("depth=0"); #20 $finish;end endmodule `timescale 1ns/1ns module funct_test; integer val; initial begin val=funct(16); $display("%0d",val); end function integer funct(input integer depth); integer i; begin funct=1; for(i=0;2**i < depth;i=i+1) funct=i+1; end endfunction endmodule module fun_task_test; integer x,y,z,re; initial fork y=8; task_test(y,z); join function integer fun(input integer y); begin
  • fun =y; end endfunction task task_test(input integer y,output integer z); begin z=fun(y); end endtask initial $monitor(x,y,z); initial begin $recordfile("fun_task.trn"); $recordvars("depth=0"); #20 $finish;end endmodule module fun_test; integer val; initial begin val=funct(16); $display("%0d",val); end function integer funct(input integer depth); integer i; begin funct=1; for(i=0;2**i < depth;i=i+1) if(i==2) break;
  • funct=i+1; end endfunction endmodule `timescale 1ns/1ns module if_test; reg rst,En,x; test the if else condition always @* begin if(rst) if(En) x=1'b1; else x=1'b0; else x=1'bx; end initial begin $monitor("rst En = %b %b x = %b time ",rst,En,x,$time); #0 rst=1'b0;En=1'b1;
  • #10 rst=1'b0;En=1'b1; #10 rst=1'b1;En=1'b0; #10 rst=1'b1;En=1'b1; #10 rst=1'b0;En=1'b1; #10 $finish; end endmodule check the operator module operator_test; integer y; initial begin $monitor("y = %2d ",y,$time); #400 y= 3 + 3 - 6 / 3 * 2 ; End endmodule //poweroperator & function test module keyword_test; integer i; parameter depth =16; integer funct; initial begin for(i=0;2**i < depth;i=i+1) if(2**i==depth2);
  • else funct=i+1; end initial $monitor(funct); endmodule `timescale 1ns/1ps Create the log file using log system task module log_test(); reg x; initial begin $monitor("%d ",x,$time); x=1'bx; #10 x=1'b0; #10 x=1'b1; #10 x=1'b0; #10 $finish; end initial begin $monitor(x); $log("log_test.v");// to store the output into logfile end endmodule CHECK THE TIMESCALE `timescale 10ns/1ns module mult_timescale; integer a; initial begin $monitor(a," ",$realtime); #1.55 a=1;
  • #1.55 a=0; end //initial begin $monitor("%t ",$realtime); // if you are using%t for time it will displayas //multiplybythe time unit as for the time precision value // end endmodule module negative_number_test(); reg [7:0]a; reg [1:0]b=-3; initial begin $monitor("%b %d %d",a,b,$time); a=8'b10101101; #10 a=a >> (b); #10 $finish; end endmodule precedence test `timescale 1ns/1ns module operator_test; integer y; initial begin y= 3 + 3 - 6 / 3 * 2 ;
  • #6 $display(y);end Endmodule Define parameter test module param_test; defparam one.MEM_SIZE=300;// overwriting parameter one #(400)one();// instantiationtime overwriting endmodule module one; //module one parameter MEM_SIZE=100; initial $display("MEM_SIZE=%3d",MEM_SIZE); // defparam has higher priority endmodule`timescale 1ns/1ns module part_select; reg [7:0] data; initial begin $monitor(data,$time); data=8'd0; #10; //data[0:3]= 4'b1110; //Reversed part-select index expression ordering
  • data[3:0] = 4'b1110; //right part selection #50 $finish; end endmodule random value generation & shift operator `timescale 1ns/1ps module random_test(); reg [7:0]a; reg [1:0]b=-1; initial begin $monitor("%d %b %b",$time,a,b); a=$random; #10 a=a>>(b); #10 $finish; end endmodule system task memread test `timescale 1ns/1ps module always_read_mem; reg [7:0]data[2:0]; integer i; initial begin $readmemb("mem_data.v",data);
  • for (i=0; i < 3; i= i+1) $displayo("data=%b",data[i]); end endmodule Repeat loop test `timescale 1ns/1ns module repeat_test; integer dout=5.3; integer data=3.5; initial begin repeat(data)begin data=data+1; #2; end end initial begin repeat(dout)begin dout=dout+1; #2; end end initial $monitor("data=%2d,dout=%2d",data,dout); endmodule Check the triggering of the always with changing value of sensitivity list
  • module shifer; integer a=0; reg signed [3:0] data=-11; reg signed[3:0] d ; initial begin $monitor("%b,%b",data,d,$time); //data = -10; // data <= #2 data >> 2; #4 data= data >>> 3; end endmodule module testr12; integer x,y,z; wire [2:0]a; initial begin x=10; y=z=x;// this is an ERROR in verilog end initial $monitor(x,y,z,$time); endmodule check the format specification module test1; reg signed [2:0] m,n; initial begin $monitor($time," %b ",m," %b ", n); m = 0; n= 0; end
  • initial #10m = m + 1; initial #10n = n + 1'b1; endmodule module test_assign_deassign_test(); reg clk; reg clear; wire q; reg d; assign_deassign_test as(q,q1,sd,clk,clear); always #10 clk = ~ clk; initial begin $monitor("force release o/p = ",q," assign_deassign o/p = ",q1," clk = ", clk); clear=1'b0; clk=1'b0; d=1'b0; #50 clear = 1'b1; d=1'b1; #30 clear =1'b1; #50 clear =1'b0; #20 finish;end initial begin $recordfile("assign_dassign_test.trn"); $recordvars("depth = 0");
  • end endmodule `timescale 1ns/1ns module test_freq_div_3; reg clk_in; reg rst; wire clk_out; freq_div_5freq(clk_out,clk_in,rst); initial begin rst=1'b0; clk_in=1'b0;
  • #20 rst=1'b1; end initial forever clk_in = #10 ~clk_in; initial begin $recordfile("cl_div.trn"); $recordvars("depth=0"); #300 $finish; end endmodule `timescale 1ns/1ns module test_math; reg [3:0] A=4'b101Z; // 4 bit value of A reg [3:0] B=4'b1X10; // 4 bit value of B reg [3:0] C, D; // 4 bit value of C & D integer E,F,G; // 32 bit value of e, f & g
  • initial begin C=A+B; // mathematicaloperation ifoprands are X or Z // result => xxxx D=A^B; // bitwise operation E= 3 + 3 - 6 / 3 * 2 % 3; // operatorprecedence => / * % + - F = 3 + 3 - 6 / 3 * (2 % 3 ); // effect of paranthesis G = 3 + 3 - 6 / ((3 * 2) % 3 ) ; // divide be Zero infinte => X end initial begin $display("input data A=%b B=%b ",A,B); $display("mathematicalresult = ",C[3],C[2],C[1],C[0]); $display("bit wise result = " ,D[3],D[2],D[1],D[0]); $display("operatorprecedence result E =%2d F =%3d G =%3d",E,F,G); end endmodule
  • `timescale 1ns/1ps module abc; reg [3:0]a=4'b101X; reg [3:0]b=4'bX010; reg [3:0]c,d; integer e; initial begin c=a+b; d=a^b; e=3+3-6/3*2; end initial $monitor(c[0],c[1],c[2],c[3]," " ,d[0],d[1],d[2],d[3]," ",e); endmodule check the timescale & different system $time task `timescale 10ns/1ns module test_timescale; integer a,b;
  • initial begin #1.55 a=1; #1.55 a=0; $display(a,"time=%3d",$time); $display(a,"stime=%3d",$stime); $display(a,"realtime=%d",$realtime); end initial begin #1.55 b=0; #1.55 b=1; $display("n"); $display(b,"%t",$time); $display(b,"%t",$stime); $display(b,"%t",$realtime); end endmodule
  • `timescale 10ns/100ps module test_timescale; integer a; initial begin #2.2 $monitor("%t " ,$time); // without specifyingthe %t it will displaythe totel time taken by the end endmodule operator test module test; integer x ,y; reg [2:0] m,n; assign a = (x == y); initial begin m = 2; n= -2; $monitor(a,$time,x,y,"",m,"", n); #2
  • x= 4; y = 4; #10 x= 5; #10 y = 5; #10 y= 32'bxx; end initial #10m = m + 1; initial #10n = n + 1'b1; endmodule module casez_test(); integer y=0; reg [2:0]data=3'd0; reg [1:8*6] name; wire x=1'b0; initial name ="aeepak";// a stringis always declare as reg and start from 1 to 8*no of character in that word assign #10 x=~x; always @* casez (data) 3'b0x1: y=2; 3'b1xz: y=1; 3'b0x1: y=3; 3'b1x0: y=4; 3'b1xz: y=8;
  • default:y=0; endcase initial begin data=3'b1zz; #10 data =3'b01z; #10 data= 3'b001; #10 data = 3'bz11; #10 data=3'b010; #10data = 3'b100; #10 data=6; #10 data = 3'b101; #50 $finish; end initial begin $recordfile("case_test.trn"); $recordvars( "depth=0"); end endmodule module one_if_con(); reg x,y,b; wire z,a; wire sig; always @(a) // nested always block dont dare to delate it if u do it will make blast connected to system f ile
  • begin b=a; always @* if(sig) x=y; else y=z; end endmodule module reg_test(); reg a; reg y; reg clk=0; /*initial begin x = 'o15; #10 x= 'hz3; #10 x=23; #10 x= 8'bx1; #20; end*/ initial begin a=1'bx;
  • #1 a=1'bz; #200 $finish; end initial begin $monitor(y,clk); y=0; repeat (3) y = y+1; while (1) clk =~ clk; end always @(a) $display("the output is %b",a); initialbegin $recordfile("register.trn"); $recordvars("depth=0"); end endmodule module register_test(a,d,clk); output d; input a; input clk;
  • reg b,c,d; always @(posedge clk) begin b=a; c=b; d=c; end endmodule module reg_test(); reg a; /*initial begin x = 'o15; #10 x= 'hz3; #10 x=23; #10 x= 8'bx1; #20; end*/ initial begin a=1'bx; #1 a=1'bz; #20 $finish; end always
  • $display("the output is %b",a); Initial begin $recordfile("register.trn"); $recordvars("depth=0"); end endmodule module reg_test(); reg a; integer y=0; reg clk=0; reg [3:0] m,n; reg [4:0]mn; initial begin a=1'bx; #200 $finish; end initial begin $monitor("sum is %b",mn,$time,data,$printtimescale); m=4'b0101; n=4'b1101; #15 mn=m+n >> 1; //mn=({1'b0,m} + {1'b0,n}) >> 1;
  • end initial begin //$monitor("yis %d",y); repeat (a) y = y+1; end initial begin //while (1) clk =~ clk; end always @(a) $display("the output is %b",a); Initial begin $recordfile("re.trn"); $recordvars("depth=0"); end and (o,a,b); and (o1,a1,b1); wire [6:0] data; assign data= {3{2'd2}}; reg [2:0] dadd; /*initial // data generation between 45 to 55;
  • begin repeat (10) begin dadd= $random; #10 data = 'd44 +dadd; end end*/ endmodule `timescale 1ps/1ps module test_file; reg [7:0]y; reg [7:0]x; reg [1:0]n; reg [7:0]z; reg ctrl; reg [4:0]p; reg [1:8*6]name; reg [7:0]sig; wire [1:8*6]my_name; mult_bi_if_cond good(x,y,sig,name,my_name); initial begin
  • $monitor("%b, %b %b",x,y,z,$time); // what is the output if i shift any no with negative no; name = "deepak"; x =8'b1101_1010; // handlingwith negativeno //x =8'b_1101_1010; //this is error the first bit cant declare as underscore #20 x={1'b01,2'd2,4'h4,1'b0}; sig =0; n = -1; #5 name="Floria"; x <= x >> 3; y <= x >>> 3; z <= x <<< 3; p=2**3; ctrl=1'b0; #10 sig =1'b1; #20 sig =1'b0; ctrl=1'b1; #10 sig =1'b1; #10 ctrl=1'b0; #50 $finish;
  • end /*always @(sig)@(ctrl) // always blockone condition with multiple snnstivitylist saperatly if(sig) x=y; else y=z; */ /*always // one always without condition if(sig) x=y; else y=z; */ always @(x) if(x) x=y; else y=z; initial begin $dumpfile("test.vcd");
  • $dumpvars; end /*initial begin $recordfile("test.trn"); $recordvars("depth=0"); end*/ endmodule module test_top(a,b); input a; output b; reg b; always @(a) b=a; endmodule `timescale 1ns/1ps module test; reg [7:0]x; wire clk=1'b0; //assign clk= #10 ~clk; not #10(clk,clk); or #10 (clk,clk,(not (clk,clk)); initial begin $monitor("%d %t",x,$time);
  • x=8'd0; #20 x={1'b1,2'd2,4'h4,1'b0};// concatenation ofmultiple data type in single variable #10 x={1'b0,2'd2,4'h3,1'b0}; #1.5 x=8'd23; #20; end initial begin $recordfile("te.trn"); $recordvars("depth=0"); end endmodule System task test `timescale 1ns/1ps module always_test(); reg x; initial begin #10.243443515 x=1'b1; x=1'b0; $strobe("%b %t",x,$realtime);
  • $timeformat(-10,6,"time_unit",2); #10; x=1'b1; #10 $finish; $save(0); end endmodule `timescale 10ns/1ns module timescale_test; realtime r; integer x; initial begin #2.111312 x=$realtime; $display("%t ",x); $timeformat(-6,4,"ns",4); //$printtimescale; #10 $finish; end endmodule
  • `timescale 1ns/1ns module wait_test(); reg x=1'b0; reg out=1'b0; initial #50$finish; always #10 x = ~x; // test the follwing code the always blockneed some delays always begin wait (x==1'b1) #2 out=~out; end //endmodule initial begin $recordfile("wait_test.trn"); $recordvars("depth = 0"); end endmodule
  • Frequency div By 5 `timescale 1ns/1ns module test_freq_div_5; reg clk_in; reg rst; wire clk_out; freq_div_5freq(clk_in,clk_out,rst); initial begin rst=1'b0; clk_in=1'b0; #20 rst=1'b1; end initial foreverclk_in = #10 ~clk_in; initial begin $recordfile("cl_div5.trn"); $recordvars("depth=0"); #300 $finish; end
  • endmodule Synthesize the following code & find the hardware module block_hardware_test_comb(temp1,temp2,temp3,a,b); input a,b; output temp1,temp2,temp3; reg temp1,temp2,temp3; always @(*) begin temp1 = a^b; temp2 = a|b; temp3 = a&b; end endmodule `timescale 1ns/1ns module block_hardware_test_clk(clk,temp1,temp2,temp3,a,b); input clk,a,b; output temp1,temp2,temp3; reg temp1,temp2,temp3; always @(posedge clk) begin temp1 = a^b; temp2 = a|b;
  • temp3 = a&b; end endmodule `timescale 1ns/1ns module block_hardware_test(clk,temp,a,b); input clk,a,b; output temp; reg temp; always @* begin temp <= a^b; temp <= a|b; temp <= a&b; end endmodule `timescale 1ns/1ns module counter_hardware(count,count_en,clk,rst); output [2:0]count; input count_en;
  • input clk; input rst; reg [2:0]count; always @(posedge clk, negedge rst) if(!rst) count <= 3'd0; else if (count_en) count <= count + 1; else count <= 3'd0; endmodule `timescale 1ns/1ns module count_hardare(count,clk,reset); output [2:0] count; input clk; input reset; always @(posedge clk ,negedge reset) if(!reset) count <= 3'd0; else count = count + 1; endmodule
  • `timescale 1ns/1ps module abc(a,b,,e,f); input [3:0]a,b; output reg [3:0] e,f; always @* begin e=a&&b; f=a||b; end endmodule module ff_no_else_hardware(q,d,y,x); input x,y; input d; output q; reg q; always @(*) begin if(x==1'b1) q<=1'b0; end endmodule
  • module ff_test_asyn_hardware_new(q,d,clk,rst); input clk ,rst; input d; output q; reg q; always @(posedge clk,posedge rst) begin if(rst==1'b1) q<=1'b0; else q<=d; end endmodule `timescale 1ns/1ns module freq_div_3(clk_out,clk_in,rst); output clk_out; input rst,clk_in; reg FF1,FF2,FF3; wire temp_clk_in; always @(posedge clk_in,negedge rst) begin
  • if(!rst) {FF1,FF2}<=2'd0; else begin FF1<=(~FF1)&(~FF2); FF2<=FF1; end end always @(posedge temp_clk_in,negedge rst) if(!rst) FF3<=1'b0; else FF3<=FF2; assign temp_clk_in=~clk_in; assign clk_out= FF2|FF3; endmodule `timescale 1ns/1ns module freq_div_5(clk_in,clk_out,rst); output clk_out; input clk_in; input rst;
  • reg [2:0]count; reg clk_B; wire clk_A; always @(posedge clk_in,negedge rst) begin if(!rst) count<=3'd0; else if(count==3'b100) count<=3'd0; else count<=count+1; end assign clk_A=count[1]; always @(negedge clk_in,negedge rst) if(!rst) clk_B<= 1'b0; else clk_B<=clk_A; assign clk_out=clk_A|clk_B; endmodule `timescale 1ns/1ns
  • module funct_hardware_test(dout,din); output [7:0]dout ; input [7:0] din; assign dout = funct(din); function integer funct(input integer din); integer i; begin funct=1; for(i=din;i < 5;i=i+1) funct=i+1; end endfunction endmodule `timescale 1ns/1ns module hardware_contineous_assignment(a,b,c); input a; output b; output c; assign c=a; assign c=b; endmodule
  • `timescale 1ns/1ns module hardware_test(a,b,c); input b; output c,a; reg c,a; always @* begin a=b; c=a; end endmodule `timescale 1ns/1ns module hardware_without_full_trigger_2(a,b,c,d,e); input a; input b,e; output c,d; reg c,d,f,g; always @(a) begin
  • c = a & b; d= e | b; end endmodule `timescale 1ns/1ns module integer_test_hardware(input clk,rst,input [3:0]a,output dout); integer dout; always @(posedge clk,negedge rst) begin if(!rst) dout<=4'b0; else dout<=a; end endmodule `timescale 1ns/1ns module logical_test_hardware(input [3:0] A,B,output reg[3:0] C,D,E,F); always @* begin C=A&B;
  • D=A&&B; E=A|B; F=A||B; end endmodule `timescale 1ns/1ns module nonbloc_test_hardware(clk,temp,a,b); input clk,a,b; output temp; reg temp; always @* begin temp <= a^b; temp <= a|b; temp <= a&b; end endmodule `timescale 1ns/1ns module nonblock_hardware_test_var(clk,temp1,temp2,temp3,a,b); input clk,a,b;
  • output temp1,temp2,temp3; reg temp1,temp2,temp3; always @(posedge clk) begin temp1 <= a^b; temp2 <= temp1|b; temp3 <= temp2&b; end endmodule `timescale 1ns/1ns module test_cond_hardware2(ain,bin,dout,out1); input ain,bin; output dout,out1; reg dout,out1; always @(ain,bin) begin if(ain)begin dout = 1; out1= dout;end end endmodule
  • module string_hardware_test(clk,dout,din); input clk; output [8*1:0]dout; input [8*1:0]din; reg [8*1:0]dout; always@(posedge clk) dout<=din; endmodule `timescale 1ns/1ns module test_case_hardware(din,dout,insr); input [1:0]insr; input [3:0]din; output dout; reg dout; always @(*) begin case (insr)
  • 2'b00: dout = din[0]; 2'b01: dout = din[1]; 2'b10: dout = din[2]; endcase end endmodule Synthesize the following code & find the hardware `timescale 1ns/1ns module test_hardware_block(a,clk,temp1,temp2,temp3); reg clk; input a,clk; output temp1,temp2,temp3; reg temp1,temp2,temp3; always @(posedge clk) begin temp1 =a; temp2 =temp1; temp3 =temp2; end endmodule
  • `timescale 1ns/1ns module test_hardware_comb_block(din,enable,dout); reg dout; input enable; input din; output dout; always @(enable or din) begin if(enable ) dout <= din; else dout <= 1'b0; end endmodule `timescale 1ns/1ns module test_hardware_math_block_without_paran(add_result,int_a,int_b,int_c,int _d,int_e); input [2:0] int_a,int_b,int_c,int_d,int_e;
  • output integer add_result; always @* begin add_result=int_a+ int_b + int_c + int_d; end endmodule `timescale 1ns/1ns module test_hardware__multbit_cond(din,data,dout); reg dout; input [7:0]data; input din; output dout; always @* begin if(data ) dout<=din; else dout<=~din; end
  • endmodule `timescale 1ns/1ns module test_hardware_star(temp1,temp2,temp3); output temp1,temp2,temp3; reg temp1,temp2,temp3; always @(*) begin temp1 <=1'b1; temp2 <=temp1; temp3 <=temp2; end endmodule module test_hardware_block1(a,temp1,temp2,temp3); reg clk; input a; output temp1,temp2,temp3; reg temp1,temp2,temp3; always @(posedge clk) begin temp1 =a; temp2 =temp1; temp3 =temp2; end
  • endmodule module test_cond_hardware2(ain,bin,enable,dout); reg dout; input enable; input ain,bin; output dout; always @(*) begin dout<=1'b0; if(enable ) dout <= ain; end endmodule