Divide by N clock

Divide by clock Deepak Floria deepakfloria@gmail.com

Clock• Clock refers to any device for measuring and displaying the time.• Clock is repetitive in nature after some time period.

System Clock• Every modern PC has multiple system clocks.• Each of these vibrates at a specific frequency, normally measured in MHz .• A clock "tick" is the smallest unit of time in which processing happens, and is sometimes called a cycle.clock

System Clock• Some types of work can be done in one cycle while others require many.• The ticking of these clocks is what drives the various circuits in the PC, and the faster they tick, the more performance you get from your machine.

Clock Periodclock On Time = t Off Time= t On Time Off Time On Time Off Time • On time = off time 2t • Total time = T = 2t Duty Cycle = [(On Time/Total time) * 100 ]% Duty Cycle = t /T * 100 % = t/2t *100 % = 50%

Clock ` Parameters Positive Edge Positive Level Negative Edge Negative LevelPosedge to negedge => posLevel => On time => High LevelNegedge to posedge => neg level => Off time => Low LevelClock Period => Posedge To Posedge or Negedge to Negedge

Divide by ClockReferenceclock • In SOC some type of job done in one clock and others in multiple cycle. • There are many types of Buses inside SOC system. • These buses works at different clock signal but take reference from the main system clock. • Taking Reference as the main System clock we perform the Divide by Clock operations.

Divide by 2N• Freq divide By 2N• N=1 => Divide By 2ReferenceClock T = 2t F = 1/TDerivedClock T = 2t F = 1/2T

Divide by 2• Counter: A counter is a device which works on each edge of the clock and count the number of clock pulses.• Mod 2 Counter: Mod 2 counter will count two clock pulses of the clock signal.• A mod 2 counter is exactly working for two clock cycle. Clk Count Clock pulses X X 0 0 0 1 1 1 2

Divide by 2 Mod 2 Counter d Q Reference Clock D-FF Div/2 Clock Q’ ResetReference Clock T = 2t Q = Div/2 Clk T = 2T

Divide by 4 • Freq divide By 2N • N=2 => Divide By 4ReferenceClockDerivedClock Clk period T = 4T Freq F= 1/T ‘=> 1/4T

Divide by 4• Mod 4 Counter: Mod 4 Clk Count Clock Johnson counter will Q1 Q0 pulses count Four clock pulses X X X 0 of the clock signal. 1 0 0 1• Consider the second FF 1 0 1 2 Q1 output which is high 1 1 1 3 for two Clock & low For 1 1 0 4 Two Clock Cycle

Divide by 4 d0 d1 Q1 Q0 D-FF Clock D-FF Clock Q0’ Q1’ Reset ResetReferenceClock

Divide by 4 • Freq divide By 2N • N=2 => Divide By 4ReferenceClock T = 2t F = 1/T 0 1 1 0 0 1 1 0 Q0Q1 Derived 0 0 1 1 0 0 1 1Clock T = 4T F = 1/4T

Alternative way to Div/4 d0 d1 Q1 Q0 D-FF Clock D-FF Clock Q0’ Q1’ Reset Reset Pass the O/P of the 1st FF to the next FFReference as Clk signalClock

Alternative way to Div/4Reference Clock T = 2t Q0 = Div/2 Clk Ref clk to 2nd FF Q1 = Div/4 Clk T’ = 4T

Divide by 8 counter• Freq divide By 2N• N=3 => Divide By 8 clk Count Clock• A divide by 8 counter requires Q2 Q1 Q0 Cycle three flip flops X X X X 0• It has 8 possible states 1 0 0 0 1 1 0 0 1 2• The Q’ output of the third FF is 1 0 1 0 3 given as an input to the first flip 1 0 1 1 4 flop 1 1 0 0 5 1 1 0 1 6 O/P of the 3rd FF is high for 3 1 1 1 0 7 clk cycle & low for 3 clk Cycle. 1 1 1 1 8 This is the required Div/8 Clk signal

Waveform for Divide by 8 clockCLK T=2t Q T’ = 8T

Divide by 8 counter Logic Diagram DA QA DB QB DC QC Div/8 DFF DFF DFF CLK

Alternative way to Div/8 d0 d1 Q1 Q0 Div/8 D-FF D-FF D-FF Clock Clock Clock Q1’ Q0’ Reset Reset Reset Pass the O/P of theReference Clock one FF to the next FF as Clk signal

Alternative way to Div/8Reference Clock T = 2tQ0 = Div/2 ClkQ2 = Div/8 Clk T’ = 8T

Divide by 16 counter• Freq divide By 2N• N=4 => Divide By 16• A divide by 16 counter requires 4 flip flops• It has 16 possible states.• The Q’ output of the last flip flop is connected to input to the first flip flop

clk Count Clock Q3 Q2 Q1 Q0 Cycle X X X X X 0 1 0 0 0 0 1 1 0 0 0 1 2 The last FF O/P 1 0 0 1 0 3value is low for 8 1 0 0 1 1 4 1 0 1 0 0 5 clk cycle & high 1 0 1 0 1 6 for 8 clk cycle. 1 0 1 1 0 7 This O/P is the 1 0 1 1 1 8required Div/16 1 1 0 0 0 9 clk signal. 1 1 0 0 1 10 1 1 0 1 0 11 1 1 0 1 1 12 1 1 1 0 0 13 1 1 1 0 1 14 1 1 1 1 0 15 1 1 1 1 1 16

Divide by 16 counterCLK T= 2tQ 8T T ‘ = 16 T F = 1/16T

Divide by 16 counter Logic Diagram DA QA DB QB DC QC DD QD Div/16 DFF DFF DFF DFF QDCLK

Divide by 2N• Freq divide By 2N• N=N => Divide By NReferenceClock T = 2t F = 1/TDerivedClock T = NT F = 1/NT

Divide by 2 N d0 d1 d2 dN Q1 Q0 Div/N Q2 D-FF D-FF D-FF D-FF Clock Clock Clock Clock Q1’ Q2’ QN’ Q0’ Reset Reset Reset ResetReferenceClock

Divide by 3• A divide by 3 clock Clk Count Clock pulses requires A mod 3 Counter. Q1 Q0• It can be constructed X X X 0 using 2 FF.• It has 4 possible states 1 0 0 1 and it needs only 3 states 1 0 1 2 1 1 0 3 Observe the OP of 2nd FF

Divide by 3• Pass the Div/ second FF O/P 3 clk to one more FF which is d0 d1 d Q Q0 triggered as Q1 negedge of clk. D-FF D-FF D-FF Clock Clock Q1’ Q’• Make ORing of Q0’ Q1 & Q. Reset Reset• This is the require Div/3 50 % duty cycle Reference Clock Clk circuit.

Waveform for Divide by 3 • Freq divide By3ReferenceClock T = 2t F = 1/T 0 1 0 0 1 0 0 1 Q0 Q1 0 0 1 0 0 1 1 1 Q Div/3 clk T = 3T

Divide by 5 clock• A divide by 5 counter requires can be developed using Mod 5 Counter in similar method.• To get 50% duty cycle output one more flip flop is added and it is negative edge triggered.• Pass the output of the second Clk Count cycle Q2 Q1 Q0 • Pass the output of the second X X X X 0 FF to one more FF which is 1 0 0 0 1 triggered with negedge of clk then make ORing of these 1 0 0 1 2 two. 1 0 1 0 3 1 0 1 1 4 Observe the output of second FF. It is High for 2 1 1 0 0 5 cycle & low for 3 cycle.

Waveform for Divide by 5CLK T =2tQB 2T QD t’= 2+1/2 TQB + Q D T’=5T

Divide by 5 Clock Logic Diagram Y . DA QA . DB QB . DC QC DD QD QA QB QCCLK

Divide by 6 counter• Div/6 can be constructed by johnson counter.• A Div/6 Johnson counter requires 3 bit FF. Clk Count cycle The O/P of the 1st FF is Q2 Q1 Q0 high for 3 clk cycle & X X X X 0 low for 3 clk cycle. This is the Required 1 0 0 0 1 Div/6 clk signal. 1 1 0 0 2 1 1 1 0 3 1 1 1 1 4 1 0 1 1 5 1 0 0 1 6

Wavaeform for Divide by 6 counterClk T=2t 3T Q T’ = 6T

Divide by 7 counter• A divide by 7 counter requires Mod 7 Clk Count cycle Q2 Q1 Q0 counter. X X X X 0• It has 8 possible 1 0 0 0 1 states and it needs 1 0 0 1 2 1 0 1 0 3 only 7 states. 1 0 1 1 4 1 1 0 0 5 The O/P of the 3rd FF is High for 3 clk cycle & low for 3 clk cycle. 1 1 0 1 6 Pass this O/P to one more FF which 1 1 1 0 7 will work negedge of Clk then make ORing of these two O/P.

Divide by 7 counter 1 2 3 4 5 6 7 1 2 3 4 5 6 CLK 2t 6T QA QD 7TQA + Q D T’=7T

Divide by 7 counter Logic Diagram . Y . DA QA . DB QB DC QC DD QD QA QB QCCLK

Divide by 9 counter• A divide by 9 counter clk Count Clock Q3 Q2 Q1 Q0 Cycle requires Mod 9 counter. X X X X X 0• It has 16 possible states 1 0 0 0 0 1 and it needs only 9 states 1 0 0 0 1 2 1 0 0 1 0 3 The 3rd FF O/P value is low for 5 clk 1 0 0 1 1 4 cycle & high for 4 clk cycle. 1 0 1 0 0 5 This O/P is the required Div/9 clk signal but not 50% duty cycle. 1 0 1 0 1 6 Pass this O/P to one more FF 1 0 1 1 0 7 triggered with negedge clk and 1 0 1 1 1 8 then make Oring fo these two signal to 50% duty cycle. 1 1 0 0 0 9 1 1 0 0 1 10

Divide by 9 counter 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6CLK 2T 4TQBQE 4+1/2TQB + Q E T’=9T

Div/9 counter Logic Diagram . Y . . DA QA DB QB . DC QC . DD QD DE QE QA QB QC QDCLK .

ThankYouDeepak floria

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Divide by N clock

by DeepakFloria on Dec 13, 2011

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