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Verification of Wireless SoCs: No Longer in the Dark Ages
 

Verification of Wireless SoCs: No Longer in the Dark Ages

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    Verification of Wireless SoCs: No Longer in the Dark Ages Verification of Wireless SoCs: No Longer in the Dark Ages Presentation Transcript

    • J. Scott RunnerSr. Director of Design Verification Verification of Wireless SoCs: No Longer in the Dark Ages
    • Talk Outline The Mobile Device Era What’s in a highly integrated wireless chipset today? Challenges and Opportunities in the Mobile Era Traditional Wireless Verification Next Generation Wireless Verification Summary: Are you ready? “If it isn’t tested, it doesn’t work” Dr. Klein Gilhousen (Qualcomm Co-founder) Dr. Roberto Padovani (Qualcomm CTO) PAGE 2 QCT QMS Review I Q2 ‘06 | April 12, 2006
    • Exit: The PC Era, Entering: the Mobile Device Era Highly integrated, Highly Heterogeneous, Interoperable PAGE 3 QCT QMS Review I Q2 ‘06 | April 12, 2006
    • Today’s Highly Integrated Wireless Devices WAN Modems (CDMA, Application RF PM UMTS…) RISC GSM/GPRS GPS WLAN/PAN 3D Graphics Modems DSP Hi res Video Audio Memory Peripherals Multiple processors (multiple RISC, multiple DSP) Multiple processors (multiple RISC, multiple DSP) Many modems (WAN, LAN, PAN) Many modems (WAN, LAN, PAN) Significant multi-media (graphics, video, video) Significant multi-media (graphics, video, video) Many peripherals: wired and wireless: SD, USB, PCIe,… Many peripherals: wired and wireless: SD, USB, PCIe,… Special functions: security, power Special functions: security, power RF, analog mixed signal, digital RF, analog mixed signal, digital A lot of memory A lot of memory SIP (System in Package) or SoC (System on a die) SIP (System in Package) or SoC (System on a die) Concurrency: e.g. modem + GPS + applications + multi-media for Concurrency: e.g. modem + GPS + applications + multi-media for advanced location basedQ2 ‘06 | April 12, 2006 advanced location based services PAGE 4 QCT QMS Review I services
    • SW/FW a Significant Part of Wireless Mobile Solutions • Support multiple OSes • Millions of lines of SW code • Comm stack • Multi-media stack • Peripheral drivers • Hard real time, soft real time and non- real time • Functionality is increasingly SW programmable • Increase in concurrent SW threads in embedded • HW-SW interactions must be robust • Download feature updates may hit new design functions – how well tested? • No longer sufficient for “SW to be booted”. Extensive HW-SW interaction verification required. • Significant SW reuse requirement PAGE 5 QCT QMS Review I Q2 ‘06 | April 12, 2006
    • Key Challenges & trends of the Mobile Era Rich Feature roadmap: Lots of product features in demand Many consumers buy new cellphone models every 9-12 months with new features Cost is Critical: Highly integrated heterogeneous devices Phone + camera + camcorder + music player + PDA + location-based services + push-to-talk + ultra- mobile PC Power Conscious New power reduction schemes have complex functional implications Cost is a function of quality (excuse by Philip Crosby) Transparent Interoperability critical Many communication protocols, on the fly…concurrently – WAN: CDMA2000, UMTS/WCDMA, OFDM, LTE – LAN: WiFi/ OFDM… – PAN/BAN: Bluetooth, USB, UWB, etc. Heterogeneous and extremely variable HW architectures to support – higher concurrency MCP: Multiple processors/DSPs and HW acceleration. Greatly increasing number of HW and SW threads. – Scalable: ability to move task between RISC, DSP, HW Increasingly more programmable, yet special purpose (i.e. heterogeneous) HW RF/Analog mixed-signal integration Non-orthogonal HW (power, security, etc). Increased levels of heterogeneous concurrency – Exponential: More threads per functional unit….more units Embedded Software complexity growth is even faster than HW SIGNIFICANT amount of embedded SW. SW complexity doubles faster than Moore’s Law PAGE 6 QCT QMS Review I Q2 ‘06 | April 12, 2006
    • Wireless Verification: The “Dark Ages”Golden System Vectors Spec Algorithm Algorithm RTL Verification RTL Verification Cfg/ DF Validation Validation System Model Matlab, SystemC/C++/C DUV Input Expected Analysis compare cfg Data Output results cfg driver DF driver Monitor Bit accurate system model used for fixed pt modeling of algorithm transformation DUV • Matlab • C++/SystemC Disadvantages: • Lack of reactivity “system vectors” pre generated as “golden • Black-box: generally produces 25-75% vectors” functional coverage Played against DUT with simple bit accurate • Lack of Functional Coverage comparison • Interactions: Reactivity for Complex Crosses • Controllability/ visibility granularity PAGE 7 • Lack of support for integration verification QCT QMS Review I Q2 ‘06 | April 12, 2006
    • Wireless Verification: The Modern EraModel Based Spec Algorithm Algorithm RTL Verification RTL Verification Cfg/ DF Validation Validation wavefrm algorithm C/xaction Tests debugger debugger debugger System Model Matlab, SystemC/C++/C Constraints Assertions Generator DUV Input Expected cfg Data Output Self-Check Cov mdl Transactor compare Coverage System Mdl Database Reference Analysis Model cfg xactor DF xactor Monitor Xaction Watch pts Level Log Bit accurate system model used for fixed pt modeling of algorithm transformation DUV • Matlab • C++/SystemC Advantages: • Integrated Analysis (not just stand • Reactive to temporal variations in DUV alone) •Tends to foster other verification Reuse the model, not system vectors enhancements: assertions at different levels Spec becomes: - model of integration & abstraction - constraints • Enables achievement of 100% coverage - assertions • Support successive integration verification & debug PAGE 8 • Caveat:Review I Q2 ‘06 | April planned modelling strategy QCT QMS Requires 12, 2006
    • Results: Constraint-based (CB)/Directed Random + ABV Works! 6K VFE Cumulative Defects Golden VectorsPercentage of bugs detected 16 by Method 14 Cumulative CR Count 12 Control Dominant 10 CRITICAL HIGH 8 Assertions Assertions 30% 30% MEDIUM Scoreboard Checkers Scoreboard Checkers 61% 61% 6 LOW Linting Linting 4% 4% 4 Other Other 5% 5% 2 0 Dataflow Dominant De 04 De 5 Ap 4 Ap 5 Ap 6 Ju 4 O 4 Ju 5 O 5 Ju 6 Au 4 Au 5 06 Fe 3 Fe 4 Fe 5 0 0 -0 0 0 0 r-0 r-0 r-0 0 0 0 0 0 - b- b- b- g- g- c- n- n- n- c- c- ct ct Assertions 20% De Assertions 20% HVL Constraint-based Scoreboard Checkers Scoreboard Checkers 72% 72% 7K VFE Cumulative Defects Linting Linting 3% 3% Other Other 5% 5% 20 18 Less than ½ the time to stabilize 16 Cumulative CR CountSignificant reduction in post silicon 14 CRITICAL 12defects 10 HIGH MEDIUM 8Faster time to stability 6 LOWIncreased predictability 4 2 0 4 5 05 06 05 5 6 05 06 04 05 -0 -0 r-0 r-0 b- b- g- c- c- n- n- ct ct Ap Ap Fe Fe Au De De Ju Ju O O PAGE 9 QCT QMS Review I Q2 ‘06 | April 12, 2006
    • Verification of RF/AMS – Digital (“Big D/Little a”)PMIC SSBI padring Digital UARTs/ UIMs CLK Out Behavioral CLK Gen Model/ Camif Monitor SSBI Interface USB PLL Rx/Tx SSBI ARM926EJ UXMC Memory Quad Tx DAC Mod SD SD Wideband CDMA/GPS Interface Model Stereo Processors Codec A/D QDSP4000 Testplan Testplan High Linearity A/D Rx Buff Connectivity Connectivity Mode Select Driver Config Interface withMode Select Match with the pin list of the digital die Match Ext the pin list of the digital die ModelAnalog/RF General Purpose Interface Ability to toggle all the interconnections JTAG interconnections Interface to toggle all the Ability Digital Test Bus Model JTAG Validate polarities Validate polarities GPIO Interactivity Interactivity Model Point-to-point Point-to-point End-to-end (chain) End-to-end (chain) Full mission mode Full mission mode RF/ Concurrency Concurrency RF/ analog Digital Systems Scenarios Systems Scenarios AMS (MSM) All functional and structural configurations All functional and structural configurations Flow Digital Flow Support other components for common modes of Support other components for common modes of I/F Mdl operation operation PAGE 10 MultipleReview I Q2 ‘06 | Aprilchains Multiple concurrent chains QCT QMS concurrent 12, 2006
    • Implications of Power Management on Verification Medium Courtesy: Cadence Design Automation public white paper Complex power management techniques: dynamic voltage and frequency scaling, multi-Vt, head/foot switches, multiple voltage islands…etc are increasing design and verification complexity Interactions between functionality and physical power management not always obvious and require new methodologies Effects have “analogish” look to them (continuous voltage) HW-SW power interactions must be considered as well PAGE 11 QCT QMS Review I Q2 ‘06 | April 12, 2006
    • Summary: Are You Ready? The Mobile Era presents many challenges and opportunities for DV engineers Convergence of communications (WAN, LAN, PAN), multimedia, peripherals (wired and wireless), processors, SoC/SIP Hybrid technologies: RF, AMS, logic, memory Multiple challenges to deal with – Power, security Looks familiar? Confluence of domains and problems from processor, networking and other applications Requires advances in design & verification methods Key Trends Integration Heterogeneity Interoperability of different things Concurrency Know what you are verifying! Learn domains Domains have similarities Depth and breadth PAGE 12 QCT QMS Review I Q2 ‘06 | April 12, 2006
    • Roberto Padovanis (QCOM CTO) favorite quote: “If it isn’t tested, it doesn’t work” Dr. Klein Gilhousen (Qualcomm Co-founder) Thank you!