Validating Next Generation CPUs
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  • Prefer “validation-aware design” to DFV – emphasis needs to be on designers understanding what is needed to make validation effective & efficient

Validating Next Generation CPUs Presentation Transcript

  • 1. Validating next generation CPUs Praveen Vishakantaiah President, Intel India Feb 22, 2008 DV Club Bangalore
  • 2. “Validation is increasingly in the critical path of product success and requires continuous innovation to meet customer satisfaction, schedule and margin requirements”2
  • 3. Agenda• Current Challenges• Addressing the challenges3
  • 4. CPU bug trendsExponential growth of design complexity• Deeply pipelined complex micro-architecture• Logic bugs increase 3 - 4x per generation Pre-silicon logic bugs per generation 25000 ( Source: Tom Schubert, Intel, DAC 2003 ) 7855 800 2240 Pentium Pentium Pro Pentium 4 Next ? Up to 70% of design time and resources are spent during Up to 70% of design time and resources are spent during functional validation functional validation4
  • 5. The Pre-Si Verification gap EE Times 2004 EE Times 03/18/2004 Verification Capabilities is fast becoming the limiting Verification Capabilities is fast becoming the limiting5 factor for VLSI design improvements factor for VLSI design improvements
  • 6. Current Challenges – Technical• Increasing CPU design complexity – Multi core – Chipset integration – Power Management – New technology like security• Increasingly bulky validation environment – Increase in development and maintenance cost – Environment bugs >= Logic design bugs• Increasing number of product variants – Validation is not as incremental as design• Increasing micro-architectural coverage space increases probability of escapes• Decreasing simulation/emulation speed limits pre-silicon cycles• Legacy features and compatibility validation High volumes magnify the cost of a High volumes magnify the cost of a6 validation escape – can not let it happen! validation escape – can not let it happen!
  • 7. Current Challenges – Non-Technical• Shorter TTM (Time to Market)• Physical limits and cost of data centers• CPU validation expertise – More pronounced in India due to frequent job changes• Cross site development – Design and validation may not be co-located7
  • 8. Post-silicon validation• SOC and Multi core leverage incremental design effort – Design interactions are spatial in nature – Effective design reuse is possible• Post Si Validation efforts currently not scaling incrementally - Logic interactions across widely separated areas introduces unexpected bugs - No effective coverage feedback mechanism - When is Validation enough ? - Synthesis of approx coverage measure - Effective Mathematical Models8
  • 9. Addressing the challenges• Use experienced architects, micro-architects and front end designers – Very likely to have lot more validation “burn” marks and will proactively code less bugs – Will be able to help validators debug issues faster – Raise the watermark for bugs and reduce iterations• Validators drive requirements into architecture and micro-architecture – Influence technology decisions to keep validation tractable – Minimize feature creep during execution – Reduce back end design impact on front end design• Instrument design models to enable validation – Assertions, instrumentation signals, comments – Aim for sweet spot with Effectiveness vs. Efficiency trade offs• Validation Environment – Minimize custom tool development• Reuse design, validation and debug tools across programs• Scale emulation, formal verification and mixed signal validation9
  • 10. Validation coverage profile and Efficacy •Efficiency: Catch bugs fast •Effectiveness: Catch all customer visible bugs Probability of bugs Si Spin1 Si Spin2 Time Early detection and bug acceleration Early detection and bug acceleration10 has significant business benefits has significant business benefits
  • 11. Q&A11