The Verification Methodology Landscape
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  • 1. 1Copyright © 2008 by Doulos. All rights reserved.The Verification MethodologyLandscapeJonathan Bromley, DoulosDVClub Bristol 22-April-2009
  • 2. 2Copyright © 2008 by Doulos. All rights reserved.The VerificationMethodology LandscapeCONTENTSThe M-wordLanguages, methodologies, tools and standardsThe big players: OVM, VMM, eRMInteroperability and convergenceConclusions?
  • 3. 3Copyright © 2008 by Doulos. All rights reserved.TLMDUTMonitorDriverVerification EnvironmentStimulusgeneratorTransactionsCoveragecollectorTransactionrecordingTestcontrollerScoreboard /Checker
  • 4. 4Copyright © 2008 by Doulos. All rights reserved.DesignUnderTestConstrained Random Verification11001001010010100000100101110110011001100100100101001110000010010011000010100100001000110010000011Constrained randomstimulusCheckerDid we see a bug?FunctionalCoverageAre we done?Header Payload ChecksumConstraintsIncrease coverage
  • 5. 5Copyright © 2008 by Doulos. All rights reserved.The Verification SpaceVerificationAcceleration+ EmulationFormalVerificationSimulationEquivalenceCheckingPropertyCheckingDynamicFormalCoverageTransaction LevelModellingConstrainedRandomAssertionsSimulation SimulationSimulationFormalSimulationFormalIntelligentTestbench
  • 6. 6Copyright © 2008 by Doulos. All rights reserved.What Our Customers Want• Ease of deployment• Customizable environment• but it must do something useful straight out of the box• Simple, uniform interface to any verification IP block• Gentle learning curve for the whole team• Power• Complex testcases co-ordinated across the whole environment• Randomization• Sophisticated coverage analysis• Interoperability• Every customer we meet has legacy verification IP
  • 7. 7Copyright © 2008 by Doulos. All rights reserved.Methodology (or just a toolkit?)• Tame the language monster• e, SystemVerilog, C++ are big and complicated• Many ways to solve a problem• Wheel reinvention is a hazard• Toolkit• OOP encourages encapsulation of standard functionalityin base classes• Ideal for component hierarchy, reporting, block-to-blockcommunication, DUT connectivity• Methodology• Published methodology encourages interoperability and re-use• Promote best practice
  • 8. 8Copyright © 2008 by Doulos. All rights reserved.Mature Language Standards• IEEE 1076 VHDL• IEEE 1850™ PSL• IEEE 1364 Verilog• IEEE 1800™ SystemVerilog• IEEE 1647™ e• ISO/IEC 14882 C++• IEEE 1666™ SystemC• Tcl/Tk, PerlList unchanged for 4 years...8FPGA, RTL, Europe, Mil-AeroASIC, RTL, USA/RoWHardware verificationVirtual hardware prototypes for S/W devHardware verificationCrude CaricatureModelling, verificationScripting
  • 9. 9Copyright © 2008 by Doulos. All rights reserved.New Standards Activity• Verilog and SystemVerilog unified• LRM this year, currently in ballot feedback• Major enhancements to assertions• Verification methodology• OVM 2.0, OVM-SC• VMM open-source• eRM3 - e / SV interoperability (Cadence)• OVM / VMM interoperability (Accellera)• SystemC TLM-2.0
  • 10. 10Copyright © 2008 by Doulos. All rights reserved.The Big Methodology Playerswww.ovmworld.orgwww.vmmcentral.orgwww.cadence.comeRM
  • 11. 11Copyright © 2008 by Doulos. All rights reserved.EnvironmentStatic View of TestbenchDUTactiveagentDriverBFMMonitorBFMSequ-encerpassiveagentDriverBFMMonitorBFMSequ-encercheckerConfigurationsimple ports (e)virtual interfaces (SV)eRM
  • 12. 12Copyright © 2008 by Doulos. All rights reserved.Static View of Testbench (VMM)DUTGenerator...test_env env = new;env.run();...TransactorDriverSelf CheckMonitorHigh leveltransactionsCheckerMonitorFunctionalCoverageProperties CheckerAtomictransactionsConstraints;directed tests
  • 13. 13Copyright © 2008 by Doulos. All rights reserved.OVM Key Features• Constrained random, coverage-driven verification• Separation of tests from verification environment• Configuration of verification environment• through a table• Verification IP reuse (canonical structure and guidelines)• TLM communication• Automation (where missing from SystemVerilog language)• Hierarchical sequential stimulus (sequences)• Standardized messaging
  • 14. 14Copyright © 2008 by Doulos. All rights reserved.eRM Key Features• Constrained random, coverage-driven verification• Separation of tests from verification environment• Configuration of verification environment• through AOP extension and pre-run constraints• Verification IP reuse (rigorously standardized rules)• Communication via ports• Automation (using e languages macro features)• Hierarchical sequential stimulus (sequences)• Standardized messaging
  • 15. 15Copyright © 2008 by Doulos. All rights reserved.VMM Key Features• Constrained random, coverage-driven verification• Configuration of verification environment• through configuration objects passed to verification components• Verification IP reuse (conventions)• Communication via channels, callbacks, notifications• Automation (scripts and macros)• Hierarchical sequential stimulus (scenarios)• Standardized messaging• Strongly influenced by RVM (Synopsys Vera)
  • 16. 16Copyright © 2008 by Doulos. All rights reserved.Structure of an OVM Componentclass my_driver extends ovm_driver #(my_transaction);// ovm_seq_item_pull_port #(...) seq_item_port;my_dut_if_wrapper m_dut_if;function new(string name, ovm_component parent);super.new(name, parent);endfunction: newfunction void build;super.build();endfunction: buildvirtual task run;forever begin...endendtask: runendclass: my_driverTLM port (inherited)Connection to DUTConstructorBuild phasecallbackRun phasecallbackBase class
  • 17. 17Copyright © 2008 by Doulos. All rights reserved.Phase Methods (OVM)buildconnectend_of_elaborationstart_of_simulationrunextractcheckreportCall factoryMake TLM connectionsAfter connections hardenedPost-processingTask (executed concurrently)Get ready to runSimilar phase arrangements in VMM, eRM
  • 18. 18Copyright © 2008 by Doulos. All rights reserved.Reconfigurable Environment (OVM)DUTReusable verification environmentScoreboard VirtualsequencerMonitor ExistingverificationcomponentExistingverificationcomponentSequencerDriverMonitorConfigTestTestset_config_*Customize environmentsset_inst_override_*set_type_override_*Customize typesBy type or instance path
  • 19. 19Copyright © 2008 by Doulos. All rights reserved.Layered Sequential StimulusDUTDriverDrive transactions into DUTtx1 tx2 tx3Constrained randomsequence of transactionsseq1 seq2seq2Virtual or layeredsequencestx1Tests enumerate possibletop-level sequencesRandomized transactions are not enough
  • 20. 20Copyright © 2008 by Doulos. All rights reserved.ovm_envovm_agentVirtual Sequencesovm_sequencerovm_driverovm_sequencerComponent hierarchy Stimulus hierarchy(co-ordinated interfaces)DUTdut_ifovm_agentovm_sequencerovm_driverdut_ifovm_sequenceovm_sequence_itemovm_sequence
  • 21. 21Copyright © 2008 by Doulos. All rights reserved.Scenario Generator (VMM)Verification environmentScenario generatorDownstream transactorgenerators output channelatomicscenario_setburst[1][0]RMW[2]burstitemsselect_scenarioselectcopies of items
  • 22. 22Copyright © 2008 by Doulos. All rights reserved.Now and Next• VMM: rapidly growing collection of "applications"• register abstraction layer, hierarchy, ...• OVM/VMM interoperability toolkits/standards• OVM/eRM mixed-language tools• OVM-SC• Increasing availability of verification IP
  • 23. 23Copyright © 2008 by Doulos. All rights reserved.Conclusion• Interesting times• standards dont always keep up with user needs• Challenges for users choosing a new approach:• tools?• methodology?• decisions are not yet completely decoupled• Training is important:• VMM, OVM, eRM are not difficult ...• ... but jump-starting your efforts pays dividends
  • 24. 24Copyright © 2008 by Doulos. All rights reserved.