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OpenSPARC on FPGAs
 

OpenSPARC on FPGAs

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    OpenSPARC on FPGAs OpenSPARC on FPGAs Presentation Transcript

    • 1www.OpenSPARC.netOpenSPARC on FPGAsDurgam.Vahia@Sun.ComOpenSPARC Engineering & Partnership DevelopmentSun Microsystems, Inc.DV Club – July 2009
    • 264 bits, 64 threads, and freewww.OpenSPARC.net DV Club – Silicon ValleyOpenSPARCOpenSPARC.net Open source variants of Sun’sCMT microprocessorsUltraSPARC T1UltraSPARC T2 Governed by GPL version2 Widely used in Linux distribution US export compliant for world-wide distribution
    • 364 bits, 64 threads, and freewww.OpenSPARC.net DV Club – Silicon ValleyAgendaChip Multi-threadingOpenSPARCMotivation for the FPGA portImplementationResultsResourcesQ & A
    • 464 bits, 64 threads, and freewww.OpenSPARC.net DV Club – Silicon ValleyChip Multi-threading (CMT)
    • 564 bits, 64 threads, and freewww.OpenSPARC.net DV Club – Silicon ValleyUltraSPARC T1SPARC V9 ISA, 64-bitEight cores, four threadseachSingle issue 6-stage pipeHigh BW 12-wayassociative 3 MB on-chipL2 cache4 DDR2 channelsShared on-chip FPUChip IO through JBUS
    • 664 bits, 64 threads, and freewww.OpenSPARC.net DV Club – Silicon ValleySPARC Core PipelineInterface tothe core
    • 764 bits, 64 threads, and freewww.OpenSPARC.net DV Club – Silicon ValleyUltraSPARC T2x8 @2.5GHzFull Cross BarC0 C1 C2 C3 C4 C5 C6 C7FPU FPU FPU FPU FPU FPU FPU FPUL2$ L2$ L2$ L2$ L2$ L2$ L2$ L2$FB DIMM FB DIMM FB DIMM FB DIMMFB DIMM FB DIMM FB DIMM FB DIMMPCI-ExNIU(E-net+)Sys I/FBuffer Switch Core2x 10GE EthernetPower 60 – 123WMCU MCU MCU MCUEight cores, eight threadseach8-stage single issue pipeOne FPU per core16-way associative 4 MBon-chip L2 cacheFour dual channelFBDIMMTwo 10G EthernetPCIe and Cryptoexcluded
    • 864 bits, 64 threads, and freewww.OpenSPARC.net DV Club – Silicon ValleyOpenSPARC BundlesHardware− HDL design files written in Verilog− Verification test-bench, diagnostics, scripts− Synthesis scripts for ASIC and FPGA− Lots of documentsSoftware− SPARC Architecture Model (SAM) source− Full-system simulator (Legion) source− Hypervisor, Open Boot PROM (OBP) source− Solaris10 disk image− Scripts to build all the components
    • 964 bits, 64 threads, and freewww.OpenSPARC.net DV Club – Silicon ValleySource browser at www.opensparc.net
    • 1064 bits, 64 threads, and freewww.OpenSPARC.net DV Club – Silicon ValleyCommunity OpenSPARC.net Contests Blogs Conferences TutorialsOperating System Port Evangelize OpenSPARC Encourage contributions Build knowledgebaseUniversities Center of Excellence Collaborations Curriculum Research TutorialsPartners FPGA implementation ASIC implementation EDA SoC implementation Foundry relationship Chip spins Coprocessors CMT EDA toolsOpenSPARC Ecosystem Research publications Textbooks Shared courseworkAreaTool KitFocusEncourage community innovation
    • 1164 bits, 64 threads, and freewww.OpenSPARC.net DV Club – Silicon ValleyInnovationwill happen everywhereOpenSPARC momentumMore than 11,000 downloadsIncludes academic and commercial interests
    • 1264 bits, 64 threads, and freewww.OpenSPARC.net DV Club – Silicon ValleyAgendaChip Multi-threadingOpenSPARCMotivation for the FPGA portImplementationResultsResourcesQ & A
    • 1364 bits, 64 threads, and freewww.OpenSPARC.net DV Club – Silicon ValleyWhy FPGAs?Community requested it− As a platform for experimentation− Gentler introduction to server class processor design− Basic building block for more interesting/complexdesignsNeed off-the-shelf FPGA board that is− Large enough for “good-sized” design points− At the “right” price point− Available world-wide
    • 1464 bits, 64 threads, and freewww.OpenSPARC.net DV Club – Silicon ValleyOpenSPARC/Xilinx FPGA Evaluation KitAvailable from http://www.digilentinc.com/v5osdk
    • 1564 bits, 64 threads, and freewww.OpenSPARC.net DV Club – Silicon ValleyFPGA implementation – Key objectivesProliferation of OpenSPARC & XilinxFPGA Technology− Make OpenSPARC FPGA-Friendly− Create reference design with complete systemfunctionality− Boot Solaris and Linux− Open it up ..− Seed ideas in the community
    • 1664 bits, 64 threads, and freewww.OpenSPARC.net DV Club – Silicon ValleyProcessor core changesPrimarily to reduce the area foot-print ofthe multi-threaded SPARC coreRecode custom SRAM cells for better resource utilizationParameterizable single- and multi-thread optionsRemoval of all the asynchronous logic – no clock gatingSimplified resetOnly flops, no latchesReduce multi-port SRAM arraysRemovable logic – Crypto accelerator, Floating-pointOverall 50% reduction in area
    • 1764 bits, 64 threads, and freewww.OpenSPARC.net DV Club – Silicon ValleyOpenSPARC FPGA SystemSPARC T1 CoreMicroblaze ProcCCX-FSLInterfaceExternal DDR2 DimmMCH-OPB MemConMicroblaze Debug UARTSPARC T1 UART10/100 EthernetFPGA BoundaryXilinx EmbeddedDeveloper’s(EDK) Design
    • 1864 bits, 64 threads, and freewww.OpenSPARC.net DV Club – Silicon ValleySoftware Stack• Out-of-the-boxoperating systeminstallation• Boots from a virtualdisk in RAM whichholds the Solarisbinaries• Able to boot eitherLinux or OpenSolaris• Entire software stackis open sourceResetCode HypervisorOpen Boot PROM(OBP)Solaris/Linux
    • 1964 bits, 64 threads, and freewww.OpenSPARC.net DV Club – Silicon ValleyResults – Capacity Utilization• Using Xilinx XC5VLX110T device• Synthesis results (no SPU, 16 TLB entries)1-thread core: 31475 LUT (45%), 115BRAM (78%)4-thread core: 51558 LUT (74%), 115BRAM (78%)(synthesized with Synplicity Synplify Pro)• Complete system:SPARC core, MicroBlaze, 2 UARTs,Ethernet, and DDR2 controller:1-thread core: 38271 LUT (55%), 128
    • 2064 bits, 64 threads, and freewww.OpenSPARC.net DV Club – Silicon ValleyResults – Community building• 50+MHz OpenSPARC FPGA system– Platform for experimentation for HW developers– Building blocks to design truly multi-core, multi-threadprocessors– Based on open-source technology– Costs ~$700 for academics ($2,000 for others)– Higher-end boards available for larger design points• Used in 200+ Universities world-wide– Architectural exploration, fault tolerance, reconfigurablecomputing, low power architecturesFree download, visit http://www.opensparc.net
    • 2164 bits, 64 threads, and freewww.OpenSPARC.net DV Club – Silicon ValleyResults - Partnerhttp://www.beecube.com
    • 2264 bits, 64 threads, and freewww.OpenSPARC.net DV Club – Silicon ValleyKey Learnings• FPGA capacity and performance areincreasing each successive generation,however– Optimal use of these resources is a big challenge• FPGA design/coding is significantly differentfrom ASIC style– E.g. pipeline bypass, latches, clock gating creates bothfunctional and P&R issues– For prototyping, create special FPGA models• FPGA tools are full of quirks– Invest in verification at each level – RTL, gate, layout,system
    • 2364 bits, 64 threads, and freewww.OpenSPARC.net DV Club – Silicon ValleyWeb pointersProgram− http://www.opensparc.netPublications− http://www.opensparc.net/publications/Downloads− http://www.opensparc.net/opensparc-t1/downloads.html− http://www.opensparc.net/opensparc-t2/downloads.htmlParticipation (Forums)− http://forums.sun.com/category.jspa?categoryID=120FPGA development boards− http://www.digilentinc.com/v5osdk
    • 24www.OpenSPARC.netOpenSPARC on FPGAsDurgam.Vahia@Sun.ComOpenSPARC Engineering & Partnership DevelopmentSun Microsystems, Inc.www.OpenSPARC.net