Low-Power Design and Verification
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Low-Power Design and Verification Low-Power Design and Verification Presentation Transcript

  • Si2 - Innovation Through CollaborationSteven E. SchulzPresident and CEOMay 20th, 2008DVclub – Austin, TXLow-Power Designand Verification
  • 2Si2 – Innovation Through CollaborationToday’s Agenda
  • 3Si2 – Innovation Through CollaborationToday’s Agenda• Why Low-Power Now?• Design and VerificationFlow Challenges / Reqts• Common Power FormatIntroduction / Examples• Industry / Market Adoptionand Silicon Benefits• Introduction to the LowPower Coalition• 2008 Roadmap / Plans• Q & A
  • Page 3HereWeare2001 International Technology Roadmap for SemiconductorsP = ACV2f + VIleakJunctionLeakagePossible kink in dynamic power DynamicpowerSub-thresholdGateJunction
  • Page 2Power Motivation and RequirementsMobile applications trends:• Leakage is significantly increasing due to process scaling• Active power increases due to application integration (with the subsequentexponential increase in leakage). Current density is also on the increase.• Active leakage is now a significant portion of SoC active power budget.• Sleep mode techniques need to be enhanced and enabled in a consistentfashion throughout the design flow• We need a concerted effort applied to leakage minimization at the micro-architectural, system and software level.• Process variation now limits how much we can voltage scale and how wedo our power accounting, and therefore new strategies need to be developto capture these constraints, and enhance our current scalingapproaches/methodologies.
  • © 2006 Virage Logic Corporation – COMPANY CONFIDENTIALSlide 18Ultra-Low-Power ApplicationsAddressing a Wide Range of RequirementsUltra-Low-Power ApplicationsAddressing a Wide Range of Requirements
  • Excel Your Idea to Silicon 10PowerSmart™ -- Low PowerDesign MethodologyPower switch1.5V OP buffer1.5V OPD QckVdd_UPSVddRetentionflip-flopIsolation cellPower IslandsMulti-VtlibraryMulti-Vth (Fusion)clkenoIntegratedclock gated cellClock GatingLevel shifterLevel shifterMulti-outputregulatorRegulator1.2V1.0V0.8V3.3VMulti-VDDMulti-VDDlibrary1.2V1.0V0.8V Low powerIPSRAMLow Power IP
  • October 5, 20063Processor design for Power Efficiency:Different needs for different markets• Server market:– Defining property: Server processors are rarely idle.– Power goal: Increase MIPS/Watt in Power State C0 (ACPI).• Mobile market:– Defining property: Laptop processors are mostly idle.– Power goal: Reduce power in C2/C3 power states.• Techniques:– Clock gating– Multiple power domains– Multiple threshold voltages– Headers/footers– Operand Isolation (holding cell inputs stable when output is unused)– Dynamic voltage and frequency scaling– And others…
  • October 5, 20064Power analysis challenges:More complex than timing analysis• It is pattern-dependent.– Circuit and gate-level power analysis require good RTL-level patterns for accurateresults.• It is a balancing act. (power efficiency)– Performance per watt (efficiency) is the metric, not Watts. Need to find blocks ornets that consume power without appropriate performance benefit.– Many tools sort blocks and nets by total power consumption notperformance/watt. (E.g. clock nets burn a lot of power, but we already knewthat)• It is an aggregate (time and space) and a user-definedconstraint.– Power analysis types: average power (for budgeting & package selection), energy(for battery life), peak power (IR drop analysis), etc.– E.g. Briefly higher localized power consumption can be tolerated for packageselection, unless it exceeds limits.• It requires coordination of data from physical design, gate design,RTL, and verification domains.– It requires knowledge in all these domains to cross-check results.• Must allow for accuracy to be improved over time.– Detailed circuit-level power analysis data often comes too late in the design cycle.
  • October 5, 200611Other related issues: DFT and Timing• Are scan paths hooked up in the RTL? Are theysimulated in the Verilog? How are they verified?• How do you analyze power consumption in scanmode?• Timing also needs to know about the multiplevoltage domains and operating points.• Need to work on timing and power in oneenvironment to achieve correct optimization andtrade-offs.
  • Slide 8System Aspects require differing viewsLayoutAlgorithmBus ArchitectureImplementationPowerSourceTemperatureRefinementSecurityAddress SpaceDocumentation
  • Slide 9Address spaceLayoutAlgorithmBus ArchitectureImplementationPowerSourceTemperatureRefinementSecurityAddress SpaceDocumentation
  • Slide 10Aspect View: Bus Architectural layoutCPUCPUCPUFLASHFLASHUSBUSB UARTUART GPIOGPIOPLLPLLPeripheral BusProcessor BusBridgeBridge SRAMSRAMEthernetEthernet……DMADMADMADMALayoutAlgorithmBus ArchitectureImplementationPowerSourceTemperatureRefinementSecurityAddress SpaceDocumentation
  • Slide 17Hierarchical view of Energy ConservationSoftwareDefinitionsDynamic system monitoring and intelligent control of energysavings, work load profiling, [dvfs], profiling and partitioningArchitecturalDefinitionsHeterogeneous processing resource optimization: MCU, DSP,accelerators, functional processing units, memory usageoptimizationDesignDefinitionsHardware support for voltage islands, power gating, low-power idle modes, SRPG, AWB, DVFS, DPTC, clock gatingPROCESS nodeDefinitionsTransistor design, Vt Optimization, memory bitcell design.Special circuits, libraries, custom and analog blocks, SOIPower Trees/Voltage islands, Connectivity of components & consistentplatform power modes, intelligent bus coding, dependencydiscovery/optimizationPlatformDefinitionsThanks to Milind Padhye, Freescale Semiconductor, Austin Wireless Design Center
  • Slide 18Low Power Design NeedsSupport Low Power Design Techniques thru the entire designflow using a single file format.Design Representation– Accurately define and capture the low power design intent, modes andconstraints.Design Implementation– Floorplan and power grids.– Common constraints for all tools (Synthesis, APR, timing, DFT)– Design analysis tools with single power constraints.– Accurate power estimation and measurementsDesign Verification– Voltage oriented simulators– Various static power technique modeling and simulations.– Silicon validation and correlation.
  • Page 5The verification flows need to enable:• a voltage aware simulation method for logic problems due tovoltage island partitioning• a method for full design multi-voltage domain analysis andreporting• a vector-less rule driven analysis of architecture, RTL, and gatecorrectness• a method for equivalence checking (i.e. across voltage states )• a method that captures Island ordering• a method that incorporates early detection of micro-architecturesequence errorsFlow and Methodology Requirements
  • Si2-Accelera Low Power Workshop, CTO/SoCDT, Herve Menager, October 5th, 20063Low power implementation : What’s new ?Becoming mainstream:– For 65nm and below , Low power is crucial for low/high performance.So far:– For dynamic power• Reducing power dissipation source when not needed.• Minimize switching capacitances.– For static power• Use of multiple Vt(s) synthesis / optimizationMore recently:– Reducing supply reduces power, but also makes circuit slower. To meet bothchip performance requirements and power goals, use voltage islands andvoltage and frequency scaling.– Leakage can also be addressed by suppressing current when not needed.Island of voltages increases the difficulty on implementationtechniques.Intrusive on functionalityImpact across design tasks ( Design-In and Implementation )
  • Si2-Accelera Low Power Workshop, CTO/SoCDT, Herve Menager, October 5th, 20064Design implementation challengesNew cells and their use model– Level Shifters– Retention logic– Isolation logic– Micro SwitchesImpacts at all levels of the design flow– Interface logic design, partitioning– Verification of power modes– Checks on interfaces between Power domains– Placement of IP in context voltage islands– Floorplanning with switches, Irdrop across switches, transientbehavior.– DFT– Verification (STA, LVS, analysis)Conceptual shift : Power nets become functional signals
  • Si2-Accelera Low Power Workshop, CTO/SoCDT, Herve Menager, October 5th, 20066Methodology and design flow impacted
  • Si2-Accelera Low Power Workshop, CTO/SoCDT, Herve Menager, October 5th, 200610Short Term need ( 2) – Fill hole in VerificationLow leakage design techniques have created a realparadigm shift.Power and ground nets are now becoming functional nets.They are not all explicitly in RTL or netlist levels.Proper connection of any other functional nets is verified byfunctional simulation….against the RTL or netlist.Being able to verify the power down modes , retention,recovery at power-on, etc in the context of RTL simulation isbecoming mandatory.Verification tools should be power modes aware.
  • 6For IP, context is keyMemoryProcessorSoC“Always-on” depends oncontextBuffer within CPUSoC buffer routed acrossCPUCharacterization range isimportantCells, memory could bedifferentComplex featuresMultiple VDD, VSS pinsMultiple operatingvoltagesVoltage dependentbehaviorClosed-loop behavior(tunable voltage)Don’t want formats limiting IP features
  • 2Canonical design to argue over…….Start with a realistic example to exercise interfaces and controlPower and Ground are signals – but not as we know them……..Power Gating, Retention, (Dynamic) Voltage Scaling, Level shifters, Memory…Isolation clamps across boundaries, a number of supply voltagese.g. a SOC with always powered logic plus:VSOCRAMwith CoreRetention(& additionalpower rail?)VRAMPGsub-systemRETAINSRPGsubsystemRETAINCPUDVFS(& LVretention?)VCPU
  • 14Addressing power management challengesOperational and Standby (leakage)Active power + leakagePower gating/voltage scalingOn-chip – fast but with care to avoid dI/dt problemsOff-chip – may add latencies as long as 100’s of microsecondsNeed to be able to quantifyReal-time cost (e.g. interrupt latency) in “wake-up” timesEnergy cost functions getting into/returning from power saving states
  • 4 © NOKIA UPF Workshop / Oct 2006 /NaulaCurrent state …• Debugging capabilities are very poor• Capacity issues• Complexity issues• Reporting weak and misleading• Functional correctness difficult to verify• Tools are mostly in Gatelevel, should be in RTL• Important is to have accuracy for RTL or otherwise it is not useful• All tools using different description for PM• PM configurations currently having thousands of statements in SoC level• No automation; It is designers responsibility to verify that all definitions aredone correctly• Because updates for these definitions are done quite seldom, it is difficult tokeep in mind complex configurations• There is no automation for PM definitions verification• Design hierarchy presentation varies in configuration files between tools, alsobetween RTL and gate in same tool. Syntax is effected by scripting languageslike perl and tcl
  • © 2006 Virage Logic Corporation – COMPANY CONFIDENTIALSlide 7Traditional Design FlowTraditional Design FlowHW/SW Co-DesignArchitectureDesignRTL DesignPlacement &OptimizationFloorplanningSynthesisClockSynthesisOptimizationRouting &OptimizationSign-off:DRC/LVSTimingVerificationLogicVerification
  • © 2006 Virage Logic Corporation – COMPANY CONFIDENTIALSlide 9Techniques Relevant To IPTechniques Relevant To IPRight size libraries– Smaller transistors lead to smaller parasitics– Performance trade-offMulti-Vt libraries– Right Vt for the right paths at the right performance– Effectively used to control leakage– Increases the number of libraries needed to implement the designVoltage Islands– Requires updates to deal with multiple power supplies and associated conditions– Requires special level shifting components to implementPower Gating/On-Chip Regulation– Requires special power gating cells/regulation cells– Need to deal with “derived” power nets– Need to deal with POR cycleSubstrate Bias– Requires dealing with multiple power supplies and possibly “negative” power supplies– Requires special level shifting components to implement
  • © 2006 Virage Logic Corporation – COMPANY CONFIDENTIALSlide 10So What Changes? … Everything …So What Changes? … Everything …Low Power CoreVoltage IslandSupportVoltage Island&State RetentionSupportOn ChipRegulation SupportVoltage Island &Back Bias SupportVDDVSSVDD1VSSVDD2VDDVSS1VSSVSSVDD
  • © 2006 Virage Logic Corporation – COMPANY CONFIDENTIALSlide 12So What Changes? … Everything …So What Changes? … Everything …HW/SW Co-DesignArchitectureDesignRTL DesignPlacement &OptimizationFloorplanningSynthesisClockSynthesisOptimizationRouting &OptimizationSign-off:DRC/LVSTimingVerificationLogicVerificationPowerSign-off Spec
  • – 4 –Innovation Through Collaboration – 4 –Innovation Through Collaboration – Low Power CoalitionLibrariesIPWhat Was the Problem?LogicInformation(Verilog)SynthesisTestSVPFormalAnalysisSimulationParserParserParserLogic is “Connected”P+RParserParserParserCan be AutomatedHardwareParserEquivalenceCheckingParserManagementParserPowerInformation(CPF)Power is Not “Connected”Very Difficult to AutomatePowerInformation(no consistency)LibrariesIPSynthesisTestSVPFormalAnalysisSimulationParserParserParserP+RParserParserParserHardwareParserEquivalenceCheckingParserManagementParser
  • – 8 –Innovation Through Collaboration – 8 –Innovation Through Collaboration – Low Power Coalition● Dec 4, 2006Cadence contributed CPF v1.0 to Si2● January 12, 2007LPC members unanimously voted andapproved CPF v1.0 as Si2 Specification forlow power standard● January 17, 2007Cadence contributed CPF v1.0 parser sourcecode to Si2● March 5, 2007CPF 1.0 available to everyone at no cost as aSi2 standardSi2 CPF Standardization
  • – 10 –Innovation Through Collaboration – 10 –Innovation Through Collaboration – Low Power CoalitionCommon Power FileASCII file to capture● Design intent and constraintsPower domainLogical: instances as domain membersPhysical: power/ground nets and connectivityAnalysis view: timing library sets for power domainsPower LogicLevel Shifter LogicIsolation LogicState-Retention logicSwitch Logic & Control SignalsPower modeMode definitionsMode transition definitions● Technology informationLevel Shifter Cells, Isolation Cells, State-Retention Cells, Switch Cells, Always On Cells
  • – 11 –Innovation Through Collaboration – 11 –Innovation Through Collaboration – Low Power CoalitionCPF Language● CPF is TCL-based.● CPF Language = TCL commands + CPF objects + Design objectsPower domainAnalysis viewDelay cornerLibrary setOperating condition● Design objects: objects that already exist in the RTL/gate netlistModule, Instance, Net, Pin, Port● Commands – 42 commandsset_* commands [version, scope, and general commands]define_*_cell commands [library cell description]create_*_rule commands [design intent]update_*_rules commands [implementation directives]
  • – 12 –Innovation Through Collaboration – 12 –Innovation Through Collaboration – Low Power CoalitionMinimal Command Set For Different Design Stagescreate_power_domaincreate_nominal_conditioncreate_power_modecreate_state_retention_rulecreate_isolation_rulecreate_level_shifter_ruledefine_library_setupdate_nominal_conditionupdate_power_modecreate_ground_netscreate_power_netsupdate_power_domaincreate_power_switch_rulecreate_analysis_viewcreate_operating_cornerSpecify power intentsverification and simulationdesign explorationearly power estimationMore implementation detailssynthesisformal verificationDFT, ATPG,gate level power estimationComplete physical implementationdetailssilicon virtual prototypingpower planningphysical synthesisstructural verificationsign-off power analysis
  • – 24 –Innovation Through Collaboration – 24 –Innovation Through Collaboration – Low Power CoalitionSpecify Power Mode Transitionscreate_mode_transition -name PM1toPM2 –from_mode PM1 –to_mode PM2 -start_condition { pcu_inst/ctrl[0] & pcu_inst/ctrl[1] }-clock_pin { pcu_inst/clk } –cycles 100create_mode_transition -name PM2toPM3 –from_mode PM2 –to_mode PM3 -start_condition { pcu_inst/ctrl[0] & !pcu_inst/ctrl[1] }-clock_pin { pcu_inst/clk } –cycles 1000create_mode_transition -name PM3toPM4 –from_mode PM2 –to_mode PM3 -start_condition { !pcu_inst/ctrl[0] & pcu_inst/ctrl[1] }-clock_pin { pcu_inst/clk } –cycles 1000create_mode_transition -name PM4toPM1 –from_mode PM2 –to_mode PM3 -start_condition { !pcu_inst/ctrl[0] & !pcu_inst/ctrl[1] }-clock_pin { pcu_inst/clk } –cycles 200PDcore PDau PDlu PDalu PDrfPM1 1.2v0.8vPM3 0.8v off off off 1.2PM4 0.8v 1.2v 1.2v 1.2v off1.2v 1.2v 1.2vPM21.2v1.2v 1.2v 1.2voffPM1PM2PM3PM4
  • – 27 –Innovation Through Collaboration – 27 –Innovation Through Collaboration – Low Power CoalitionLow Power Design Verification Using CPF● No need to specify power or ground nets at RTL stage● No need to specify implementation related constraints at this stage suchas library, timing constraints etc● Minimal set of CPF commands for front-end designers to useSimulation toolsto simulation power domain on and offto simulate power mode transitions for DVFSCoverage toolsto check power mode coverageto check power mode transition coverageAssertion toolsto generate power domain and mode aware assertionsVerification toolsto check for the correctness and completeness of CPF
  • – 33 –Innovation Through Collaboration – 33 –Innovation Through Collaboration – Low Power CoalitionLow Power Logic Implementation and Verification Using CPF● Still, no need to specify power or ground nets at this design stage● Minimal set of CPF commands for designers to useLogic synthesis toolsto synthesize isolation, level shifter and state retention logicto perform power domain aware logic synthesisto perform power mode aware (DVFS) synthesisTest synthesis toolsto perform power domain and power mode aware DFT synthesisto generate power domain aware test control logicFormal Verification toolsto check the correctness of low power structural implemented by synthesis toolsto perform low power equivalency checking (RTL+CPF vs Netlist)Simulation toolsto perform power aware gate level simulationto generate additional assertions for gate level simulationAnalysis toolsto perform power domain aware and power mode aware power analysis
  • – 45 –Innovation Through Collaboration – 45 –Innovation Through Collaboration – Low Power Coalition?CPF Enabled Low Power Design FlowDesign CreationbSynthesisConstraintGenerationDesign for TestSVPEquivalenceCheckingConstraintValidationSpecificationFunction, timing, powerRTLCodingRTL + CPFCodingIterateQuick architectural explorationRe-use pre-verified IPInstantiate singleRTL with differentpower profilesHand off to drive physicalimplementationPhysical ImplementationChip IntegrationPrototypingPhysical SynthesisRoutingDFTAnalysisSign-offATPGConstraintValidationEquivalencecheckingLVS/DRC/ExtGDSIIConstraints CPF NetlistGoldenspecificationeliminatesassumptions andmiscommunicationsAutomatic partitioning ofpower domainsAutomatic scheduling oftest modesSingle powerspecification used fromspecification to GDSIIVerificationCoverageTestbenchAutomationVerificationStructural &Funct. ChecksFormalAnalysisSimulationAcceleration& EmulationFunctionally verifyadvanced powerimplementationtechniquesIterate
  • Power Forward Initiative Continues Growth24 companies across the design chainwww.powerforward.org26
  • – 48 –Innovation Through Collaboration – 48 –Innovation Through Collaboration – Low Power Coalition48TSMC 8.0 Low Power Reference FlowCPFCPF CPF Quality CheckConformal Low PowerCPF Quality CheckConformal Low PowerCPF-Enabled Functional simulationIncisive Design Team SimulatorIncisive Design Team ManagerCPF-Enabled Functional simulationIncisive Design Team SimulatorIncisive Design Team ManagerCPF-Enabled Logic Synthesis & DFTEncounter RTL CompilerCPF-Enabled Logic Synthesis & DFTEncounter RTL CompilerCPF-Enabled LEC + Power ChecksConformal Low PowerCPF-Enabled LEC + Power ChecksConformal Low PowerCPF-Enabled LEC + Power ChecksConformal Low PowerCPF-Enabled LEC + Power ChecksConformal Low PowerCPF-Enabled Timing & SI signoffEncounter Timing SystemCPF-Enabled Timing & SI signoffEncounter Timing SystemCPF-Enabled Physical implementationSoC EncounterCPF-Enabled Physical implementationSoC EncounterCPF-Enabled Logic simulationIncisive Design Team SimulatorCPF-Enabled Logic simulationIncisive Design Team SimulatorCPF-Enabled ATPGEncounter TestCPF-Enabled ATPGEncounter TestCPF-Enabled IR drop & Power signoffVoltageStorm-DGCPF-Enabled IR drop & Power signoffVoltageStorm-DGCPF-Enabled Leakage & Thermal AnalysisEncounter Timing SystemCPF-Enabled Leakage & Thermal AnalysisEncounter Timing Systemwww.tsmc.com
  • ConfidentialARM1176-IEM iRM FeaturesAutomated RTL to GDS Multi Supply VoltageImplementation flowCPF based flowCPF file is used to describe the low power intent and todrive implementation and verification flowMulti Mode Multi Corner (MMMC) analysis andoptimizationEnsures design is optimized across complete voltage andfrequency rangeTri-lib based flowProvides accurate interpolation for DVFS and IR dropanalysisECSM extensions to .lib
  • ConfidentialCPF Flow AvailabilityVRAMVDDCORE VDDRAM VSSVRAMVCOREVSOCARM1176-IEM iRMavailable now from ARMShipped along withstandard ARM1176 RTLdeliverablesIncludes CPF, scripts,documentation and frontend libraries (130G)Port to ARM Advantage65GP in H108
  • – 49 –Innovation Through Collaboration – 49 –Innovation Through Collaboration – Low Power Coalition49ARC Proof Point Project Using CPF Based Low Power Solution● Simulation with CPF identifiesproblems that you will nototherwise identify● CPF aids communication of powerintent across team boundaries,ensuring accurate implementationat all flow stages● Significant power savings resultsusing these techniquesAlways OnSCQSCQSCQSCQ SCM SDMSIMDSCM SDMI$ D$ SCQARC700I$ D$Clock Gating DomainsPower DomainsFunctional BlocksARC700 with SIMD Co-Processor• For high bit-rate data streams, boththe ARC and the SIMD run flat out• For lower bit-rate data stream, thesubsystem can be run at a lowerfrequency• For generic processing, the SIMDcan be inactivePower Forwardlow-power implementation &verification project results
  • Copyright© 2007. ARC International. All rights reserved.• ARC Energy PRO: new active power managementtechnology– Reduces power by as much as four fold– End-to-end fully verified power management solution –reduces TTM– Ideal for battery-operated portable applications• Integrated with Cadence Low-Power Solution andCPF to ensure accurate implementation at all flowstages• Energy PRO technology will be included in futureARC processor cores and multimedia subsystems
  • 51©2008SequenceDesign,Inc.CPF Out Current Status and Next StepsReleased to customers on Feb 11th, 2008An official part of the PowerTheater 2008.1 releaseCPF Out marked as beta in the releaseTested the flow using RC on numerous small tests and theNano CPU example from CadenceNext StepsGet feedback from key customers over the next monthVerify interpretation of create_global_connection,create_power_nets and create_power_switch commandsDo a CPF-In for power verification flowLeadership in Design for Power (DFP)
  • – 51 –Innovation Through Collaboration – 51 –Innovation Through Collaboration – Low Power Coalition51Power DomainPowerModePD0 PD1 PD2 PD3 PD4 PD5PM1 1.2V 1.2V 1.2V 0.74V 0.74V 0.74VPM2 1.2V PSO 1.2V 0.74V 0.74V 0.74VPM3 1.2V 1.2V PSO 0.74V 0.74V 0.74VPM4 1.2V 1.2V 1.2V PSO 0.74V 0.74VPM5 1.2V PSO PSO PSO 0.74V PSODriverPD4:0.74VPD0: 1.2V(Default,Always On)PD5:0.74VPD3:0.74VPD2:1.2VPD1:1.2VPSOcntlPSGcntlISOcntlValidated CPF and CPF-based flowfor major low power methodologiesin NEC Electronics386 checkpoints evaluated successfullyCPF describe-abilityMulti-Supply-Voltage (MSV)Power Shut Off (PSO)State Retention Logic (SRL)Variable Voltage Library (VVL)Clock Tree Gating (CTG)CPF based flow will be in use from Q3/2007NEC Proof Point Project Using CPF Based Low Power SolutionNEC ElectronicsNEC ElectronicsCorporationCorporation65nm6 Power Domains5 Power Modes2 Supply Voltage
  • – 50 –Innovation Through Collaboration – 50 –Innovation Through Collaboration – Low Power Coalition50Fujitsu Proof Point Project Using CPF Based Low Power SolutionCPU1 CPU2peripheralsPower Switch90nm940K instances11 Power Domains19 Power ModesPowerDomains● Verified with test designPSO functional verification with simulationLow power structural and physical check(Shifters/Isolators/Power switches)Domain aware place and route● ConclusionFunctional verification is necessary forcomplex PSO design for design bugsStructural check with CPF could verify LPdesignFujitsu will support CPF-based ASIC flow fortheir customers Silicon Proven September ‘07Silicon Proven September ‘07DVFS
  • – 52 –Innovation Through Collaboration – 52 –Innovation Through Collaboration – Low Power Coalition52Power Forward low-powerplatform SoC results● CPF-based functionalverification (using simulation)catches system level powerissues early in the flow● Use of CPF ensured whatimplementation built was whatwas verified• SoC consists of 11 islands• 3 major power consumers -RISCCPU, VLIW DSP & L2 SystemCache are controlled using DVFS• High bandwidth expansion portsenable extension, with graphicsor cellular modem subsystemsNXP Proof Point Project Using CPF Based Low Power Solution
  • Low-Power MethodologyA Practical Case Study in Low-Power Methodology• Special thanks to NXP Semiconductors
  • Si2 – Innovation Through CollaborationLow-Power Methodology• New! Educational eBook resource for industry… no-cost download (168pp.)• Contents include:– LP Techniques - Design / Verification / Implementation w/ CPF– Real end-user chip design experiencescourtesy, PowerForward.org
  • Additional Chapters in the pipeline• Low power test - Cadence• TSMC –Reference Flow 8.0, 9.0, Low Power Physical IP• ARM (3) – 1176 RM, Cortex A8, historical LP collaboration inSDC, How to use ARM LP IP• UMC – Ulterior PPP (with ARM)• Sequence -- Architectural power exploration• Faraday – Low power service success• GUC - success story• AMD – PPP
  • Raising The Low-Power Debate
  • What Is The Low-Power Coalition?● Flow-based solutions Standards to promote integration of open technologies into cohesive flows CPF was contributed to LPC 4Q06, approved as Si2 standard in March 2007 CPF is fully open to the entire industry at no cost – anyone can influence direction Analyze / develop semantic consistency across data exchanges● User-centric and comprehensive Focused on user needs for faster adoption into production chip design flows Owns the industrys low-power roadmap of requirements Comprehensive: enabling software, training & educational materials, articles,books, conferences, press coverage, etc.
  • LPC Member Companies● Advanced Micro Devices*● ARM● Atrenta● Azuro● Cadence Design Systems● Calypto Design Systems● Chipvision Design Systems AG● Entasys Design● Freescale Semiconductor● IBM Corporation● Intel Corporation● LSI● NXP Semiconductors● Sequence Design● Virage Logic• 6 End-Users• 7 EDA Companies• 2 IP Providers(*) = LPC Chair
  • LPC Structure, Working Groups● Full LPC membership (AMD, Chair) Business/policy & standards approvals● Technical Steering Group (TSG): charters working groups,owns the low-power technology roadmap Includes 3 Chief Architects (Cadence, IBM, LSI)● Active and completed working groups: Flow WG – align on low-power reference design flow and designtechniques to drive clarity for enhancements Data Model and API WG – map clear semantics and datarelationships in CPF, add API interface support to CPF Format WG – define priorities and detailed requirements (RFT);define the next revision of CPF (v1.1) > 100 pp. of (backward-compatible) enhancements Format Comparison WG – report on technical comparison of CPFand UPF (Done, results widely shared)
  • LPC StructureFull LPC MembershipTechnical Steering Group3 Chief ArchitectsFlow WG FormatWGFormatComparison WGData Model& API WG
  • LPC Working Groups● Flow Working Group Definition of complete reference flow from ESL to GDSII Target completion date: 2Q08 Analysis of power stimuli for SoC power estimation Target completion date: 2Q08 Compilation of all known low power design techniques Target completion date: 2Q08
  • LPC Working Groups● Data Model Working Group LP Glossary v1.0 completed and posted for download Developing UML-based models to support enhanced power-aware design Will be based on OpenAccess data model Target date: 1H08
  • LPC Working Groups● Format Working Group Develop format extensions requirements document Target date: 1Q08 (DONE) Open RFT, receive contributions DONE CPF 1.1 standardization target: Aug 08 CPF roadmap alignment across both Flow and Data Model WGs
  • Recent LPC / CPF Publicity
  • Recent LPC / CPF Publicity
  • – 1 –Innovation Through Collaboration – 1 –Innovation Through Collaboration – Low Power CoalitionFormat Enhancement RequirementsImmediate - Requirements for Version 1.1 (extension to 1.0)Hierarchical flow Support.Memory modeling styles and support.Gatelevel verification Flow CPF support.Power estimation SupportClocking and related updates are required to drive power optimization.Medium Term – Requirement for CPF 1.2Pre-Si and post_Si power modeling and budgeting.Test power definitions not represented in CPF.Investigate Load_foreign.IO modeling and representation.Long term - Next GenerationCPF needs to drive debug related to power.CPF based system level definition.1.11.22.0
  • – 3 –Innovation Through Collaboration – 3 –Innovation Through Collaboration – Low Power CoalitionHierarchical Flow – Bottom UpChip Level power StructureCPFMemoriesHard IP with(Behavioural)Hard IP withRTL or GatesSoft IPRTLMultiple CPF Multiple CPF Multiple CPF Multiple CPF
  • – 64 –Innovation Through Collaboration – 64 –Innovation Through Collaboration – Low Power Coalition: Si2 ConfidentialSoft IP Reuse● IP is defined with multiple power structures and functionalities● At chip level, part of the power structures or functionality will be used● Need toMerge power domainsReconfigure power domainsReconfigure power rulesMerge rules and resolve precedenceIntegrate power modesNeed to be capable of composing modes description from combination of powersupplies and other modes.Allow block level configurations to refine top level power mode..Should be capable of specifying the performance parameter.
  • – 62 –Innovation Through Collaboration – 62 –Innovation Through Collaboration – Low Power Coalition: Si2 ConfidentialHierarchical Flow Requirements● PerspectiveEnable IP reuseReuse Design Hierarchy and better organization.Enable Low power Custom IP Integration and verification.Support Bottom-up and Top Down Flow● EnsuresConsistent RepresentationConsistent Integration styleConsistent VerificationConsistent Rules, semantics, precedence policy.
  • – 67 –Innovation Through Collaboration – 67 –Innovation Through Collaboration – Low Power Coalition: Si2 ConfidentialCustom IP Support Requirements● A Hard IP can be connected to multiple power ports and significant logicmay belong to multiple domains.Assigning the entire component to single domain may create incorrect representation.● Support integration of custom IP.To most of the flow it is considered a blackbox● Support Verification of Custom IP using CPFIP may have non-trivial power structuresIP has a behavioral model with no relation to hierarchy of power domains.● Need toMaintain IP level power control sequence.Define the power structure using only boundary ports and registers.Provide hooks to use the behavioral modelIntegrate power connections at chip level
  • – 74 –Innovation Through Collaboration – 74 –Innovation Through Collaboration – Low Power Coalition: Si2 ConfidentialPower Network Component Models● Power Network ComponentSwitchesRegulatorsConverters● Provide an approach to model the power network components.Component inputComponent outputComponent EfficiencyComponent Electrical Characteristics● Need recommendations from flow group and other working groups.
  • – 77 –Innovation Through Collaboration – 77 –Innovation Through Collaboration – Low Power Coalition: Si2 ConfidentialProposed CPF Roadmap2.01.21.1Start H1/09Start Q1/08 Start H2/08
  • Si2 – Innovation Through CollaborationSummary of Low-Power Collateral1. CPF v1.0 Standard2. CPF v1.0 Parser software3. CPF Pocket Reference Guide4. CPF On-line Tutorial - both in English and Mandarin (2.5 hrs)5. Low-Power Glossary of Terms6. CPF v1.1 Requirements Document (and RFT)7. Low-Power Industry Roadmap8. “A Practical Guide to Low Power Design” (168pp. ebook)For downloads, go to:www.si2.org/?page=726
  • Silicon Integration Initiative 1DFMCNew...CPFRelationalAnalyzer
  • Silicon Integration Initiative 2Why• Structured, Low Power design methodology is currentlythe exclusive and elite domain of a few “Power Users”The CPF Relational Analyzeris for everybody else• Simple, Interactive Training Tool• Realizes in open source softwarethe key concepts of the CPF Format• Accelerates the CPF learning curve LP Design Using CPF- Who me?
  • Silicon Integration Initiative 4Plenty of Room for Confusion (and Errors)Multiple SourceFilesMultiple GroupsTop LevelPower TargetsPowerDomainsMultiple Levelsof hierarchySame DomainConstraintsLevel ShiftRulesMultiple Libraries w/ Multiple VariantsPower UnitmWPower UnituWIncrementalChanges
  • Silicon Integration Initiative 6set_design top# Set up logic structure for all power domainsset_time_unit usset_power_unit uWcreate_power_domain -name PDcore -defaultcreate_power_domain -name PDalu -instances {inst_A inst_B} -shutoff_condition {!pm_inst.pse_enable[0]}create_power_domain -name PDrf -instances inst_C -shutoff_condition {!pm_inst.pse_enable[1]}create_power_domain -name PD4 -instances inst_D -shutoff_condition {!pm_inst.pse_enable[2]}# Define static behavior of all power domains and specify timing constraintscreate_nominal_condition -name high -voltage 1.2create_nominal_condition -name medium -voltage 1.1create_nominal_condition -name low -voltage 1.0create_power_mode -name PMhot -domain_conditions {PDcore@high PDalu@medium PDrf@high PD4@low} -defaultcreate_power_mode -name PMcool -domain_conditions {PDcore@high PDrf@high PD4@low}create_power_mode -name PMsleep -domain_conditions {PDcore@high PD4@low}create_power_mode -name PMhibernate -domain_conditions {PDcore@low}# Set up required isolation and state retention rules for all domainscreate_state_retention_rule -name sr1 -domain PDalu -restore_edge {!pm_inst.pge_enable[0]}create_state_retention_rule -name sr2 -domain PDrf -restore_edge {!pm_inst.pge_enable[1]}create_state_retention_rule -name sr3 -domain PD4 -restore_edge {!pm_inst.pge_enable[2]}create_isolation_rule -name ir1 -from PDalu -isolation_condition {pm_inst.ice_enable[0]} -isolation_output highcreate_isolation_rule -name ir2 -from PDrf -isolation_condition {pm_inst.ice_enable[1]} -isolation_output highcreate_isolation_rule -name ir3 -from PD4 -isolation_condition {pm_inst.ice_enable[2]} -isolation_output lowcreate_level_shifter_rule -name lsr1 -to {PDcore PDrf}end_designCPF Format ConceptsDefinePDsDefineNominalsPMsBind PD & NCRulesandmorerulesWhat if this command was in a different file andthe IP in PDcore had not been characterized atthe “low” nominal condition?
  • Silicon Integration Initiative 7CPF Relational Analyzer• Each object in the CPF hierarchy is tracked separately via metadata• Architecture handles hierarchy merging, module cloning & port mapping• Broad analysis – Analyze all objects and all O2O relationships• Deep analysis – Every attribute, every object with every updateInteractive and Incremental:Designed for “Hands-on” learners with English as a Second LanguageExposes the final state of the design intent compiled from many sourcesSearch and Report capabilities:All searches can use standard wildcards of *, ?, [a-z], [0-9]Any combination of CPF Objects, Property Names and Property Values
  • Silicon Integration Initiative 5CPF Information Model
  • Si2 – Innovation Through Collaboration
  • Si2 - Innovation Through CollaborationThank You!