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Dean Drako, President & CEOShiv Sikand, VP EngineeringIC ManageIP Reuse Impact on Design VerificationManagement across the EnterpriseTo Win Hardware Design Race: Master IP ReuseDVClub LunchFebruary 14, 2013
Hardware Design is Always a Race• Intense Time toMarket Competition• Continued Cost,power, performancepressures
Continuous Design: Samsung Galaxy SJune 2010 SFeb 2011 SLMay 2011 S IIAug 2011 S PlusApr 2012 S AdvanceAug 2012 S DuosNov 2012 S III MiniApril 2013?? S IVMay 2012 S III30 month timeline6-10 2-11 5-11 8-11 4-12 5-12 8-12 11-12
To Win Race: Must Master IP ReuseManage/Reuse IP across:- Instances- Versions- Subsystems- Designs, DerivativesDesigners- Find IP they need- Plug it in- It works !
Survey results: Verification & IP Reuse CriticalSource: 2011 & 2012 blind, independent surveys, with 465 & 524 respondents, respectively~50% of respondents were engineering management• EDA Verification tools - 63%• IP Reuse Tools - 50%• EDA Design tools - 42%,• Embedded software tools - 26%SoC design topinvestment areas• Bug tracing & notification acrossdesign teams & versions - 50%#1 IP Reuse featurerequestedDesign datamanagementdrivers• Easier to trace & fix bugs -53%• Easier team collaboration - 49%• Better IP reuse management -43%
Verification Reuse is Critical part of IP Reuse• Verification reuse is often neglected• Finding & fixing moving parts on ‘speeding cars’• Need technology & process for IP Reuse Dependency Management
Reduce Verification Effort throughEffective IP Reuse Dependency ManagementSource: 2013 independent survey, 372 respondents40% of debuggingtime is identifying &managing bugdependencies!DevelopingTestbenches26%Writing/RunningTests26%IdentifyingBugs25%Other6%Managing BugDependencies17%
Example: Managing Bugs across Projects, ReleasesAn IP is shared across 3 projects, each node represents a release, andthe edges show the direction of sharing.If an identical defect is found in both releases I and M, what is theminimum number of releases at risk due to the defect?
Example: Managing Bugs across Projects, ReleasesAnswer: 12 (B,D,E,F,H,I,K,J,L,M,N,O)B is common ancestor of releases I and M.Thus B plus all of its 11 descendants are at risk.
Dean Drako, President & CEOShiv Sikand, VP EngineeringIC ManageIP Reuse Impact on Design VerificationManagement across the EnterpriseIP Reuse Dependency ManagementChallenges, Vision, and Best PracticesDVClub LunchFebruary 14, 2013
IP Reuse Example: IP1Constituents Impacted by DependenciesManagersProject leadsChip DesignersIP OwnersVerification Engineers
Top IP Reuse Dependency Management Challenges1. Managing multiple data sources2. Testbenches for IP modules not adequately shared/reused3. Unknown IP usage vs. product releases & difficultynotifying IP user re known bugs/fixes4. IP Development or Verification steps not enforced/tracked5. 3rd party IP provider & internal teams data exchange6. Lack of processes and/or designer participation7. Key IP properties/status items not tied to IP8. Bug roll-up reportingSource: 2013 independent survey, 372 respondents
IP Reuse VerificationNeed Effective DV Dependency ManagementIP Verification ChecklistIdentify checklist itemsContinuously gauge progressBug DiscoveryView design & bug historyReturn to stateDependency TracingIP instancesDesignsIP & Design VersionsIP Bug NotificationIP ownersIP users - Chip DesignerManagementBug FixesSelective Auto-PropagationLink to IP & Design HistoryRoll-up ReportingManagement MetricsVerification leadChip lead
IP Verification Checklist ItemsIP Checklist:Design History (Engineers + changesConstraintsFoundry, processVersionBug status/dependenciesTestbenchVerification Checklist:RTL passes regressionAll protocols checked against formal model/protocol checkerFunctional/ assertion/ test coverageClock domain crossing verifiedCondition code coverageDFT /Scan /BIST simulation pass at specified cornersExpression code coverageGate-level passes regressionLine code coverageLogic equivalence checking passes post-scan insertionLogic equivalence checking passes pre-scanPin list matches specificationState & transition code coverageAnalog Functionality RegressionIP1
DV Best Practices forIP Reuse Dependency Management1. Partition new design work intofunctional modules, keeping verificationin mind.2. Organize each IP block according todata type.3. Put all new IP – internal andexternal - into the IP repository.4. Link the IP repository to a bugtracking system from project start.Enforce formal discipline.5. Encapsulate Design & Verificationdata with IP for reuse.
DV Best Practices forIP Reuse Dependency Management6. While creating new IP derivatives,use traceable branching instead ofcopying the IP.7. Use private branching to manage IPblock derivatives within same design.8. Set up and utilize a checklist-drivenflow during IP development.9. Establish practice of continuousdesign integration.10. Set up automatic notifications andselective propagations for fixes.
Dean Drako, President & CEOShiv Sikand, VP EngineeringIC ManageIP Reuse Impact on Design VerificationManagement across the EnterpriseIP Reuse Dependency ManagementOrganizational ImpactDVClub LunchFebruary 14, 2013
DV Dependency Management Crucial toKeeping Projects on Schedule• Chip development starts on schedule• Must quickly and accurately select & verify right IPversions for right design• Must understand impact of new bugs on ALL designs– taped out or in progress• Need timely notifications design changes, bugs, fixes
IP Reuse Dependency Management Goal:Higher Return on Assets
IP Reuse Dependency ManagementProcesses & Systems ROI RESULTS• 31% more efficient use oflimited engineering resources• 30% faster TTMSource: 2013 independent survey, 372 respondentsEngineeringResourcesRequired69%EngineeringResourceReduction31%30%Project TimeReduction