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Formal Verification Techniques
Formal Verification Techniques
Formal Verification Techniques
Formal Verification Techniques
Formal Verification Techniques
Formal Verification Techniques
Formal Verification Techniques
Formal Verification Techniques
Formal Verification Techniques
Formal Verification Techniques
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Formal Verification Techniques

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  • 1. TMRekha BangaloreFormal VerificationTechniquesDV Club March 2007
  • 2. TM Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of FreescaleSemiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.Slide 1What is Formal Verification?• Formal verification is the process of proving or disprovingproperties using formal methods (i.e., mathematically precise,algorithmic methods). A formal proof of a property provides aguarantee that no simulation of the system considered willviolate the property. This eliminates the need for writingadditional test cases to check the property.
  • 3. TM Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of FreescaleSemiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.Slide 2What are Formal Verification properties?• Properties for formal verification are represented in amathematically precise, machine-readable language for whichthere are formal semantics.• Assertions are the preferred language for writing suchproperties.• Adding assertions will help verify the design feature sets andalso obtain coverage for assessing IP quality.
  • 4. TM Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of FreescaleSemiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.Slide 3Formal Verification in Verification space• Formal Verification can be applied at block level to eliminatefunctional bugs early in the design cycle and match blockspecifications.• It is difficult to assess the need for additional patterns forexhaustive verification if coverage goals are not integrated aspart of formal verification.
  • 5. TM Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of FreescaleSemiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.Slide 4Formal Verification in Verification space• Formal Verification Tools can be applied at SoC level forStatic design rule checksCheck for tied ports at SoC levelBus contentionVerifying inter modular constraints ( Case study)> This is not an easy task as all assertions are built in for stand aloneverification and to move to the next level requires:– Understanding of module interactions in the application.– Understanding of integration of the modules at SoC level– Porting of assertions at SoC level can slow down the speed of the toolsto process the design and prove the properties.– Sequential depth will become a harder issue to resolve.
  • 6. TM Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of FreescaleSemiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.Slide 5• Checks in Formal Verification tools includeSynthesis pragmasCross clock domainsX-state propagations in the designTri state and bus contentionDead code in the designChecks for Case and branch enable statementsChecks for Structural modelingChecks for clock related errors• Checks for user defined properties in Formal Verification tools includeSpecifications in form of assertionsSpecifications in form of constraintsFeatures of Formal Verification
  • 7. TM Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of FreescaleSemiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.Slide 6• Reduce vector set for either dynamic or random simulations. Formalverification is vectorless and checks assumptions made by designers• Smaller vector set for corner cases are easier to detect at block level andbugs can be fixed prior to SoC integration• Automatic generation of testbench• Bugs found at Post layout due to incorrect timing constraints are detectedearly. Example: Multi cycle paths and False Paths• Validates constraints from designersSynthesis constraints are input to Formal VerificationHelps in any invalid timing constraints for IP by the designersHelps in reducing post layout debug time when IP is integrated in SoCAdvantages of Formal Verification
  • 8. TM Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of FreescaleSemiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.Slide 7Challenges of current tools:Capacity issuesCustom cells integrated at block level.Cannot generate functional coverage metrics from assertionsSupporting all features of LRMAutomatic generation of assertions/constraints based on scenariosFormal compatible VIP for standard ProtocolsCannot generate Code coverage reports based on the proofChallenges of Formal Verification tools
  • 9. TM Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of FreescaleSemiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.Slide 8Challenges of Formal Verification methodology• Challenges of using Formal techniques on large designsApply constraints for intermodular signals ( Not tried it yet.) and see ifviolations show up.Check for tied ports in the design and correlate with toggle coveragetools.Complex SoC vector initialization is required.Analog and Memory behavioral model checks are not fully available inEDA tools currentlyCannot use for multiple functional modes. Separate initializationsequences are required.
  • 10. TM Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of FreescaleSemiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005.Slide 9Conclusion• Formal Verification is a must for quality verification• Efficient strategy is required to plan the flow for both block and fullchip.• Tools must be updated to improve the engines internally to handlelarger designs and have the capability of changing the user definedrules dynamically.

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