14 Nov 2007 TI Proprietary InformationDesign Verification to ApplicationValidation of a Multiprocessor SoCIsh Kumar Dham (...
14 Nov 2007 TI Proprietary InformationStructure• Understanding the Complexity– Design Goals– Additional Verification Team ...
14 Nov 2007 TI Proprietary InformationMedia Gateway• Convergence ofFixed Line &Mobile Services• Mobile BroadbandData – not...
14 Nov 2007 TI Proprietary InformationInnovation for Communications InfrastructurePerformanceIncreases ChannelDensity by 3...
14 Nov 2007 TI Proprietary InformationDesign Complexity• Large Design– 10-15 M Gate Complexity– Multiprocessor System – sy...
14 Nov 2007 TI Proprietary InformationVerification GoalsStart BasicOk to VerifyMajor ModesOkRTLFreezeTapeOutGoodChipSetupE...
14 Nov 2007 TI Proprietary InformationApplication Validation GoalsStart BasicOk to VerifyMajor ModesOkRTLFreezeTapeOutGood...
14 Nov 2007 TI Proprietary InformationEnvironmentsStart BasicOk to VerifyMajor ModesOkRTLFreezeTapeOutGoodChipSetupEnviron...
14 Nov 2007 TI Proprietary InformationManaging ComplexitySystemComplexPerformance,t0Power Mgmnt,Verify IntegrationRTL Simu...
14 Nov 2007 TI Proprietary InformationReuse• Same test-bench used for RTLsimulations, GATE level, accelerationplatforms an...
14 Nov 2007 TI Proprietary InformationMultiply & Not Add• Break up tests into components that could bepermuted– Same tests...
14 Nov 2007 TI Proprietary InformationSummary• Verification teams not just prove designs– they support H/W – S/W verificat...
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Design Verification to Application Validation of a Multiprocessor SoC

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Design Verification to Application Validation of a Multiprocessor SoC

  1. 1. 14 Nov 2007 TI Proprietary InformationDesign Verification to ApplicationValidation of a Multiprocessor SoCIsh Kumar Dham (dham@ti.com)DSP SystemsTexas Instruments
  2. 2. 14 Nov 2007 TI Proprietary InformationStructure• Understanding the Complexity– Design Goals– Additional Verification Team Goals– Application Validation Goals– Environments & Tools• Managing Complexity– Breaking the complexity– Staging it out– Reuse
  3. 3. 14 Nov 2007 TI Proprietary InformationMedia Gateway• Convergence ofFixed Line &Mobile Services• Mobile BroadbandData – not justVoice: email,Multimedia, StreamingMultimedia, Interactive• IP as the PervasiveNetworkTransportTechnologyIPNetworkIPNetworkPSTNPSTNMobileNetworkMobileNetworkMedia GatewayVoiceFAXVoice (VoIP)DataMultimedia (Video/Audio)Voice, DataMultimedia
  4. 4. 14 Nov 2007 TI Proprietary InformationInnovation for Communications InfrastructurePerformanceIncreases ChannelDensity by 3XOver 500 G.711ChannelsOver 200 G.729ChannelsC64x+ enablesAudio/VideoTranscodeEnabled by worldclass software:Telogy Voice SoftwareBundle, Voice & VideoCodecs, TelinnovationsLine Echo CancelationSoftware, PIQUASoftwarePower6 x 500 MHzC64x+ Cores allowperformance atlower voltageLarge Shared L2Memory and nextgenerationperipheralsreduce systempower dissipationSeparate powerdomains for highperformance/highpower peripheralsTNETV3020
  5. 5. 14 Nov 2007 TI Proprietary InformationDesign Complexity• Large Design– 10-15 M Gate Complexity– Multiprocessor System – symmetric multiprocessing• Local and Shared Memory• Complex High Speed Interfaces : DDR, SRIO,Gigabit Ethernet• IP reused from previous designs + new IPdeveloped concurrently – locally as well as byremote teams• Power Management : Power Domains as well asClock Gating– Dynamic as well as Static (some IPs always powered offor powered on)
  6. 6. 14 Nov 2007 TI Proprietary InformationVerification GoalsStart BasicOk to VerifyMajor ModesOkRTLFreezeTapeOutGoodChipSetupEnvironmentSoftware InfraIntegration FocusKey Module Functions All modes andSystem FeaturesGLS,Manufacturing TestsSilicon Testbench(FPGA)Releaseto ApplicationsTeamFinal Phy. DesignRunsToManufacturing
  7. 7. 14 Nov 2007 TI Proprietary InformationApplication Validation GoalsStart BasicOk to VerifyMajor ModesOkRTLFreezeTapeOutGoodChipApplication Requirements Library DevelopmentTestbench RequirementsCheck out on Design Env. Basic ApplicationScenariosCritical Application ScenariosAll Application ScenariosROM Code ValidationReal ApplicationsSilicon Testbench(FPGA)Power MeasurementTestsDesign Available on AccelerratedPlatformRunningApps
  8. 8. 14 Nov 2007 TI Proprietary InformationEnvironmentsStart BasicOk to VerifyMajor ModesOkRTLFreezeTapeOutGoodChipSetupEnvironmentSoftware InfraIntegration FocusKey Module Functions All modes andSystem FeaturesGLS,Manufacturing TestsSilicon Testbench(FPGA)Releaseto ApplicationsTeamFinal Phy. DesignRunsToManufacturingSimulation ToolsSim-AccelerationFPGA+ SiFormalSpecman
  9. 9. 14 Nov 2007 TI Proprietary InformationManaging ComplexitySystemComplexPerformance,t0Power Mgmnt,Verify IntegrationRTL SimulationAuto-Gen Basic TestReviewsNot all aspects easy to observeVerify Components SeparatelyFormal, Specman
  10. 10. 14 Nov 2007 TI Proprietary InformationReuse• Same test-bench used for RTLsimulations, GATE level, accelerationplatforms and final Silicon– As Simulation Model, Synthesized toAcceleration Environment and FPGA• Same tests can run in all environments– Not all are run. Actual runs are based offneeds.• Reuse test benches and tests acrossdesigns• Share some low level and data bases codewith software teams• Use test generators for basic tests
  11. 11. 14 Nov 2007 TI Proprietary InformationMultiply & Not Add• Break up tests into components that could bepermuted– Same tests can be run from various memory locationsand PLL configurations– With or without interrupts• Tests written for one CPU run on other CPUs• Multiple individual tests combined to run onmultiple CPUs• Simple, small tests written so that changingdefines could make them large and complex tests• Write tests like any software – build them inlayersX
  12. 12. 14 Nov 2007 TI Proprietary InformationSummary• Verification teams not just prove designs– they support H/W – S/W verificationtoo – Systems not just Chips• Complexity broken out• Application Validation and DesignVerification use a similar environment• Early Application Validation– High confidence on chip at Tape Out– Applications running a few days after Silicon
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