This document discusses physics of failure (PoF) reliability assurance software. It begins with an introduction to design for reliability (DfR) and the history and limitations of traditional DfR approaches. It then discusses how PoF is now important for modeling wearout failures. The document provides examples of modeling solder joint fatigue, vibration analysis, and shock environments. It also discusses validation of the software predictions against experimental data. In summary, the software allows modeling of reliability from multiple failure mechanisms to provide assurance that design goals are met.

1. Physics of Failure Electronics Reliability Assurance Software
Cheryl Tulkoff, Nate Blattau, & Randy Schueller
Senior Members of the Technical Staff
at DfR Solutions
IPC APEX EXPO 2010

2. Design for Reliability (DfR)
•DfR: A process for ensuring the reliability of a product or system during the design stage before physical prototype
•Reliability: The measure of a product‟s ability to
–…perform the specified function
–…at the customer (with their use environment)
–…over the desired lifetime

3. History
•DfR has been a concept promoted by electronics community since the early 1950‟s
•DARPA identified DfR as an “Area of Promise” to resolve issue with Defense Systems Reliability in 1958
Identification of Certain Current Defense Problems and Possible Means of Solution, INSTITUTE FOR DEFENSE ANALYSES, 1958

4. Why DfR?
Architectural Design for Reliability, R. Cranwell and R. Hunter, Sandia Labs, 1997

5. Limitations of Current DfR
•Too broad in focus (not electronics focused)
•Too much emphasis on techniques (e.g., FMEA and FTA) and not answers
–FMEA/FTA rarely identify DfR issues because of limited focus on the failure mechanism
•Overreliance on MTBF calculations and standardized product testing
•Incorporation of HALT and failure analysis (HALT is test, not DfR; failure analysis is too late)
–Frustration with „test-in reliability‟, even HALT, has been part of the recent focus on DfR

6. DfR and Physics of Failure (PoF)
•Due to some of the limitations of classic DfR, there has been an increasing interest in PoF (aka, Reliability Physics)
•PoF Definition: The use of science (physics, chemistry, etc.) to capture an understanding of failure mechanisms and evaluate useful life under actual operating conditions

7. Why PoF is Now Important
Failure Rate
Time
Electronics: 1960s, 1970s, 1980s
No wearout!
Electronics: Today and the Future
Wearout!

8. Solder Joint (SJ) Wearout
•Elimination of leaded devices
–Provides lower RC and higher package densities
–Reduces compliance
Cycles to failure -40 to 125C
QFP: >10,000
BGA: 3,000 to 8,000
QFN: 1,000 to 3,000
CSP / Flip Chip: <1,000

9. SJ Wearout (cont.)
• Design change: More silicon, less plastic
• Increases mismatch in coefficient of thermal
expansion (CTE)
BOARD LEVEL ASSEMBLY AND RELIABILITY
CONSIDERATIONS FOR QFN TYPE PACKAGES,
Ahmer Syed and WonJoon Kang, Amkor Technology.

10. Reliability Assurance -- Definition
•Reliability is the measure of a product‟s ability to
–…perform the specified function
–…at the customer (independent of environment)
–…over the desired lifetime
•Assurance is “freedom from doubt”
–Confidence in your product‟s capabilities
•Typical approaches to reliability assurance
–„Gut feel‟
–Empirical predictions (MIL-HDBK-217, TR-332)
–Industry specifications
–Test-in reliability
•Sherlock is a reliability assurance software based upon physics of failure algorithms

11. Motivation
•Ensuring sufficient product reliability is critical
–Markets lost and gained
–Reputations can persist for years or decades
–Hundreds of millions of dollars won and lost
•Designing in Reliability before prototype build & test
–Saves costs
–Reduces development time
•Opportunities for improvement, automotive example:
–Total warranty costs range from $75 to $700 per car
–Failure rates for E/E systems in vehicles range from 1 to 5% in first year of operation
•Hansen Report (April 2005)
–Difficult to introduce drive-by-wire, other system-critical components
•E/E issues will result in increase in “walk home” events

12. Other Costs of Failure
Type of Business Lost Revenue per Hour
Retail Brokerages $6,450,000
Credit Card Sales Authorization $2,600,000
Home Shopping Channels $113,750
Catalog Sales Centers $90,000
Airline Reservation Centers $89,500
Cellular Service Activations $41,000
Package Shipping Services $28,250
Online Network Connect Fees $22,250
ATM Service Fees $14,500
Supermarkets $10,000
Does not include liability and loss of market share

13. Reliability and Design
•The foundation of a reliable product is a robust design
–Provides margin
–Mitigates risk from defects
–Satisfies the customer

14. Currently Available DfR Tools
•FMEA – many limitations
•MIL-HNBK-217 MTTF Calculations – also many limitations (no solder joint considerations)
•FEA modeling – good but often expensive and limited to a few components.
•Sherlock – a new tool that models all the circuit cards assemblies and provides predicted life curves from many failure mechanisms.

15. Limitations of MTTF/MTBF
•MTBF/MTTF calculations tend to assume that failures are random in nature
–Provides no motivation for failure avoidance
•Easy to manipulate numbers
–Tweaks are made to reach desired MTBF
–E.g., quality factors for each component are modified
•Often misinterpreted
–50K hour MTBF does not mean no failures in 50K hours
•Better fit towards logistics and procurement, not failure avoidance

16. Sherlock Coverage
•This software modeling tool predicts failures from
–Solder joint wear-out from thermal cycling (SAC305 or SnPb)
–Conductive anodic filament formation
–Plated through hole fatigue
–217 MTBF calculations are also generated
•In addition the software uses FEA to determine
–Board deflection from mechanical shock
–Board deflection from vibration
–The natural frequencies for the board based on the mount points.

17. Process Overview
•There are several high levels steps involved in running the software (named Sherlock). They are:
–Create a Project
–Define Reliability Goals
–Define Environments
–Add Circuit Cards
•Import Files
•Generate Inputs
–Perform Analysis
–Interpret Results

18. Inputs
•Gerber or ODB files for PCB and Pick & Place (w/ BOM)
•Thermal cycle conditions (Miner‟s Rule is applied) – in the field or in test.
•Shock & Vibration conditions.
Layer Plot Examples

19. Identify Field Environment
•Approach 1: Use of industry/military specifications
–MIL-STD-810,
–MIL-HDBK-310,
–SAE J1211,
–IPC-SM-785,
–Telcordia GR3108,
–IEC 60721-3, etc.
•Advantages
–No additional cost!
–Sometimes very comprehensive
–Agreement throughout the industry
–Missing information? Consider standards from other industries
•Disadvantages
–Most more than 20 years old
–Always less or greater than actual (by how much, unknown)

20. Field Environment (cont.)
•Approach 2: Based on actual measurements of similar products in similar environments
–Determine average and realistic worst- case
–Identify all failure-inducing loads
–Include all environments
•Manufacturing
•Transportation
•Storage
•Field

21. Field Environment (example)
•For automotive electronics outside the engine compartment with minimal power dissipation, the diurnal (daily) temperature cycle provides the primary degradation-inducing load
•Absolute worst-case: Max. 58ºC, Min. -70ºC
•Realistic worst-case: Phoenix, AZ (USA)
–Add +10ºC due to direct exposure to the sun
Month Cycles/Year Ramp Dwell Max. Temp (oC) Min. Temp. (oC) Jan.+Feb.+Dec. 90 6 hrs 6 hrs 20 5 March+November 60 6 hrs 6 hrs 25 10 April+October 60 6 hrs 6 hrs 30 15 May+September 60 6 hrs 6 hrs 35 20 June+July+August 90 6 hrs 6 hrs 40 25

22. Thermal Environment Example

23. Solder Joint Fatigue
•Two most common solder types are available.
–Eutectic tin-lead (SnPb)
–Lead-free SAC 305 (Sn-3.0%Ag-0.5%Cu)
–Additional solders may be added in the future
–Specified at the board or component level

24. Validation Example
Leadless Ceramic
Chip Carrier
Novice user (intern)
Solder Material
Cycles to
Failure (calc)
Cycles to Failure
(exp)
Min
Temp
(˚C)
Min Dwell
Time (min)
Max
Temp (˚C)
Max Dwell
Time (min)
Thickness
(mm) Exy (GPA)
CTExy
(ppm/C) Name
Tin-Lead 415 346 25 1.67 125 1.67 1.6 22 18 LCCC-84 Basaran and Chandaroy
Tin-Lead 302 664 -55 10 125 30 2.34 29.103 15 LCCC-20 Osterman and Pecht
Lead-Free 198 480 -55 10 125 30 2.34 29.103 15 LCCC-20 Osterman and Pecht
Tin-Lead 2360 1600 -20 10 80 30 2.34 29.103 15 LCCC-20 Osterman and Pecht
Lead-Free 2580 2213 -20 10 80 30 2.34 29.103 14 LCCC-20 Osterman and Pecht
Tin-Lead 338 150 0 5 100 5 1.6 22 22 LCCC-44 Whitten
Lead-Free (SnAg) 297 280 0 5 100 5 1.6 22 22 LCCC-44 Whitten
Tin-Lead 45 75 -55 20 125 20 1.6 22 22 LCCC-44 Whitten
Lead-Free (SnAg) 30 110 -55 20 125 20 1.6 22 22 LCCC-44 Whitten
Author(s)
Solder Properties Thermal Profile Board Properties Package Properties
LCCC Sherlock Validation Graph
10
100
1000
10000
100000
10 100 1000 10000 100000
Predicted
Experimental

25. Validation
Example
QFN
Solder Material Cycles to Failure (calc) Cycles to Failure (exprm) Stress Strain Energy Name
Tin-Lead 496 631 2.28E+01 3.326 QFN-52 Tee, Ng, Yap, Zhong
Lead-Free 7938 7800 3.639 6.63E-02 HVQFN-24 de Vries, Jansen, van Driel
Lead-Free 9079 5250 2.828 5.80E-02 HVQFN-48 de Vries, Jansen, van Driel
Lead-Free 3366 4500 5.528 0.4021 HVQFN-72 de Vries, Jansen, van Driel
Tin-Lead 2463 1635 8.932 0.67 QFN-44 Tee, Ng, Yap, Zhong
Tin-Lead 976 2015 17.76 1.702 QFN-36 Tee, Ng, Yap, Zhong
Tin-Lead 956 2165 19.36 1.725 QFN-28 Tee, Ng, Yap, Zhong
Tin-Lead 3542 2928 10.23 0.4658 QFN-20 Tee, Ng, Yap, Zhong
Lead-Free 1437 1280 10.04 0.3663 QFN-40 Mukadam, Meilunas, et al
Lead-Free 1448 2063 10.92 0.3635 QFN-42 Mukadam, Meilunas, et al
Lead-Free 3651 803 5.565 0.1442 QFN-44 Mukadam, Meilunas, et al
Tin-Lead 760 947 16.77 2.17 QFN-20 Zhang and Lee & Kim, Han, et al
Solder Properties Package Properties
Author(s)
QFN Sherlock Validation Profile
100
1000
10000
100000
100 1000 10000 100000
Predicted
Experimental

26. Validation
BGA
BGA Sherlock Validation Graph
100
1000
10000
100000
100 1000 10000 100000
Predicted
Experimental
Large scatter in data is typical of
experimental results for BGAs

27. Assessment of IPC-TR-579
•Based on round-robin testing of 200,000 PTHs
–Performed between 1986 to 1988
–Hole diameters (250 μm to 500 μm)
–Board thicknesses (0.75 mm to 2.25 mm)
–Wall thickness (20 μm and 32 μm)
•Advantages
–Analytical (calculation straightforward)
–Validated through testing
•Disadvantages
–No ownership
–Validation data is ~18 years old
–Unable to assess complex geometries (PTH spacing, PTH pads)
•Complex geometries tend to extend lifetime
–Difficult to assess effect of multiple temperature cycles
•Can be performed using Miner‟s Rule
•Software conducts calculations for all plated through holes and thermal cycles (combined using Miner‟s Rule)

28. Vibration Environment
Number of natural frequencies to look for within the desired frequency range
Single point or frequency sweep loading Techniques are available for equivalence random vibration to harmonic vibration

29. Vibration (cont.)
•Vibration loads can be very complex
–Sinusoidal (g as function of frequency)
–Random (g2/Hz as a function of frequency)
–Sine over/on random
•Vibration loads can be multi-axis
•Vibration can be damped or amplified depending upon chassis/housing
–Transmissibility
•Response of the electronics will be dependent upon attachments and stiffeners
•Peak loads can occur over a range of frequencies
–Standard range: 20 to 2000 Hz
–Ultrasonic cleaning: 15 to 400 kHz

30. Vibration (cont.)
•Failures primarily occur when peak loads occur at similar frequencies as the natural frequency of the product / design
•Natural frequencies
–Larger boards, simply supported: 60 – 150 Hz
–Smaller boards, wedge locked: 200 – 500 Hz
–Gold wire bonds: 2k – 4kHz
–Aluminum wire bonds: >10kHz

31. Mechanical Loads (Vibration)
•Exposure to vibration loads can result in highly variable results
–Vibration loads can vary by orders of magnitude (e.g., 0.001 g2/Hz to 1 g2/Hz)
–Time to failure is very sensitive to vibration loads (tf  W4)
•Very broad range of vibration environments
–MIL-STD-810 lists 3 manufacturing categories, 8 transportation categories, 12 operational categories, and 2 supplemental categories

32. Interpretation (Vibration)
•SAC is „stiffer‟ than SnPb
–For a given force / load, it will respond with a lower displacement / strain (elastic and plastic)
•Low-cycle fatigue (plasticity driven)
–Under displacement-driven mechanical cycling, SnPb will tend to out-perform SAC (e.g., chip scale packages [CSP])
–Under load-driven mechanical cycling, SAC will tend to out-perform SnPb (e.g., leads of thin scale outline packages [TSOP])
•High-cycle fatigue (elasticity driven)
–Stiffer solder (i.e., SAC), lower strain range

33. Vibration Software
Implementation
c L
c

 
• The software uses the finite element results for board
level strain in a modified Steinberg like formula that
substitutes the board level strain for deflection and
computes cycles to failure
• Critical strain for the component
ζ is analogous to 0.00022B but modified for strain
c is a component packaging constant, 1 to 2.25
L is component length

34. Software Vibration

35. Vibration and Shock Summary

36. Vibration Results - Example
Board level strains during vibration exposure

37. Vibration Results – Component Breakdown

38. Environments (Mechanical Shock)
•Initially driven by experiences during shipping and transportation
•Increasing importance with use of portable electronic devices
–A surprising concern for portable medical devices
–Floor transitions (1 to 5 inch „drop‟)
•Environmental definitions
–Height or G levels
–Surface (e.g., concrete)
–Orientation (corner or face; all orientations or worst- case)
–Number of drops

39. Software Shock
•Implements Shock based upon a critical board level strain
•Will not predict how many drops to failure
•Either the design is robust with regards to the expected shock environment or it is not
•Additional work being initiated to investigate corner staking patterns and material influences

40. Shock Results - Example

41. Shock Results – Component Breakdown

42. Constant Failure Rate Module
•MIL-HNBK- 217F Calculations

43. Life Graphs - Examples

44. Example: Fewer Cycles No Vibration

45. Possible Actions
•Based on the reliability assessment one may decide to increase reliability by:
–Changing package types
–Changing location of components
–Changing the mount point locations
–Increasing Cu thickness in PTHs
–Etc.
•Trial and error can be used on the virtual board
•The software can also be used to determine the TC test conditions that best simulate the field use conditions.

46. Reliability Assurance Tool
•This powerful software tool uses the principles of PoF to predict the life of CCAs prior to prototypes being built.
•Optimization of the design layout can now take place early in the design cycle which greatly improves the chances of designing it right the first time.