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Charan
Charan
Charan
Charan
Charan
Charan
Charan
Charan
Charan
Charan
Charan
Charan
Charan
Charan
Charan
Charan
Charan
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Charan

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  • 1. DESIGN AND SIMULATION OFRADIX-4 MULTIPLIER USINGMENTOR GRAPHIC TOOLSPROJECT BY10BA1A0411,10BA1A0419,10BA1A0425
  • 2. Outlines• Background & Motivation• Principles• Implementation & Simulation• Advantages & Disadvantages• Conclusions
  • 3. Background & Motivation• One of the most critical functions carried outby ALU• Digital multiplication is the most extensivelyused operation (especially in signalprocessing), people who design digital signalprocessors sacrifice a lot of chip area in orderto make the multiply as fast as possible• Innumerable schemes have been proposed forrealization of the operation
  • 4. Objective• In array multiplier we use thesigned,unsigned numbers separetly butwe want to perform the bothsigned,unsigned operations at the sametime for time delay by using theverilogHDL.
  • 5. Introduction The booth encoding performs the signed unsignedmodified encoding multiplier. The requirement of the modern computer system isdedicated and very high speed unique multiplier unitfor signed and unsigned numbers. The carry save adder(CSA) tree and the final carrylook ahead(CLA) adder used to speed up themultiplier operation.
  • 6. Multiplication Schemes• Serial Multiplication (Shift-Add)– Computing a set of partial products, and thensumming the partial products together.– The implementations are primitive with simplearchitectures (used when there is a lack of a dedicatedhardware multiplier)• Parallel Multiplication– Partial products are generated simultaneously– Parallel implementations are used for highperformance machines, where computation latencyneeds to be minimized
  • 7. EXISTING METHOD• IN general a multiplier uses array of full adders or wallacetree instead of the array of fas.,i.e.,this multiplier mainlyconsists of the two parts: a tree to compress the partialproducts such as wallace tree,and final adder.• Because wallace tree is to add the partial products fromencoder as parllel as possible,its operation time isproportional to, where is the number of outputs• The most effective way to increase the speed of a multiplier isto reduce the number of the partial products.
  • 8. Principles of Array Multiplier• 4*4 bit multiplicationa3 a2 a1 a0× b3 b2 b1 b0a3b0 a2b0 a1b0 a0b0a3b1 a2b1 a1b1 a0b1a3b2 a2b2 a1b2 a0b2a3b3 a3b2 a3b1 a3b0p7 p6 p5 p4 p3 p2 p1 p0
  • 9. Principles of Array Multiplier(Cont.)
  • 10. For 4*4 Array Multiplier, it needs 16AND gates, 4 HAs, 8FAs (total 12Adders)For m*n Array Multiplier, it needsm*n AND gates, n HAs, (m-2)*n FAs,(total (m-1)*n Adders)
  • 11. Advantages & Disadvantages• Advantages:– Minimum complexity– Easily scalable– Easily pipelined– Regular shape, easy toplace & route• Disadvantages:– High power consumption– More digital gatesresulting in large chip area
  • 12. PROPOSED METHOD• TO reduce the number of calculation steps for partialproducts,MBE algorithm has been applied mostly wherewallace tree has taken the role of increasing the speed to addthe partial products.• To increase the speed of the MBE algorithm many parallelmultiplications have been detected but a configurable boothmultiplier has been designed which provides a flexiblearithmatic capacity an d a tradeoff between output precisionand power consumption.
  • 13. Booths Algorithm Advantages• Multiplication can be sped up• When large number of consecutive 1s inmultiplier• Replace consecutive additions• Subtract at least-significant end• Add at position to the left of the most-significant end
  • 14. Implementation & Simulation• Verilog (ISE 10.1)• Multiplier Design– Cell: MulCell– Multiplier: ArrayMult• Testbench– Stimulus– Verification & Timing
  • 15. Conclusions• Array multiplier is implemented and verified inVerilog• Although it utilizes more gates, theperformance can easily be increased usingpipeline technique• As a parallel multiplication method, arraymultiplier outperforms serial multiplicationschemes in terms of speed.
  • 16. Questions?

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