Your SlideShare is downloading. ×
Upcoming SlideShare
Loading in...5

Thanks for flagging this SlideShare!

Oops! An error has occurred.

Saving this for later? Get the SlideShare app to save on your phone or tablet. Read anywhere, anytime – even offline.
Text the download link to your phone
Standard text messaging rates apply



Published on

Published in: Technology, Business
  • Be the first to comment

  • Be the first to like this

No Downloads
Total Views
On Slideshare
From Embeds
Number of Embeds
Embeds 0
No embeds

Report content
Flagged as inappropriate Flag as inappropriate
Flag as inappropriate

Select your reason for flagging this presentation as inappropriate.

No notes for slide


  • 1. Volume 1, Issue 1 Devoted to our POWER Systems(p,i) customers in OH PA, KY, IN, MI , April 2009 Midwest POWER Systems Newsletter Midwest POWER Systems Newsletter In this Issue What is this Newsletter Using POWER6 based blades Your Midwest Region POWER Field Technical Support Using blades is a great way to reduce cost in • What is this? Specialists (FTSS’s) in the Western Pennsylvania, Ohio, the data center. By sharing a chassis and Northern Kentucky, Indiana, and Michigan area would chassis components, blades reduce cabling, • Using POWER6- like to provide their customers, systems administrators power, and footprint in your data center. This based blades and systems engineers with up-to-date information and column will focus on the POWER6 family of news related to IBM POWER-based systems in this blades, JS12 & JS22. This issue will serve as • AIX tip Quarterly Newsletter. an introduction to the JS line. b • IBM Systems This inaugural issue for the 2nd Quarter of 2009, The JS12 and JS22 blades fit into the same represents our commitment to providing you a high BladeCenter chassis as the IBM System x line. Director 6.1 quality communiqué. We hope you find this useful and In fact, all currently offered IBM blades (H, JS, update please do not hesitate to contact any of the contributors LS, & QS) can run in the same chassis, at the (listed at end of this newsletter) regarding its contents, same time. This provides a great deal of • POWER-i (i- your thoughts on future topics, and other constructive flexibility. series) corner feedback. The JS blades run AIX, IBM i, Redhat and/or • VIOS Tip We look forward to providing you with additional SuSE linux. VIOs 1.5 and 2.1 are also newsletters in the future. Give us your feedback. supported. Because they are part of the Power • PowerVM Contact Rick Beach ( System family, they support the same PowerVM Options features that you leverage on your larger IBM servers. PowerVM Standard Edition comes • POWER with either blade and Enterprise is available. Architecture AIX TIP: How to tell my micro- partition’s The JS12 has a single socket, dual core, 3.8 Article MAX utilization? GHz processor. The integrated memory controller supports eight pluggable DDR2 • Power5/Power6 DIMMs, which must be installed in pairs. The Firmware What is the MAX utilization for a given UNCAPPED total memory supported is 2 GB to 64 GB. Zero micro-partition (SPLPAR)? Since the number of Virtual to two SAS hard drives are supported on the Update blade. Processors in an SPLPAR cannot exceed 10 times the • Events Calendar entitlement/processing units of that SPLPAR, the The JS22 has two dual core processor sockets theoretical MAX is 1000% utilization. However, MOST and runs at 4.0GHz. Four DDR2 DIMM slots support from 2 GB to 32 GB of RAM. This customers don’t follow this 10:1 ratio of vcpus to blade supports 0 to 1 SAS disk drive on-board. entitlement. You typically use a smaller ratio. So how do you determine any particular SPLPAR’s max? Both JS blades have a built-in dual port 1 Gb Ethernet. They support a variety of PCI-x and PCI-e I/O daughter cards. PowerHA and Live From a mathematical formula standpoint its: Partition Mobility are also available for both. (vcpus / entitlement%)* 100 = max util % To learn more, please see IBM Power Blade available servers at: IBM Power Blade Servers Example : Uncapped SPLPAR with 4 vcpus and .5 Contributed by Richard Milton entitlement. (4 / .50) * 100 = 8 * 100 = 800%. This particular micro-partition could theoretically get 800% of its entitlement should the resources be available! Another example: Uncapped SPLPAR, 3 vcpus, entitlement of .75. The math would yield a maximum utilization percent of  400% (3 / .75) * 100 = 400. Contributed by Rick Beach ( AIX Command(s): Determining MAX utilization from the command line! # ENT=`lparstat -i | grep "Entitled" | grep -v Pool | awk '{print $4}'` # VP=`lparstat -i | grep Online | grep CPU | awk '{print $5}'` # echo $VP/$ENT*100 | bc <result displayed here) 2nd Quarter Midwest Newsletter 6/16/2010 Page 1 of 6
  • 2. Your System i loyalty is rewarded Take advantage of significant savings when upgrading to Power Systems. • Save 50% on IBM i license entitlements for Systems Director 6.1 Installation Tips select Power Systems. Which platform to run Systems Director on? Hurry this promotional Systems Director 6.1 is supported on Windows 2003, AIX 5.3/6.1, RedHat, SuSe. I have discount offering ends on personally installed on Windows 2003 and AIX6.1. Systems Director 6.1 is easy to install and June 30, 2009. installation takes about an hour on either Windows or AIX. Announcement Letter For more information on Systems Director 6.1 resources and documentation see: IBM Systems 309-517 Director Documentation and Resources • No charge IBM i processor First, download the latest code from the download site, even if you don’t see any byte size entitlement on difference from a previous download. Since version control is not implemented at this time and replacement systems updates do not necessarily reflect a change in byte size. From this site you can download Systems Director 6.1, common/platform agents, and plug-ins for advanced functions like Active For more information Energy Manager, Electronic Agent, and Systems Director migration for 5.2 – 6.1. contact your IBM or To obtain the latest download code see: IBM Systems Director Downloads Business Partner rep or go to the iLoyalty Web Site. You will need to download SSH from SourceForge. SSH and SSL is used for the primary Contributed by John Bizon authentication. Here are the filesets that I have installed: ( openssh.base.client COMMITTED Open Secure Shell Commands openssh.base.server COMMITTED Open Secure Shell Server openssh.license COMMITTED Open Secure Shell License COMMITTED Open Secure Shell  Su openssl.base COMMITTED Open Secure Socket Layer pp openssl.license COMMITTED Open Secure Socket License ort openssh.base.client COMMITTED Open Secure Shell Commands for openssh.base.server COMMITTED Open Secure Shell Server openssl.base COMMITTED Open Secure Socket Layer Hardware and See: Source Forge Project Support Planning Information (i) NOTE: The installation of the “Director.Server.ext.FSPProxy.rte” requires ‘csm.hc_utils’ which can be downloaded from IBM Cluster Systems Management(CSM) • V5R3 is being withdrawn from support on April 30, Security and Users. Authentication is provided by the local operating system, and users need to 2009 be created on the local security method, (/etc/passwd, /etc/group or Windows users) or through i5/OS and OS/400 LDAP. All communication between Systems Director and servers use SSH and need Release Cycle Web Site root/administrator for monitoring and managing. • Power 6 systems are the After initial install, Systems Director is ready to start discovering servers. last to support the Contributed by Doug Herman ( following: -RIO/HSL I/O drawers and towers - IOPs notes (IBM i only) WAN/LAN support of SDLC/SNA devices requiring IOP - Twinax devices require an IOP or OEM converter PHP on i-series - Support for some older Are you looking to develop or deploy web applications on IBM i? PHP, the leading scripting tapes drives/libraries language for web applications, provides an open and easy to use alternative and gives you require IOP access to thousands of open source applications and scripts. Thousands of IBM i customers around the world have downloaded Zend’s PHP products for i for a wide variety of web • Share this insight to help application development and deployment initiatives. Starting in February of 2009, Zend build plans for Core, the PHP runtime, is preloaded with IBM i 6.1 and 5.4 . modernizing I/O • See Upgrade Planning So what is PHP? PHP is a powerful, open, and easy-to-use Web application environment that web site for more has the support of a large community with thousands of applications and components to share. It information . is an open source scripting language that is designed for Web application development and enables very simple scripting. Short for "PHP: Hypertext Preprocessor ," PHP is widely used for content management, customer relationship management, database access, ecommerce, forums, blogs, wikis, and other Web-based applications. With more than 20 million Internet domains and countless more intranet sites, PHP is gaining attention within the development community and enterprises around the world. Additional information at Zend and IBM i. Contributed by Dean Woodke, (  Su pp ort for Dean Woodke so 2nd Quarter Midwest Newsletter 6/16/2010 Page 2 of 6
  • 3. VIOS Tip: Running a VIOS command as root user (or oem_setup_env ) Always ‘switching’ between padmin and root user to look at devices, create devices, etc… in your Virtual I/O Server? Try ‘prefixing’ the virtual I/O server command you’d like to run with /usr/ios/cli/ioscli Ex: # /usr/ios/cli/ioscli lsmap –vadapter vhost0 --OR-- # /usr/ios/cli/ioscli lsdev -virtual POWERVM Virtualization Capabilities Virtualization is the Fastest Growing Server Software Component in the Industry. PowerVM is the hardware and software that delivers industry-leading virtualization on IBM POWER processor-based servers for UNIX, i and Linux clients. Features of PowerVM virtualization software for Power™ Systems are  POWER Hypervisor: Support for virtualization and multiple operating environments.  Logical Partitioning: Flexibility to create either dedicated LPARs and/or Micro-partitions.  Shared Dedicated Capacity: Unused dedicated processor resource in a LPAR can be shared with other LPARs.  Dynamic Logical Partitioning (DLPAR): Dynamic resource movement between LPARs.  Multiple Shared Processor Pools: Cap processor resources for a group of partitions and share processing units between the LPARs in a group. Shared Processor Pools provide additional processing units on demand to micro-partitions dynamically.  PowerVM Active Memory™ Sharing (SOD – Statement of Direction): IBM intends to enhance PowerVM with Active Memory Sharing (ASM), an advanced memory virtualization technology. Active Memory Sharing will intelligently flow memory from one partition to another for increased utilization and flexibility of memory usage. This is planned to be available with PowerVM Enterprise Edition for AIX 6.1, Linux and i 6.1 partitions that use VIOS and shared processors on POWER6 processor-based systems.  Virtual I/O Server (VIOS): Virtualizes physical resources such as SCSI, Ethernet and SAN devices to share with multiple client LPARs running either AIX, Linux or IBM i OS.  Integrated Virtualization Manager (IVM): Simplifies partition management for entry systems. It is a browser based tool and provides the HMC functionality in a VIOS partition.  Lx86: Enables to run most x86 32 bit Linux binaries on Power Systems without recompilation. This is installed in a Linux partition on a Power Systems server.  Live Partition Mobility: Feature to move a AIX or Linux LPAR live from one POWER6 processor based server to another.  System Planning Tool: Simplifies the planning, ordering and deployment of Power servers with PowerVM. iSeries Redbooks Website PowerVM optimizes the computing resources by sharing them on Power Systems servers (Blades, Entry, Midrange and Enterprise class) and thus reduces TCO and improves ROI. Computing resources such as processors, memory (SOD), boot disks, network and SAN adapters can be shared by multiple LPARs in a consolidated environment. Recent Releases IBM PowerVM is offered in three flavors - Express Edition, Standard Edition and Enterprise Edition. IBM offers an easy upgrade path iSeries IP Networks: Dynamic! May 5, 2004 SG24-6718-00 V5 TCP/IP Applications to another with the Capacity upgrade option. Express Edition is available only on 11, 2004 and 550 servers from one edition on the IBM iSeries May Power 520 SG24-6321-00 whereas Standard and Enterprise Edition is available on all Power Systems servers. Using IBM WebSphere Host Access Transformation Services V5 May 17, 2004 SG24-6099-00 Lotus Domino 6 PowerVM Offerings for more the IBM See IBM Multi-Versioning Support on information. Contributed by Ravi Singh ( 2004 iSeries May 21, SG24-6940-00 IBM i5 and iSeries System Handbook: IBM i5/OS Version 5 Release 3 May 28, 2004 GA19-5486-25 Feature/Function Express Standard Enterprise Domino 6 for iSeries Best Practices Guide Edition Edition Edition June 18, 2004 SG24-6937-00 The IBM TotalStorage Tape Libraries Guideand 550 Servers Supported Power Systems 520 for Open Systems JS21, JS22, JS22, June 25, 2004 SG24-5946-02 IBM Power Systems Power Systems and PeopleSoft Technology Foundation: Ensuring a High Quality of Service June 29, 2004 SG24-6308-00 Student Edition WebSphere Development Studio for iSeries V5.0 July 15, 2004 SG24-7086-00 Max LPARs 2 LPARS +1 VIOS per Server 10 / Core 10 / Core Management IVM IVM & HMC IVM & HMC VIOS Yes Yes Yes Live Partition Mobility No No Yes Shared Processor Pools No Yes (P6 & HMC Required) Yes (HMC Required) Shared Dedicated Capacity Yes Yes (POWER6: Servers & Yes Blades) Operating Systems AIX / Linux / i AIX / Linux / i AIX / Linux / i PowerVM Lx86 Yes Yes Yes 2nd Quarter Midwest Newsletter 6/16/2010 Page 3 of 6
  • 4. Power Architecture So how does IBM design those world- class leading Power Microprocessors? This is probably, the single most asked question I get on a day to day basis. IBM has enjoyed a large lead in microprocessor technology for many years thanks to our design teams. Let’s explore, briefly, how a Power processor is designed. Power design is a combined effort from design teams located in: Austin (TX), Burlington (VT), Raleigh (NC), Rochester (MN) and Böblingen (Germany). Our lead design team is located in Austin along with our main Power Systems Briefing Center. As a side, if you’ve never had a chance to visit an IBM Briefing Center, ask your IBM representative today; it’s an eye opening and very worthwhile experience. The first step in any design is to set the direction of the overall architecture of the specific chip being designed (i.e. Power5, Power6, etc). This is done as a collaboration between the various architects between sites. Microprocessor architects are the most experienced engineers within a design group. When setting the direction for a design, performance goals, reliability considerations and other factors are all considered. This design stage is called high level design (HLD). Before a processor design exits HLD, a performance model is made and the proposed design is “test driven” for performance. If the simulated performance is lacking then changes must be made in the design. When the proposed design meets all design criteria the real work begins. IBM usually splits its design teams into several smaller teams working on various projects. Some teams design game chips (Nintendo, Sony, Microsoft), others design high end chips (Power6, Power7) and still others design embedded processors (PowerPC 750, embedded processors used in NASA Mars mission, etc). There is some overlap between teams as some engineers may participate on more than one team. In addition to architects, within each team there are several roles, Logic Designers, Verification Engineers, Circuit Designers and Layout Technicians. Again, some designs may have multiple roles, but as a whole everyone on the team is very specialized. Let’s explore these roles: Logic designers develop the gate level logic of the processor. Before other engineers have any work to do, the logic design teams have to create a “first draft” of the processor. At this point, the verification team will compile the logic into a model of the processor which is used to run virtual compute test cycles. These test cycles run on the model are comprised of test programs and logic checkers that look for bugs in the compiled logic. When bugs are found the logic designer will investigate and fix the problem in an iterative fashion with the verification engineer. IBM runs several billion/trillion virtual clock cycles before any chip ever leaves our design labs. This gives IBM the utmost confidence that each chip is free of bugs. Once the logic design has begun, the circuit designers start their task. Their job is to translate the gate level logic into circuits used to do the work of the processor. As the logic designers change their logic the circuit designers must change their circuits in like fashion. Layout Technicians work with circuit designers. These skilled individuals carefully render each circuit into a manufacturable form. The layout of a modern VLSI CMOS chip is very much like a ridiculously large jigsaw puzzle. Each area of the silicon die (a die is a term referencing each processor on a wafer) must be carefully laid out in such a fashion as not to be too large or oddly shaped, adversely squeezing adjacent areas for space. In addition to all this design criteria, the design must be fast. Slow circuits are constantly analyzed and massaged for speed. After all, the chip is only as fast as its slowest circuit. This discussion only centers on the immediate design team of each microprocessor. It is important not to forget the teams of engineers outside of the immediate processor design that make each chip successful. Without these folks, even the best design will fall flat on its face. A design cycle for a high end processor usually lasts on average four years. During this time, the logic designers, verification engineers, circuits designers and layout techs go back and fourth with each other solving problems, working through bugs, and speeding up circuits. Once this process completes and the design is considered complete it is time for the RIT. RIT is an IBM term for “Release Interface Tape”, and antiquated term first used in the early days of semiconductor design. It specifically refers to writing the design to tape and shipping (carrying) it over to the manufacturing facility to start the fabrication process. RIT day in IBM is a big day. It’s the first time the design teams can take a break. After RIT, the teams will review their work for any patentable ideas. All ideas are submitted to IBM’s IP law department for patent consideration. Any unique and novel ideas are sent to the patent office in Washington DC. IBM engineers are famous for producing more patents each year than any other company in the world; many of these patents arise from IBM’s design activities. This is simply a brief overview of the IBM microprocessor design process. I could talk all day on this specific topic and often do if given the chance. If you’d like a more in depth view into this world I’d be happy to expand on any given topic. The next several articles will explore design elements in modern Power microprocessors. IBM Power Architecture – Providing real business value every day! Contributed by DJ Singley ( 2nd Quarter Midwest Newsletter 6/16/2010 Page 4 of 6
  • 5. Power5/Power6 Firmware Updates Firmware Updates There are two reasons why you might want to update microcode: 1. IBM periodically updates microcode to add new function for your systems and adapters. For example, you might want to install new system flash microcode to add boot support for a boot device that was not available when your system was shipped; or you might want to update the microcode on a graphics adapter so you can attach a new display that was not previously supported. 2. You may want to update your microcode to fix a problem. Even IBM's rigorous test process does not always catch every problem. Whenever possible, we update the microcode to fix a problem. Using “Fix Central” to obtain the updates If you use IBM’s Fix Central website, you can not only obtain system microcode, but are given the following options: 1- All firmware components. Obtain system firmware, device firmware, and HMC updates. The power subsystem firmware will be included if applicable 2- System firmware. Obtain system firmware only. The power subsystem firmware will be included if applicable. 3- Device firmware. Obtain device firmware only. Available for adapters hard disks and media devices. 4- HMC Firmware. Obtain HMC Recovery images, service packs, and specific fixes. Fix Central also can help answer your questions – these links are available to help you decide what levels you should be running: • Frequently Asked Questions • Best practices • Subscription services • Quick link to description files • Quick link to latest fixes on CD-ROM • Fix Level Recommendation Tool • Supplemental Firmware • Firmware survey tools • Diagnostic CD-ROMs • Tape drive information • ISO / IEC compliant firmware • Power 5 HPSNM/IBMNM fixes and links • P5 and P6 HMC Network Install files Selected System Microcode Levels (as of March 24 th , 2009) 9119-FHA (595): EH340_039 9117-MMA(570): EM340_041 8203-E4A (520): EL340_039 Next Issue – Deciphering code levels, concurrent updates and deferred fixes. Contributed by Ross Coniglio ( Contributors OH and No. KY Cleveland, OH Kevin McCombs Cincinnati, OH Ross Coniglio Columbus, OH Rick Beach Columbus, OH DJ Singley dsingley@us, IN PA Indianapolis, IN Brett Murphy Pittsburgh, PA MI Flint, MI Dean Woodke,com Detroit, MI John Bizon Detroit, MI Ravi Singh Detroit, MI Rick Milton Detroit, MI Doug Hermann Mgr, Brian Richmond 2nd Quarter Midwest Newsletter 6/16/2010 Page 5 of 6
  • 6. 2009 Power Midwest OI Events January February March S S Su M Tu W Th F Sa u M Tu W Th F Sa u M Tu W Th F Sa 1 2 3 1 2 3 4 5 6 7 1 2 3 4 5 6 7 4 5 6 7 8 9 10 8 9 10 11 12 13 14 8 9 10 11 12 13 14 11 12 13 14 15 16 17 15 16 17 18 19 20 21 15 16 17 18 19 20 21 18 19 20 21 22 23 24 22 23 24 25 26 27 28 22 23 24 25 26 27 28 25 26 27 28 29 30 31 29 30 31 April May June S S Su M Tu W Th F Sa u M Tu W Th F Sa u M Tu W Th F Sa 1 2 3 4 1 2 1 2 3 4 5 6 5 6 7 8 9 10 11 3 4 5 6 7 8 9 7 8 9 10 11 12 13 12 13 14 15 16 17 18 10 11 12 13 14 15 16 14 15 16 17 18 19 20 19 20 21 22 23 24 25 17 18 19 20 21 22 23 21 22 23 24 25 26 27 26 27 28 29 30 24 25 26 27 28 29 30 28 29 30 31 Date Event Description City FTSS 2/13 Cincinnati Power Customer Council Cincinnati Ross Coniglio 2/24-2/ 25 Remote VIO Class Pilot Indianapolis Brett Murphy 2/24 AIX Advanced Tuning Columbus DJ Singley 2/25 AIX Advanced Tuning Columbus DJ Singley 2/26-2/ 27 Remote VIO Class Pilot Indianapolis Brett Murphy 3/5 Power System p Virtual Users Group Virtual Joe Armstrong 3/19 Power System i Virtual Users Group Virtual Jamie Barnes 3/25 Oracle Performance Turning Columbus Rick Beach 3/26 Oracle Performance Turning Indianapolis Brett Murphy 3/27 Oracle Performance Turning Cincinnati Ross Coniglio 3/26-3/ 27 Micro-Partitioning p VUG Joe Armstrong 4/1 Power Trends and Directions Toledo DMC (IBMBP) 4/21-4/ 23 AIX for Pros Class Detroit Rick Milton 4/24 Power HA and Technical Update Cincinnati Ross Coniglio 5/5-5/7 Linux on Power Columbus Rick Beach John Bizon & Rick 5/6 Power Announcement Overview Grand Rapids Milton 05/08 'ish Power Announcement Overview Detroit Brian Richmond 5/29 Live Partition Mobility Cincinnati Ross Coniglio 6/5 Demystifying Virtualization Columbus Rick Beach POWER System p Virtual Users Group POWER System i Virtual Users Group 2nd Quarter Midwest Newsletter 6/16/2010 Page 6 of 6