IMPLEMENTATION OF FAST MULTIPLIER ARCHITECTURES FOR CONVOLUTION APPLICATION IN SIGNAL PROCESSING K.SUSHMA(709212142027) B.GAYATRI(709212142008)
INTRODUCTION Convolution is the fundamental and important operation in Signal processing Multiply-accumulate operation is widely used in Convolution Computes the product of two numbers and adds that product to an accumulator Consists of a multiplier followed by an accumulator that contains the sum of the previous consecutive products
VEDIC MATHEMATICS Ancient technique which simplifies multiplication, division, squaring and cubing of a number etc . Unique technique of calculations based on simple principles and rules. Consists of sixteen mathematical sutras and Upa sutras.
URDHVA- TRIYAGBHYAM One of the sixteen Vedic sutras. Urdhva means vertical and Triyagbhyam means crosswise.
LINE DIAGRAM FOR MULTIPLICATION OF TWO- 4 BIT NUMBERS STEP 1: STEP 2: STEP 3:
COLUMN BYPASS MULTIPLIER If any bit of the multiplicand is zero, then the corresponding partial product will be zero Therefore, the column of adders need not to be activated If aj=0 then the corresponding operations in a column can be disabled
CIRCUIT DIAGRAM OF 4X4 COLUMN BYPASS MULTIPLIER
BLOCK DIAGRAM OF MODIFIED FULL ADDER CELL Full-Adder Tri-state buffer Mux 2-1
SIMULATED WAVE FORM OF 16-BIT COLUMN BYPASS MULTIPLIER