IMPLEMENTATION OF FAST MULTIPLIER ARCHITECTURES     FOR CONVOLUTION APPLICATION IN SIGNAL                  PROCESSING     ...
INTRODUCTION Convolution is the fundamental and  important operation in Signal processing Multiply-accumulate operation ...
BLOCK DIAGRAM OF MAC UNIT
 Different multipliers likea)Vedic multiplierb)Column bypass multiplierc)Multiplier using different Compressors  can be u...
VEDIC MULTIPLIER
VEDIC MATHEMATICS   Ancient technique which simplifies    multiplication, division, squaring and    cubing of a number et...
URDHVA- TRIYAGBHYAM   One of the sixteen Vedic sutras.   Urdhva means vertical and    Triyagbhyam means crosswise.
LINE DIAGRAM FOR MULTIPLICATION     OF TWO- 4 BIT NUMBERS   STEP 1:   STEP 2:   STEP 3:
   STEP 4:   STEP5:   STEP 6:   STEP 7:
CIRCUIT DIAGRAM OF 4-BIT VEDIC MULTIPLIER
BLOCK DIAGRAM OF 8X8 VEDIC        MULTIPLIER
SIMULATED WAVE FORM OF 16-BIT VEDIC    MULTIPLIER USING XILINX 13.1i
SIMULATED WAVEFORM OF 16-BITMAC
4-BIT VEDIC MULTIPLIER MASK           LAYOUT
SIMULATED OUTPUT WAVEFORM USING    MICROWIND LAYOUT EDITOR
COLUMN BYPASS  MULTIPLIER
COLUMN BYPASS MULTIPLIER   If any bit of the multiplicand is    zero, then the corresponding partial    product will be z...
CIRCUIT DIAGRAM OF 4X4 COLUMN      BYPASS MULTIPLIER
BLOCK DIAGRAM OF MODIFIED FULL          ADDER CELL   Full-Adder   Tri-state buffer   Mux 2-1
SIMULATED WAVE FORM OF 16-BIT  COLUMN BYPASS MULTIPLIER
SIMULATED WAVEFORM OF 16-BITMAC
4-BIT COLUMN BYPASS MULTIPLIER          MASK LAYOUT
SIMULATED OUTPUT WAVEFORM USING    MICROWIND LAYOUT EDITOR
MULTIPLIER USING DIFFERENTCOMPRESSORS AND ADDERS
BLOCK DIAGRAM OF MULTIPLIER USING    COMPRESSOR AND ADDERS
BLOCK DIAGRAM OF DIFFERENT      COMPRESSORS
ARCHITECTURE OF 8X8 MULTIPLIER     USING COMPRESSORS
SIMULATED WAVE FORM OF 16-BIT MULTIPLIER          USING COMPRESSORS
SIMULATED WAVEFORM OF 16-BIT MAC
4-BIT MULTIPLIER USINGCOMPRESSOR MASK LAYOUT
SIMULATED OUTPUT WAVEFORM USING    MICROWIND LAYOUT EDITOR
SYNTHESIS RESULTS ON XILINX             13.1I                    Multiplier 16*16   Number of LUT’s                    Ved...
APPLICATIONS   Convolution   DSP processor   FFT
THANK YOU
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MAC UNIT USING DIFFERENT MULTIPLIERS

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IMPLEMENTATION OF FAST MULTIPLIER ARCHITECTURES FOR CONVOLUTION APPLICATION IN SIGNAL PROCESSING

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MAC UNIT USING DIFFERENT MULTIPLIERS

  1. 1. IMPLEMENTATION OF FAST MULTIPLIER ARCHITECTURES FOR CONVOLUTION APPLICATION IN SIGNAL PROCESSING K.SUSHMA(709212142027) B.GAYATRI(709212142008)
  2. 2. INTRODUCTION Convolution is the fundamental and important operation in Signal processing Multiply-accumulate operation is widely used in Convolution Computes the product of two numbers and adds that product to an accumulator Consists of a multiplier followed by an accumulator that contains the sum of the previous consecutive products
  3. 3. BLOCK DIAGRAM OF MAC UNIT
  4. 4.  Different multipliers likea)Vedic multiplierb)Column bypass multiplierc)Multiplier using different Compressors can be used
  5. 5. VEDIC MULTIPLIER
  6. 6. VEDIC MATHEMATICS Ancient technique which simplifies multiplication, division, squaring and cubing of a number etc . Unique technique of calculations based on simple principles and rules. Consists of sixteen mathematical sutras and Upa sutras.
  7. 7. URDHVA- TRIYAGBHYAM One of the sixteen Vedic sutras. Urdhva means vertical and Triyagbhyam means crosswise.
  8. 8. LINE DIAGRAM FOR MULTIPLICATION OF TWO- 4 BIT NUMBERS STEP 1: STEP 2: STEP 3:
  9. 9.  STEP 4: STEP5: STEP 6: STEP 7:
  10. 10. CIRCUIT DIAGRAM OF 4-BIT VEDIC MULTIPLIER
  11. 11. BLOCK DIAGRAM OF 8X8 VEDIC MULTIPLIER
  12. 12. SIMULATED WAVE FORM OF 16-BIT VEDIC MULTIPLIER USING XILINX 13.1i
  13. 13. SIMULATED WAVEFORM OF 16-BITMAC
  14. 14. 4-BIT VEDIC MULTIPLIER MASK LAYOUT
  15. 15. SIMULATED OUTPUT WAVEFORM USING MICROWIND LAYOUT EDITOR
  16. 16. COLUMN BYPASS MULTIPLIER
  17. 17. COLUMN BYPASS MULTIPLIER If any bit of the multiplicand is zero, then the corresponding partial product will be zero Therefore, the column of adders need not to be activated If aj=0 then the corresponding operations in a column can be disabled
  18. 18. CIRCUIT DIAGRAM OF 4X4 COLUMN BYPASS MULTIPLIER
  19. 19. BLOCK DIAGRAM OF MODIFIED FULL ADDER CELL Full-Adder Tri-state buffer Mux 2-1
  20. 20. SIMULATED WAVE FORM OF 16-BIT COLUMN BYPASS MULTIPLIER
  21. 21. SIMULATED WAVEFORM OF 16-BITMAC
  22. 22. 4-BIT COLUMN BYPASS MULTIPLIER MASK LAYOUT
  23. 23. SIMULATED OUTPUT WAVEFORM USING MICROWIND LAYOUT EDITOR
  24. 24. MULTIPLIER USING DIFFERENTCOMPRESSORS AND ADDERS
  25. 25. BLOCK DIAGRAM OF MULTIPLIER USING COMPRESSOR AND ADDERS
  26. 26. BLOCK DIAGRAM OF DIFFERENT COMPRESSORS
  27. 27. ARCHITECTURE OF 8X8 MULTIPLIER USING COMPRESSORS
  28. 28. SIMULATED WAVE FORM OF 16-BIT MULTIPLIER USING COMPRESSORS
  29. 29. SIMULATED WAVEFORM OF 16-BIT MAC
  30. 30. 4-BIT MULTIPLIER USINGCOMPRESSOR MASK LAYOUT
  31. 31. SIMULATED OUTPUT WAVEFORM USING MICROWIND LAYOUT EDITOR
  32. 32. SYNTHESIS RESULTS ON XILINX 13.1I Multiplier 16*16 Number of LUT’s Vedic 726 Column Bypass 716 Compressors 729Multiplier Type Vedic Compressors Column BypassVendor Xilinx Xilinx XilinxDevice and Family Spartan3E Spartan3E Spartan3EEstimate Delay 48.258 ns 41.795 ns 46.105 nsPower 81mW 81mW 41mW
  33. 33. APPLICATIONS Convolution DSP processor FFT
  34. 34. THANK YOU

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