Your SlideShare is downloading. ×
0
Final ppt
Final ppt
Final ppt
Final ppt
Final ppt
Final ppt
Final ppt
Final ppt
Final ppt
Final ppt
Final ppt
Final ppt
Final ppt
Final ppt
Final ppt
Final ppt
Final ppt
Final ppt
Final ppt
Final ppt
Final ppt
Final ppt
Final ppt
Final ppt
Final ppt
Final ppt
Final ppt
Upcoming SlideShare
Loading in...5
×

Thanks for flagging this SlideShare!

Oops! An error has occurred.

×
Saving this for later? Get the SlideShare app to save on your phone or tablet. Read anywhere, anytime – even offline.
Text the download link to your phone
Standard text messaging rates apply

Final ppt

3,891

Published on

implementaion of 8 bit conditional sum adder and parallel prefix adder

implementaion of 8 bit conditional sum adder and parallel prefix adder

Published in: Technology
0 Comments
0 Likes
Statistics
Notes
  • Be the first to comment

  • Be the first to like this

No Downloads
Views
Total Views
3,891
On Slideshare
0
From Embeds
0
Number of Embeds
0
Actions
Shares
0
Downloads
142
Comments
0
Likes
0
Embeds 0
No embeds

Report content
Flagged as inappropriate Flag as inappropriate
Flag as inappropriate

Select your reason for flagging this presentation as inappropriate.

Cancel
No notes for slide

Transcript

  • 1. Implementation of 8-bit Conditional Sum adder and Parallel Prefix Adders for Fast Addition<br />by<br />B.Gayathri<br />K.Sushma<br />
  • 2. Introduction<br />The csa generates two sets of outputs for a given group of operand bts say n-bits. Each set includes n-sum bits and an outgoing carry. One set assumes that the incoming carry will be zero, while the other assumes that it will be one. Once the incoming carry is known, we need only to select the carrcet set of outputs by using a multiplexer without waiting for the carrry to further propagate the n-positions.<br />In ppa the aadition is done in parallel fashion there for it is said to be a parallel prefix adder, and some of the parallel prefix adders are<br /> Brent-Kung Adder <br />Kogge-Stone Adder<br />Ladner-Fischer Adder<br />
  • 3. Conditional Sum Adder<br />
  • 4. Circuit Diagram of 8-bit CSA:<br />
  • 5. Top Model View of 8-bit CSA:<br />
  • 6. Simulated Waveform Using Modelsim:<br />
  • 7. CSA Mask layout Using I/O Pads:<br />
  • 8. Simulated Ouput Waveform Using Microwind Layout Editor:<br />
  • 9. Parallel Prefix Adders<br />
  • 10. Block Diagram of Parallel Prefix Adder:<br />
  • 11. STEP1: The pre-calculation stage is implemented by<br />STEP2: carry signals can be generated by using different prefix graphs.<br />STEP3: summation unit can be implemented by<br />
  • 12. Calculation of Carriers in Prefix Graph:<br />
  • 13. Tree Structure Diagrams of Parallel Prefix Adder:<br />Kogge-Stone Ladner-Fischer<br /> Brent-Kung<br />
  • 14. Top Modules for Parallel Prefix Adders:<br /> TOP VEIW OF 8-BIT KOGGE-STONE ADDER<br />
  • 15. TOP VIEW OF 8-BIT LADNER-FISCHER ADDER<br />
  • 16. TOP VIEW OF 8-BIT BRENT-KUNG ADDER<br />
  • 17. Simulated Waveform of KSA Using Modelsim:<br />
  • 18. KSA Mask layout Using I/O Pads:<br />
  • 19. Simulated Ouput Waveform of KSA Using Microwind Layout Editor:<br />
  • 20. Simulated Waveform of LFA Using Modelsim:<br />
  • 21. LFA Mask layout Using I/O Pads:<br />
  • 22. Simulated Ouput Waveform of LFA Using Microwind Layout Editor:<br />
  • 23. Simulated Waveform of BKA Using Modelsim:<br />
  • 24. BKA Mask layout Using I/O Pads:<br />
  • 25. Simulated Ouput Waveform of BKA Using Microwind Layout Editor:<br />
  • 26. Scope of Expansion:<br />Radix-3<br />Radix-4<br />
  • 27. Thanq u<br />

×