Why choose DME?DME supports centralized shared memory (CM) and distributed shared memory (DSM).For medium and large system, we prefer to use DSM structures, since centralizedmemory has already become a bottleneck. Memories are preferrably distributed,featuring good scalability and less delay of memory access. 5
Why choose DME Processor1 Processor2 Cache Cache Interface Interface LocalNI modules in DME DME P1 M4 Memoryare designed to DME P1 M2 Localsupport Standard Memory NIbus interface, e.g. NI We support:AHB,APB,AXI, OCP 1. common bus protocol, easy to integrate into existing system; Network-on-Chip (NoC) 2. configurable for differentDME can perform as data formats;a bridge connectingdifferent IPs withNetwork NI NI DME P1 M2 DME P1 M0 (Local Interface DDR-Interface Memory) DDR controller Custom IP DDR Memory 7
DME ProductDME comes in three flavoursP1 M0 – DME Light – Small footprint, low power, for memory access and similar standard tasksP1 M2 – DME Flex – Programmable, fully featured for maximum flexibility and customizationP1 M4 – DME Flex Plus – Programmable, fully featured, with maximum performance 8
DME Product DME P1 M0 – DME Light DME Interconnect-IP IP-Interface Interconnect Interface Feature list: Transaction Scheduler 1.DSM(distributed shared memory) 2.Private|Shared division 3.Synchronization 4.Privilege level setting (3/2013) Memory Interface Crossbar 5.IP interface support (AHB,APB) (4/2013) 6.Interconnection interface support (AHB,APB) (4/2013) Local Memory Local Memory Local Memory Local Memory 9
DME Product DME P1 M2 Data M anagement Engine InterconnectCPU CPU Interface Interconnect Interface Feature list: Transaction Scheduler h 1.DSM(distributed shared memory) t a p s 2.Private|Shared division M ini- M ini - s a processor processor p y 3.V2P B 4.Synchronization 5.Privilege level setting (3/2013) M emory Interface Crossbar 6.IP interface support (AHB,APB) (4/2013) 7.Interconnection interface support (AHB,APB) Local Local (4/2013) M emory M emory 8.DMA-1, DMA-2 (3/2013) 9.Message passing (4/2013) 10.micro-programming 10
DME Product DME P1 M4 Data M anagement Engine InterconnectCPU CPU Interface Interconnect Interface Feature list: Transaction Scheduler h t 1.DSM(distributed shared memory) a p M ini- M ini - M ini - M ini - s s 2.Private|Shared division a processor processor processor processor p 3.V2P y B 4.Synchronization 5.Privilege level setting (3/2013) M emory Interface Crossbar 6.IP interface support (AHB,APB) (4/2013) Local Local Local Local 7.Interconnection interface support (AHB,APB) M emory M emory M emory M emory (4/2013) 8.DMA-1, DMA-2 (3/2013) 9.Message passing (4/2013) 10.micro-programming 11
DME Planned FeaturesFeaturesAXI Q2 2013DMA-3 Q2 2013Striding access Q2 2013Data shuffling Q2 2013SystemC Model, SIMICS Model Q3 2013Transaction ordering support (memory consistency) Q3 2013Dynamic memory allocation Q4 2013OCP Q4 2013Directory based cache coherence On Demand 12
Application Example: H.264 decoder Task P1 P2 P3 Pn Distributor ITRANS/ INTRA ENTROPY DEQUANT PREDICTION P1 P2 P3 P4 P5 P6 Load Private Shared Store Mem Mem 3 Private SharedNODES MEM MEM MEM MEM MEM MEM Mem Mem Private Shared Mem Mem P7 P8 P9 P10 P11 P12 12NODES Private Shared MEM MEM MEM MEM MEM MEM Mem Mem with DME based on distributed shared memory without DME based on centralized memory 14
Demonstrator Performance Performance(fps) 7775 with DM E 51 QCIF(176x144)50 25 without DM E25 30 31 24 20 with DM E 13 CIF(352x288) 6 without DM E 7 7 3 6 9 node 15
ApplicationsThe DME is useful for many-core SoCs in: Video, signal and network processing Cloud computing Industrial automation Set-top boxes Scientific computing Solid state disks Other high-end embedded applications 16
DME FeaturesNote: Perceived value is based on early customer input, and is application dependent.
Evaluating the DMEFor evaluation of the DME, Elsip offers: Introduction Booklet DME Application DevelopmentPackage, with API libraries C++ Model SIMICS Model Compiled IP Model User manual Demonstrator On-site and off-site support
RoadmapLooking into the future, other IP we’re working oninclude:Packet- and Circuit-switched NoCs (Circuit-switchedcan be faster than packet-switched fortelecom/datacom applications)DRRA - Dynamically Reconfgurable Resource Array(reconfgurable on bus level, better silicon usage thanFPGA)
Thank you! Please go to www.elsip.sefor more information
The foundersAxel Jantsch, CTO. Professor, KTH Electronic Systems since 2002. 20+ years of research, primarily within NoC and SoC. 200+ scientific papers published. Visiting professor of Fudan University in PRC and Cantabria University in SpainAhmed Hemani. Professor, KTH, focus on high-level system integration, design automation, NoC, asynchronous circuit, configurable system. Industrial experience from NSC, NXP/Philips, ABB, Ericsson, Newlogic, Synthesia and Spirea (co-founder).Zhonghai Lu: Professor, KTH, expert in SoC and NoC. Reviewer of 14 international periodicals. Principal investigator of Intel, dealing with future nuclear processor chip frame. 21
ContactSales Director Bengt EdlundMail: firstname.lastname@example.orgPhone: +46 708 722 800CEO Adam EdströmMail: email@example.comPhone +46 702 579 734Address: c/o SICS, PO Box 1263, SE16429, Kista, Sweden 22
Some ELSIP Milestones• Founded by professors Axel Jantsch, Ahmed Hemani and Zhonghai Lu at the Royal Institute of Technology in Stockholm 2011• Received initial funding from Vinnova• Commercial launch when Adam Edström (CEO) and Bengt Edlund (Sales Dir) joined the company Sept 2012• Established subsidiary Memcom in Shanghai March 2012, PRC, with Zhonghai Lu as CTO and Zhuo Zou as CEO. Received initial funding from Wuxi government.• Cooperation with Fudan-Wuxi Institute, Shanghai, PRC• Selected by SICS, the Swedish Institute of Computer Science, as member of SICS Startup Accelerator 23
A particular slide catching your eye?
Clipping is a handy way to collect important slides you want to go back to later.