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Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
Dme presentation-dec2012-rev13-1
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Dme presentation-dec2012-rev13-1

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  • 1. Elsip Adam Edström CEOBengt Edlund Sales Director December 2012 © Elsip 2012. Elsip non-confidential
  • 2. Needs and Solutions
  • 3. Our Sweet Spot Software Defined Data Managementfor Many-core SoC Designs
  • 4. Why were needed Many-core Reconfigurability Complexity
  • 5. Many-core instead of MHzClock frequencies don’tise anymore. Figure shows the clock frequencies of processors presented at ISSCC between 1993 and 2011. After a long period of steady increase the top frequency has leveled off since 2005, at 2-3 Ghz. Source: ISSCC, 2011.
  • 6. Entering the Many-core Era More parallelism is the only way to higherperformance. Sequential programs limits multithreading to~10 instructions per cycle. Higher degrees of parallelism have to beextracted at the process and the applicationlevels. => Hundreds of cores in a few years!
  • 7. Microprocessor ChallengesPerformance100.000.000 10-100x 3D SoC Improvement 10.000.000 memory Many Core Days 1.000.000 25%/Year More than 100x improvement Saturation 100.000 Multi Core days 10%/Year 20%/Year 10.000 Single Core Tornado 1.000 50%/Year 100 Early days 10 20%/Year 1 1980 1990 2000 2010 2020 Serial Challenges Parallel Memory Bandwidth Programming Scaling
  • 8. Makimoto extended
  • 9. Reconfigurability Products are increasingly defined as flexibleplatforms. Standardization is pushed by the fact that futureproducts will include more embedded processing,more communication and more interconnect. => Heterogeneous IC architectures, with flexiblereconfigurable processing cores, and interfacecomponents configurable for standardizedcommunication and interaction protocols.
  • 10. Architecture complexity Computational energy efficiency High Heterogeneous many-core with distributed Homogeneous shared cache and many-core with main memory distributed Multi-core shared cache and with main memory distributed shared cache with common Std single core main memory CPU with cacheOperations/sec/Joule and main memory Design Low Complexity
  • 11. Architecture complexity Computational energy efficiency 3D S High tack D ie Heterogeneous many-core with distributed Homogeneous shared cache and many-core with main memory distributed Multi-core shared cache and with main memory distributed shared cache with common Std single core main memory CPU with cacheOperations/sec/Joule and main memory Design Low Complexity
  • 12. Architecture complexity Computational energy efficiency 3D S High tack D ie Heterogeneous many-core with distributed Homogeneous shared cache and many-core with main memory distributed Multi-core shared cache and with main memory distributed shared cache with common Std single core main memory Elsips target market CPU with cacheOperations/sec/Joule and main memory Design Low Complexity
  • 13. Memory architecture matters Performance of multi-core architectures with centralized and distributed memory organization. Both use a cache, so the observed difference is only due to the delay in accessing uncached data. Source: Elsip. Beyond a certain level of parallelization, any gain in computation time is offsetby the overhead of memory access and synchronization. For the matrix and FFT operations this means that the performance in a 64 nodecentral memory architecture is in fact lower than on 16 nodes. The performance advantage of DSM increases with the number of cores
  • 14. Distributed memory needs A distributed memory architecture needs a data management mechanism supporting: Distributed memory access Flexible private/shared memory space management Synchronization for memory consistency Virtual address space management Scaleability Flexibility Transaction ordering (Memory consistency) Data movement (DMA) functions Message passing Cache coherence
  • 15. Introducing DMEElsips DME – Data Management Engine – is a microprogrammableIP block for on-chip data management.Microprograms in the DME realize the different data managementfunctions. The microprograms can also be downloadeddynamically, giving applications flexibility to adapt the DME tospecific needs.For higher performance and/or power critical applications the DMEcan be hard coded (replaced by a state machine)=> The DME is a software defined MPSoC data management IPblock
  • 16. ApplicationsThe DME is useful for many-core SoCs in: Video, signal and network processing Cloud computing Industrial automation Set-top boxes Scientific computing Solid state disks High-end personal mobile devices Other high-end embedded applications 16
  • 17. Video and Data Packet processors are drivers for faster memory access today- Graphics- Mobile Video- Network Processor- FPGADavid McCann GF Snr Dir
  • 18. SSD
  • 19. Memory
  • 20. Portable
  • 21. The DME provides Programmability => the DME can be optimized for anyparticular application. Lower design risk, allowing late designchanges without need for re-spin Customization => different hardware versions can begenerated for different platform instances. Dynamic programmability => facilitates use of customizedfunctions in different parts or phases of an application. Efficiency => speed and power on par with custom hardware Separation => offloading computing cores, giving higher degreeof parallelism. The DME complies to several standard interfaces, e.g. AHB,APB and AXI, with configurable data bus widths.
  • 22. DME FeaturesNote: Perceived value is based on early customer input, and is application dependent.
  • 23. DME Products
  • 24. The DME architecture 24
  • 25. Application example: SSD NodeInterface PCI-eCPU for flash write-read-remove scheduling and buffermanagementPower budget for the SSD board is 13 W, for MCU is 5w. 25
  • 26. Application example: SSD Node The CPU needs complex functionality and perhaps an OS. The DME is not a good candidate to replace the CPU DME ? DME ? DME ?Depending on theprecise functionality, The DME couldthe DME could be implement the FTLoptimized for buffer (Flash Translationmanagement. Layer) 26
  • 27. Application example 2: SSD Array DesignStar-ring topology instead of treeFrom the rack perspective, it is a star topologyIntra-cluster and inter-cluster nodes are rings. 27
  • 28. Application example 2: SSD Array Design DME + DME + Switch Switch DME + Switch DME + DME + Switch SwitchDME + ELSIP in-house switch can be optimized for managing large SSD Arrays 28
  • 29. Evaluating the DMEFor evaluation of the DME, Elsip offers: Introduction Booklet DME Application Development Package, with APIlibraries C++ Model Compiled IP Model User manual Demonstrator On-site and off-site support
  • 30. The foundersAxel Jantsch, CTO. Professor, KTH Electronic Systems since 2002. 20+ years of research, primarily within NoC and SoC. 200+ scientific papers published. Visiting professor of Fudan University in PRC and Cantabria University in SpainAhmed Hemani. Professor, KTH, focus on high-level system integration, design automation, NoC, asynchronous circuit, configurable system. Industrial experience from NSC, NXP/Philips, ABB, Ericsson, Newlogic, Synthesia and Spirea (co-founder).Zhonghai Lu: Professor, KTH, expert in SoC and NoC. Reviewer of 14 international periodicals. Principal investigator of Intel, dealing with future nuclear processor chip frame. 30
  • 31. Management TeamAdam Edström, CEO. 20+ years as editor and editor-in- chief of Elektroniktidningen, Swedens major electronics publication. Visiting editor at Fortune Magazine in NYC. VP International affairs at SICS, Swedish Institute of Computer Science. Founded three companies prior to Elsip.Bengt Edlund, Sales Director. 30+ years of semiconductor sales, marketing and new technology business development at National Semiconductor and Hewlett Packard. Served as European director of business development, marketing and global sales. 31
  • 32. Some ELSIP Milestones•Founded by professors Axel Jantsch, Ahmed Hemani andZhonghai Lu at the Royal Institute of Technology inStockholm 2011•Received initial funding from Vinnova•Commercial launch when Adam Edström (CEO) andBengt Edlund (Sales Dir) joined the company Sept 2012•Established subsidiary Memcom in Shanghai March 2012,PRC, with Zhonghai Lu as CTO and Zhuo Zou as CEO.Received initial funding from Wuxi government.•Cooperation with Fudan-Wuxi Institute, Shanghai, PRC•Selected by SICS, the Swedish Institute of ComputerScience, as member of SICS Startup Accelerator 32
  • 33. RoadmapLooking into the future, other IP we’re working on include:Circuit-switched NoC (faster than today’s NoC fortelecom/datacom applications)CGRA - Coarse Grain Reconfigurable Architecture (reconfigurableon bus level, better silicon usage than FPGA)
  • 34. ContactSales Director Bengt EdlundMail: bengt@elsip.sePhone: +46 708 722 800CEO Adam EdströmMail: adam@elsip.sePhone +46 702 579 734Address: c/o SICS, PO Box 1263, SE16429, Kista, Sweden 34
  • 35. Thank you!

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