PACKAGINGOF VLSIDEVICESPackage Types,Packaging DesignConsiderationASHUTOSH SINGHB Tech 4th year (ECE)Hindustan Institute ofTechnology0821331024
TABLE OF CONTENTS 1. INTRODUCTION 2. PACKAGE DESIGN CONSIDERATIONS Number of terminals Electrical design considerations Thermal design consideration Reliability Testability 3. PACKAGE TYPES Through hole packages Surface mounted packages Flip chip packages Chip size packages Multi chip modules 3-D VLSI packaging
INTRODUCTIONPackaging of electronic circuits is the science and the art of establishinginterconnections and a suitableoperating environment for predominantly electricalcircuits. It supplies the chips with wires to distributesignals and power, removes theheat generated by the circuits, and provides them with physical supportandenvironmental protection. It plays an important role in determining the performance,cost, andreliability of the system. With the decrease in feature size and increase inthe scale of integration, thedelay in on-chip circuitry is now smaller than thatintroduced by the package. Thus, the ideal packagewould be one that is compact,and should supply the chips with a required number of signal andpowerconnections, which have minute capacitance, inductance, and resistance.The package should remove theheat generated by the circuits. Its thermalproperties should match well with semiconductor chips toavoid stress-inducedcracks and failures. The package should be reliable, and it should cost muchlessthan the chips it carriesELECTRONIC PACKAGING REQUIREMENTS
PACKAGE DESIGNCONSIDERATIONS: PACKAGEPARAMETERSA successful package design will satisfy all given application requirements at anacceptable design,manufacturing, and operating expense.As a rule, application requirements prescribe the number oflogic circuits and/or bitsof storage that must be packaged, interconnected, supplied with electricpower,kept within a proper temperature range, mechanically supported, andprotected against the environment.Thus, IC packages are designed to accomplish the following three basic functions:• Enclose the chip within a protective envelope to protect it from the externalenvironment• Provide electrical connection from chip to circuit board• Dissipate heat generated by the chip by establishing a thermal path from asemiconductor junctionto the external environmentTo execute these functions, package designers start with a fundamental conceptand, using principlesof engineering, material science, and processing technology,create a design that encompasses:1. Low lead capacitance and inductance2. Safe stress levels3. Material compatibility4. Low thermal resistance5. Seal integrity6. High reliability7. Ease of manufacture8. Low costSuccess in performing the functions outlined depends on the package designconfiguration, the choiceof encapsulating materials, and the operating conditions.Package design is driven by performance,cost, reliability, and manufacturingconsiderations. Conflicts between these multiple criteria are common.The design
process involves many trade-off analyses and the optimization of conflictingrequirements.While designing the package for an application, the following parameters areconsidered:Number of TerminalsThe total number of terminals at packaging interfaces is a major cost factor. Signalinterconnections andterminals constitute the majority of conducting elements. Otherconductors supply power and provideground or other reference voltages.Thenumber of terminals supporting a group of circuits is strongly dependent on thefunction of thisgroup. The smallest pin-out can be obtained with memory ICsbecause the stream of data can be limitedto a single bit. Exactly the opposite is thecase with groups of logic circuits which result from a randompartitioning of acomputer. The pin-out requirement is one of the key driving parameters for all levelsofpackaging: chips, chip carriers, cards, modules, cables, and cable connectors.Electrical Design ConsiderationsElectrical performance at the IC package level is of great importance formicrowave designs and hasgained considerable attention recently for silicon digitaldevices due to ever-increasing speed of today’scircuits and their potentiallyreduced noise margins.As a signal propagates through the package, it isdegradeddue to reflections and line resistance. Controlling the resistance and the inductanceassociatedwith the power and ground distribution paths to combat ground bounceand the simultaneous switchingnoise has now become essential. Controlling theimpedance environment of the signal distribution pathin the package to mitigatethe reflection-related noise is becoming important. Reflections, in addition,cause anincrease in the transition time, and may split the signal into two or more pulses withthe potentialof causing erroneous switching in the subsequent circuit and thusmalfunction of the system. Controllingthe capacitive coupling between signal tracesin the signal distribution path to reduce crosstalk is gainingimportance. Increasedspeed of the devices demands that package bandwidth be increased toreduceundue distortion of the signal. All these criteria are related through geometricvariables, such as conductorcross-section and length, dielectric thickness, and thedielectric constant of the packaging body. Theseproblems are usually handled withtransmission line theory.
Thermal Design ConsiderationsThe thermal design objective is to keep the operating junction temperature of asilicon chip low enoughto prevent triggering the temperature-activated failuremechanisms. Thus, the package should provide agood medium for heat transferfrom junction to the ambient/heat sink. It is generally recommended tokeep thejunction temperature below 150°C to ensure proper electrical performance and tocontain thepropensity to fail.Thermal expansion caused by heating up thepackaging structure is not uniform — it varies inaccordance with the temperaturegradient at any point in time and with the mismatches in the thermalcoefficient ofexpansion. Mechanical stresses result from these differences and are one of thecontributorsto the finite lifetime and the failure rate of any packaging structure.In asimplistic heat transfer model of a packaged chip, the heat is transferred from thechip to thesurface of the package by conduction and from the package surface tothe ambient by convection andradiation.Typically, the temperature differencebetween the case and ambient is small, and henceradiation can be neglected. Thismodel also neglects conduction heat transfer out of the package terminals,whichcan become significant. A multilayer example, which models the heat transfer froma region inthe silicon device to the ambient, is shown in Fig. 2.Figure 1: Steady-state heat flow and thermal resistance in a multilayer structure (a) path of heat flow;(b)
The total thermal resistance from the junctionto the ambient is given by:The resulting junction temperature, assuming a power dissipation of Pd, isin analogy with electric circuits. If there are parallel paths for heat flow, the thermalresistances arecombined in exactly the same manner as electrical resistors inparallel.Rθcs, the conductive thermal resistance, is mainly a function of package materialsand geometry. Withthe higher power requirements, one must consider thetemperature dependence of materials selected indesign.Tj depends on package geometry, package orientation in the application, and theconditions ofthe ambient in the operating environment. The heat sink is responsiblefor getting rid of the heat of theenvironment by convection and radiation. Becauseof all the many heat transfer modes occurring in afinned heat sink, the accurateway to obtain the exact thermal resistance of the heat sink would be tomeasure it.However, most heat sink manufacturers today provide information about theirextrusionsconcerning the thermal resistance per unit length.ReliabilityThe package should have good thermo-mechanical performance for betterreliability. A variety of materialsof widely differing coefficients of thermal expansion(CTEs) are joined to create interfaces. These interfacesare subject to relatively highprocess temperatures and undergo many temperature cycles in theiruseful life asthe device is powered on and off. As a result, residual stresses are created in theinterfaces.These stresses cause reliability problems in the packages.TestabilityImplicit in reliability considerations is the assumption of a flawless product functionafter its initialassembly — a zero defect manufacturing. Although feasible inprinciple, it is rarely practiced because ofthe high costs and possible loss ofcompetitive edge due to conservative dimensions, tolerances, materials,andprocess choices. So, several tests are employed to assess the reliability of thepackages.
PACKAGE TYPESIC packages have been developed over time to meet the requirements of highspeed and density. Thehistory of IC package development has been the continuousbattle to miniaturize.Figure 3 illustratesthe size and weight reduction of IC packagesover time.Figure 2: Packaging trendsFigure 3: A generic schematic diagram showing the difference between the surface-mount technology(upper) and through hole technology
Several packages can be classified as follows:Through Hole PackagesThrough-the-board hole mounting technology uses precision holes drilled throughthe board and platedwith copper. This copper plating forms the connectionsbetween separate layers. These layers consist ofthin copper sheets stacked togetherand insulated by epoxy fiber-glass. There are no dedicated via structuresto makeconnections between wiring levels; through holes serve that purpose. Through holesform asturdy support for the chip carrier and resist thermal and mechanical stressescaused by the variationsin the expansions of components at raised temperatures.Different types (Fig. 5) of through holepackages can be further classified as:Figure 4: Different through mount packages.Dual-in-Line Packages (DIPs)A dual-in-line package is a rectangular package with two rows of pins in its twosides. Here, first the dieis bonded on the lead frame and in the next step, chip I/Oand power/ground pads are wire-bonded tothe lead frame, and the package ismolded in plastic. DIPs are the workhorse of the high-volume andgeneral-purposelogic products.Quad Flat Packages (QFPs)With the advances in VLSI technology, the lower available pin counts of therectangular DIP became alimiting factor. With pins spaced 2.4 mm apart on onlytwo sides of the package, the physical size of theDIP has become too great. On theother hand, the physical size of an unpackaged microelectronic circuit(bare die)has been reduced to a few millimeters. As a result, the DIP package has become upto 50 timeslarger than the bare die size itself, thus defeating the objective of shrinkingthe size of the integratedcircuits. So, one solution is to provide pins all around. InQFPs, pins are provided on all four sides. ThinQFPs are developed to reduce theweight of the package.
Pin Grid Arrays (PGA)A pin grid array has leads on its entire bottom surface rather than only at itsperiphery. This way it can offera much larger pin count. It has cavity-up and cavity-down versions. In a cavity-down version, a die is mountedon the same side as thepins facing toward the PC board, and a heat sink can be mounted on its backsidetoimprove the heat flow. When the cavity and the pins are on the same side, thetotal number of pins is reducedbecause the area occupied by the cavity is notavailable for brazed pins. The mounting and wire bonding ofthe dice are also moredifficult because of the existence of the pins next to the cavity. High pin countandlarger power dissipation capability of PGAs make them attractive for differenttypes of packaging.Surface-Mounted PackagesSurface mounting solves many of the shortcomings of through-the-board mounting.In this technology,a chip carrier is soldered to the pads on the surface of a boardwithout requiring any through holes. Thesmaller component sizes, lack of throughholes, and the possibility of mounting chips on both sides ofthe PC board improvethe board density. This reduces package parasitic capacitances andinductancesassociated with the package pins and board wiring. Various types ofsurface-mount packages are availableon the market and can be divided into thefollowing categories.Figure 5: Different surface-mount packages.Small-Outline Packages (SOPs)
The small-outline package has gull-wing shaped leads. It requires less pin spacingthan through-holemountedDIPs and PGAs. SOP packages usually have small leadcounts and are used for discrete, analog,and SSI/MSI logic parts.Plastic-leaded Chip Carriers (PLCCs)Plastic-leaded chip carriers, such as gull-wing and J-leaded chip carriers, offer higherpin counts thanSOP. J-leaded chip carriers pack denser and are more suitable forautomation than gull-wing leadedcarriers because their leads do not extendbeyond the package.Leadless Ceramic Chip Carriers (LCCCs)Leadless ceramic chip carriers take advantage of multilayer ceramic technology.The conductors are leftexposed around the package periphery to provide contactsfor surface mounting. Dice in leadless chipcarriers are mounted in cavity-downposition, and the back side of the chip faces away from the board,providing a goodheat removal path. The ceramic substrate also has a high thermal conductivity.LCCCsare hermetically sealed.Flip-Chip PackagesThe length of the electrical connections between the chip and the substrate can beminimized by placingsolder bumps on the dice, flipping the chips over, aligningthem with the contacts pads on the substrate,and reflowing the solder balls in afurnace to establish the bonding between the chips and the package.This method provides electrical connections with minute parasitic inductance andcapacitance. In addition,contact pads are distributed over the entire chip surface.This saves silicon area, increases themaximum I/O and power/ground terminalsavailable with a given die size, and provides more efficientlyrouted signal andpower/ground interconnections on the chips.Figure 6: Flip chip packaging and its interconnections.
Chip Size Packages (CSPs)To combine the advantages of both packaged chip and bare chip in one solution,a variety of CSPs havebeen developed. CSPs can be divided into two categories:the fan-in type and the fan-out type.Fan-in type CSPs are suitable for memory applications that have relatively low pincounts. This typeis further divided into two types, depending on the location ofbonding pads on the chip surface; theseare the center pad type and the peripheralpad type. This type of CSP keeps all the solder bumps withinthe chip area byarranging bumps in area array format on the chip surface.The fan-out CSPs are used mainly for logic applications: because of the die size topin count ratio,the solder bumps cannot be designed within the chip area.Multi-Chip Modules (MCMs)In a multi-chip module, several chips are supported on a single package. Most multi-chip packages aremade of ceramic. By eliminating one level of packaging, theinductance and capacitance of the electricalconnections among the dice arereduced. Usually, the dice are mounted on a multilayer ceramic substratevia solderbumps, and the ceramic substrate offers a dense interconnection network. Thereare several advantages of multi-chip modules over single-chip carriers. The multi-chip moduleminimizes the chip-to-chip spacing and reduces the inductive andcapacitive discontinuities between thechips mounted on the substrate by replacingthe die-bump-interconnect-bump-die path. In addition,narrower and shorter wireson the ceramic substrate have much less capacitance and inductance thanthe PCboard interconnections.
Figure 7: A generic schematic diagram of an MCM, showing how bare dice are interconnected to anMCM3-D VLSI PackagingThe driving forces behind the development of three-dimensional packagingtechnology are similar to themulti-chip module technology, although therequirements for the 3-D technology are more aggressive.These requirementsinclude the need for significant size and weight reductions, higherperformance,small delay, higher reliability, and potentially reduced powerconsumption.