ONFI 3.0 NAND Flash Controller
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ONFI 3.0 NAND Flash Controller

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The Arasan ONFI 3.0 compliant NAND Flash Controller IP Core is a full featured, easy to use, synthesizable design that is easily integrated into any SoC or FPGA development. Designed to support both ...

The Arasan ONFI 3.0 compliant NAND Flash Controller IP Core is a full featured, easy to use, synthesizable design that is easily integrated into any SoC or FPGA development. Designed to support both SLC and MLC flash memories, it is flexible to use and implement

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ONFI 3.0 NAND Flash Controller ONFI 3.0 NAND Flash Controller Presentation Transcript

  • Introducing the ONFI 3.0NAND Flash Controller By Dennis McCarty
  • Arasan Chip Systems Total IP SolutionsONFI 3.0 FeaturesCore ArchitectureDeliverablesArasan Advantages ©Arasan Chip Systems Inc. 2011
  • Arasan Total IP Solutions©Arasan Chip Systems Inc. 2011
  • ONFI BackgroundONFI Open NAND Flash Interface • NAND Flash Industry ConsortiumVersion 3.0 • Latest specification for NAND Flash control • Faster data transfers and new features • Backwards compatible with previous versions ©Arasan Chip Systems Inc. 2011
  • ONFI 3.0 FeaturesOperates memory devices at any frequencyup to 200 MHz • 200 MT/SDifferential signaling on clock and data linesDDR-2 Transfers • True and Complement Data Strobes • SDR, NV-DDR and NV-DDR2 ©Arasan Chip Systems Inc. 2011
  • ONFI 3.0 FeaturesSingle and Dual data bus discoveryEight chip enablesPage sizes up to 8KECC up to 64 bits • Dynamically configurable ECC widthWarm-up cycles for high-speed operationSupports all new commands ©Arasan Chip Systems Inc. 2011
  • Patented BCH CodingBCH Coded ECC supports dynamicallyscalable correction bitsParallel bit processing on the BCH encoderParallel syndrome generationInversion-less Berlekamp-Massey algorithmfor key equation solverParallel computation for the key equationsolverParallel Chien search algorithm ©Arasan Chip Systems Inc. 2011
  • NAND Flash Architecture©Arasan Chip Systems Inc. 2011
  • ONFI ComplianceCompliant to the 3.0 ONFI (rev. 2011)Only announced product in the market ©Arasan Chip Systems Inc. 2011
  • DeliverablesRMM (Reuse Methodology Manual)compliant VerilogConfigurable Behavioral modelsVerification Suite & Test CasesDocumentation and Design Support ©Arasan Chip Systems Inc. 2011
  • Total IP SolutionsFeatures • Analog and Digital cores, with no gaskets or wrappers for efficient, low-gate design • Software, Synthesis scripts and Test Environments • Verification IP, ESL models • HW Development Kits & Verification Platforms • Design Services ©Arasan Chip Systems Inc. 2011
  • Total IP SolutionsBenefits • Compliance across the standard • Single supplier – Single support • Guaranteed compatibility • Lowest overall cost and risk • Seamless integration from PHY to SW layers • Fastest cycle: MRD to SoC ©Arasan Chip Systems Inc. 2011