Design Automation Conference - IP Talks June 2011
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Design Automation Conference - IP Talks June 2011

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Overview of SD storage IP from Arasan Chip Systems, given at the Design Automation Conference (DAC 2011) San Diego, CA by Dennis McCarty

Overview of SD storage IP from Arasan Chip Systems, given at the Design Automation Conference (DAC 2011) San Diego, CA by Dennis McCarty

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    Design Automation Conference - IP Talks June 2011 Design Automation Conference - IP Talks June 2011 Presentation Transcript

    • Total Storage Solutions Dennis McCarty Arasan Chip Systems
      • Keeping up with Standards
      • Arasan Supported Standards
      • SD Flash Now and in the Future
      • SD 4.0 Improvements
      • ONFI Flash Overview
      • Universal Flash Storage
      • Deliverables
      • Arasan Total Solution
      • Total Solution Advantage
      Overview
    • IP Customers Need
      • IP products that adhere to evolving standards
      • Customers want custom versions that adapt to new standards
      • Users want timely support from design engineers who know the product
    • Arasan Standards Products
      • Membership and participation in standards bodies allows us ground floor view of changes and additions to new versions
      • Products roll out as soon as standard approved
      • Development engineers also support products
    • Arasan IP Memory Standards Coverage
      • SD / SDIO / MMC / CF / XD / Pro
      • ONFI NAND Flash
      • Universal Flash Storage
    • SD is Pervasive
      • SD is the most pervasive format for Flash
      • SD found in
        • Cameras
        • Video
        • Games
        • Mobile
        • Tablets
    • SD is Improving
      • SD growing at 15% annually
      • Capacities increasing as shown by the SDXC offering 32G to 2T
      • Speeds going to 104 MB/s
    • Growth of SD Standard
    • SD 4.0 Background
      • SD 4.0 most recent revision to the SD standard
      • Introduces the powerful UHS-II PHY for faster throughput
        • 1.56 GB/s/lane at 52MHz
        • 300 MB/s overall
      • Adds second row of pins for differential signaling
        • D0+/- and D1+/-
      • Bus clock 208 MHz
      • Capacity from 32GBy to 2TBy
    • SD 4.0 Controller Architecture
    • Arasan SD Compliance
      • Current to SD 4.0 (rev. April 2011)
      • Arasan 4.0 Device controller core available April 2011
      • Only announced product in the market
    • ONFI Background
      • ONFI Open NAND Flash Interface
        • NAND Flash Industry Consortium
      • Version 3.0
        • Latest specification for NAND Flash control
        • Faster data transfers and new features
        • Backwards compatible with previous versions
      • Operates memory devices at any frequency up to 200 MHz
        • 400 MT/S
      • Differential signaling on clock and data lines
      • DDR-2 Transfers
        • True and Complement Data Strobes
        • SDR, NV-DDR and NV-DDR2
      ONFI 3.0 Features
    • ONFI 3.0 Features
      • Single and Dual data bus discovery
      • Eight chip enables
      • Page sizes up to 8K
      • ECC up to 64 bits
        • Dynamically configurable ECC width
      • Warm-up cycles for high-speed operation
      • Supports all new commands
    • Patented BCH Coding
      • BCH Coded ECC supports dynamically scalable correction bits
      • Parallel bit processing on the BCH encoder
      • Parallel syndrome generation
      • Inversion-less Berlekamp-Massey algorithm for key equation solver
      • Parallel computation for the key equation solver
      • Parallel Chien search algorithm
    • ONFI Compliance
      • Compliant to the 3.0 ONFI (rev. 2011)
      • Arasan 3.0 core available July 2011
      • Only announced product in the market
    • ONFI NAND Flash Architecture CE_N(7:0) CLK- Data(15:0)+ Data(15:0)- CLK+
      • Originally part of Mobile Industry Processor Interface (MIPI) Alliance
      • Universal Flash Storage
        • Similar to SCSI, but with own command set
        • Large storage capacity
        • Simple, high-performance serial interface
      • 2.9Gbps max per lane, version 1.0
      • Multiple partitions on memory Logical Units (LU)
      UFS Features
    • UFS Architecture
    • Arasan IP Core Deliverables
      • RMM (Reuse Methodology Manual) compliant Verilog
      • Configurable Behavioral models
      • Verification Suite & Test Cases
      • Documentation and Design Support
        • User Guide
        • 24/7 phone and email support
        • Optional on-site support
    • Arasan Total Solution
      • A ‘Total IP Solution’ bundles everything you need to implement standards
        • RTL
        • Analog Mixed Signal
        • Verification IP
        • Software Drivers/Stacks
        • Protocol Analyzers
        • Hardware Development Kits
        • Technology Consulting
      • Total Solution Benefits
        • Cores, with no gaskets or wrappers for low-gate design
        • Compliance across the standard
        • Single supplier – Single support
        • Guaranteed compatibility
        • Lowest overall cost and risk
        • Seamless integration from PHY to SW layers
        • Fastest cycle: MRD to SoC
      Total Solution Benefits
    • Thank you
      • Explore Arasan Chip Systems IP at ChipEstimate.com
      • Use Arasan Chip Systems IP to plan your next product
      • Please stay and talk with Dennis McCarty