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Arasan Total IP Solution for Mobile Storage
- 1. Copyright © 2012, Arasan Chip Systems, Inc.Copyright © 2012, Arasan Chip Systems, Inc. Mobile Storage and Memory Total IP Solution Q3. 2013
- 2. Copyright © 2012, Arasan Chip Systems, Inc. 12/12/2012 Arasan Total IP Solution Total IP Solution RTL IPAnalog IP Software Stacks & Drivers Hardware Validation Platforms Verification IP Architecture Development & Customization
- 3. Copyright © 2012, Arasan Chip Systems, Inc. Strong Market Position Number of top ten semiconductor companies who are our customers Number MIPI Association Board Members who buy MIPI from us Sales rank of SD Association founding member who buys SD products from us Number of largest semiconductor companies on the UFSA Board who our UFS products
- 4. Copyright © 2012, Arasan Chip Systems, Inc. Standards Leadership and Partnerships Standards Participation Partner Community 12/12/2012
- 5. Copyright © 2012, Arasan Chip Systems, Inc. UFS 1.1/2.0 Key Features 12/12/2012 Core Logic Block UFSM-PHY HCI μP Core Host block diagram Device block diagram Reset Ref Clock Dout+/- Din+/- Din+/- Dout+/- Core Logic Block UFSM-PHY MemoryI/O Flash Memory
- 6. Copyright © 2012, Arasan Chip Systems, Inc. UFS-SCSI Command Set Layer (UCS) UFS Transport Protocol Layer (UTP) UFS InterConnect Layer (UIC) L4 = Transport L3 = Network L2 = Data Link L1.5 = Phy adapt L1 = M-PHY UniPro M-PHY UFS Controller IC Application SW & Stacks UFS Layered Architecture 12/12/2012 PHY
- 7. Copyright © 2012, Arasan Chip Systems, Inc. SD/SDIO/eMMC Host Controller 12/12/2012 Legacy SD Bus Interface New Serial Differential Interface SD 3.0/4.2, SDIO 3.0 , eMMC 4.51/5.0 Backward Compatible
- 8. Copyright © 2012, Arasan Chip Systems, Inc. Migration Path is Here 12/12/2012 Legacy Versions Newest Versions SD 3.0 Host SD 4.2 Host Multi-function Host SD3.0 / SDIO 3.0 / eMMC 4.41 Multi-function Host SD 4.1 / SD3.0 / SDIO 3.0 / eMMC 5.0 ONFI 2.3 NAND Controller ONFI 3.1 NAND Controller eMMC4.51 Device eMMC 5.0 UFS 1.1/2.0
- 9. Copyright © 2012, Arasan Chip Systems, Inc. Arasan’s Advantage 12/12/2012 • Total Solution Supplier • Silicon IP, Verification IP, Software Stacks and Drivers, Hardware Validation Platform • Migration Path is Here • SD / SDIO / MMC • SD 4.1, eMMC 5.0, ONFI 3.1, UFS1.1/2.0 • Continue Expanding Global Support • Japan, Europe, India, Korea, Taiwan, China, Vietnam, US
Editor's Notes
- UFS has very low pin count, as depicted in this slide. It has two wires for Tx, two wires for Rx, and reset and clock pin.For UFS controller implementation, you have UFS host and UFS device.On the host side, there is the physciallayer with UFS M-PHY. The core logic includes the UniPro functions. Connecting the core logic to the core processor is the HCI, host controller interface. HCI is also defined by JEDEC.On the device side, it has the same UFS M-PHY and similar core logic with the UniPro function. It also has the NAND flash memory controller with interface to NAND flash.Device side
- To maximize reusability, UFS adopted a layered architecture to include three major layers. At the physical layer, the interconnect layer connects electrically the UFS host and UFS device.Transport Layer is responsible for encapsulating the protocol into the appropriate frame structure for the interconnect layer.At the software application layer, the command set layer incorporate the SCSI standard as the baseline protocol for UFS specification.Let’s take a look of what UniPro does. UniPro stands for Universal Protocol defined by MIPI. UniPro has four layers, L1.5 the PHY adapter, L2 the data link layer, L3, the network layer, and L4, the transport layer.