Adc by anil kr yadav

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  • 1. Department of Electronics engineering School of Engineering and Technology Pondicherry University. Presented by:- ANIL KUMAR YADAV M.TECH(1ST YEAR) REG. NO- 13304025 1
  • 2. Contents 2
  • 3. An electronic integrated circuit which transforms a signal from analog (continuous) to digital (discrete) form. The basic principle of operation is to use the comparator principle to determine whether or not to turn on a particular bit of the binary number output 3
  • 4. Microprocessors can only perform complex processing on digitized signals. •When signals are in digital form they are less susceptible to the deleterious effects of additive noise. • ADC Provides a link between the analog world of transducers and the digital world of signal processing and data handling. 4
  • 5. 2 steps process • Sampling and Holding (S/H) •Quantizing and Encoding (Q/E) 5
  • 6. •The behavior of S/H is analogous to that of camera. its main function is “to capture picture” of the analog signal and hold its value until the adc can process the information. •Holding signal benefits the accuracy of the A/D Conversion •Minimum sampling rate should be at least twice the highest data frequency of the analog signal 6
  • 7. • Quantizing: Partitioning the reference signal range into a number of discrete quanta, then matching the input signal to the correct quantum. • Encoding: Assigning a unique digital code to each quantum, then allocating the digital code to the input signal. 7
  • 8. Speed: Rate of conversion of a single digital input to its analog equivalent. Conversion Rate Depends on clock speed of input signal Depends on settling time of converter 8
  • 9. 1. Ramp or stair case or Counter type A/D converter 2. Tracking A/D converter 3. Successive Approximation A/D Converter 4. Flash A/D Converter 5. Delta-Sigma A/D Converter 6. Dual Slope or integrating type A/D Converter 9
  • 10. Counter type  One of the simplest types of analog to digital converter is counter type ADC.  This type of converter uses some type of counter as part of its operation  Counter type contains the following elements:  Digital to analog converter  Some type of counting mechanism  Comparator  clock  The input signal of ADC is connected to the signal input of its internal comparator.  The ADC then systematically increases the voltage of the reference input of the comparator until the reference becomes larger than the signal.  And the comparator output goes to 0 10
  • 11. Operation of counter type Control Logic D A C Counter START Vin Comparator Digital Output clock 11
  • 12. Operation of counter type Control Logic D A C Counter START Vin Comparator Digital Output clock 12
  • 13. Continue  Ex: consider an input signal is 4.78 volts. The initial comparator’s input would be 2.5 volts  The comparator compares the two value then the result this is less than 4.78 then the next higher voltage (5.00 volts) is applied  The comparator compares the two value and says this is greater than 4.78 and switches 0  The digital output of the ADC is the number of times the ADC increase the voltage after starting at the initial 2.5 volts  This scheme is relatively simple , but as the number of ADC increases the time it takes to scan through all possible values lower than input will grow quickly 13
  • 14. The conversion time on the counter type is NOT fixed but depends on the actual value of the analogue input expressed as a fraction of the full scale. This can be expressed as :- where N is the number of bits and T is the time period of the clock pulse Example : A counter type ADC has the following parameters, N=8, Vref=5.1V and clock=1MHz. Find the digital word for an Vin of 4.36V and the conversion time taken to reach this value? solution Step size = 5.1v / 2^N = 5.1V / 256 = 0.0199=0.02 The number of steps = 4.36 / 0.02 = 218.1=219  (219)10 = 110110112 Conversion time = 219 x 1/1MHz = 219 x 1uS = 219 uS 14
  • 15. Features of counter type Use a clock to index the counter Use DAC to generate analog signal to compare against input Comparator is used to compare VIN and VDAC where VIN is the signal to be digitized The input to the DAC is from the counter 15
  • 16. Track & Hold Logic D A C Up/Down Counter Vin Comparator Digital Output clock Tracking ADC - similar to the counter type except it uses an up/down counter and can track a varying signal more quickly. 16
  • 17. Fundamental Components (For n bit Flash A/D) 2^n-1 Comparators 2^n Resistors Control Logic Flash adc is fastest in all adc because flash type adc is using combinational logic (not sequential logic ). Therefore ,clock is not required ,in case of flash type adc. If propagation delay time of combinational circuit is zero, then ideal conversion time of adc is zero. But practical conversion time is sum of all propagation delay of combinational circuit involve in flash type adc. 17
  • 18. A resistive voltage divider (see figure) can provide all the digital reference states required. There are eight reference values for the 3-bit converter. The analog signal is compared concurrently with each reference state; therefore a separate comparator is required for each comparison. Digital logic then combines the several comparator outputs to determine the appropriate binary code to present. The reference voltages are set to 0.5, 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, and 7.5 volts respectively. The comparator outputs are labeled correspondingly as 1, 2, 3, 4, 5, 6, and 7 respectively. 18
  • 19. Uses the 2^n resistors to form a ladder voltage divider, which divides the reference voltage into 2^n equal intervals. Uses the 2^n-1 comparators to determine in which of these 2^n voltage intervals the input voltage Vin lies. The Combinational logic then translates the information provided by the output of the comparators This ADC does not require a clock so the conversion time is essentially set by the settling time of the comparators and the propagation time of the combinational logic. 19
  • 20. Advantage Very Fast (Fastest) Very simple operational theory Speed is only limited by gate and comparator propagation delay Disadvantage Expensive  Prone to produce glitches in the output Each additional bit of resolution requires twice the comparators 20
  • 21. Main Components Resistors Capacitor  Comparators  Control Logic  DAC 21
  • 22. input is over sampled, and goes to integrator.  The integration is then compared to ground. Then o/p value of comparator passes through D Latch and produces a serial bit stream Output is a serial bit stream 1’s ,proportional to Vin With this arrangement the sigma-delta modulator automatically adjusts its output to ensure that the average error at the quantize output is zero. The integrator value is the sum of all past values of the error, so whenever there is a non-zero error value the integrator value just keeps building until the error is once again forced to zero. 22
  • 23. Advantage High Resolution No need for precision Components Disadvantage Slow due to oversampling Only good for low bandwidth 23
  • 24. Uses a n-bit DAC to compare DAC and original analog results. Uses Successive Approximation Register (SAR) supplies an approximate digital code to DAC of Vin. Comparison changes digital output to bring it closer to the input value. Uses Closed-Loop Feedback Conversion 24
  • 25. Process 1. MSB initialized as 1 2. Convert digital value to analog using DAC 3. Compares guess to analog input 4. Is Vin>VDAC • Set bit 1 • If no, bit is 0 and test next bit 25
  • 26. Advantage Capable of high speed and reliable Medium accuracy compared to other ADC Good tradeoff between speed and cost Capable of outputting the binary number in serial (one bit at a time) format. Disadvantage Higher resolution slower Speed limited to ~5Msps 26
  • 27. Example: Given data • in 10 bit ADC,Vin= 0.6 volts (from analog device),Vref=1 volts .Find the digital value of Vin? Solution N=2^n (N of possible states) N=1024 Vmax-Vmin/N = 1 Volt/1024 = 0.0009765625V of Vref (resolution) 27
  • 28. Continue……… MSB (bit 9) Divided Vref by 2 Compare Vref /2 with Vin If Vin >Vref /2 , turn MSB on (1) If Vin < Vref /2 , turn MSB off (0)  Vin =0.6V and V=0.5  Since Vin>V, MSB = 1 (on) 28
  • 29. Next Calculate MSB-1 (bit 8) Compare Vin=0.6 V to V=Vref/2 + Vref/4= 0.5+0.25 =0.75V Since 0.6<0.75, MSB is turned off.  Calculate MSB-2 (bit 7)  Go back to the last voltage that caused it to be turned on (Bit 9) and add it to Vref/8, and compare with Vin. Compare Vin with (0.5+Vref/8)=0.625 Since 0.6<0.625, MSB is turned off Continue……… 29
  • 30. Calculate the state of MSB-3 (bit 6) Go to the last bit that caused it to be turned on (in this case MSB-1) and add it to Vref/16, and compare it to Vin. Compare Vin to V= 0.5 + Vref/16= 0.5625 Since 0.6>0.5625, MSB-3=1 (turned on) Continue……… 30
  • 31. This process continues for all the remaining bits. Continue……… 31
  • 32. Fundamental components 1. integrator 2. Electronically Controlled Switches 3. Counter 4. Clock 5. Control Logic 6. Comparator 32
  • 33. How Does it Work At t<0, S1 is set to ground, S2 is closed, and counter=0. At t=0 a conversion begins and S2 is open, and S1 is set so the input to the integrator is Vin. S1 is held for Tint which is a constant predetermined time interval.  When S1 is set the counter begins to count clock pulses, the counter resets to zero after Tint Vout of integrator at t=Tint is Vin Tint/RC is linearly proportional to Vin. At t=Tint S1 is set at -Vref to the input of the integrator which has the voltage Vin Tint/RC stored in it. The integrator voltage then drops linearly with a slop -Vref/RC.  A compartor is used to determine when the output voltage of the integrator crosses zero When it is zero the digitized output value is the state of the counter. 33
  • 34. 34
  • 35. 35
  • 36. Advantage •Conversion result is insensitive to errors in the component values. • Fewer adverse affects from “noise” • High Accuracy Disadvantages •Slow • Accuracy is dependent on the use of precision external components • Cost 36
  • 37. 37 Resolution Dual-slope integrating, Counter Tracking successive approximation Flash. Speed Flash Tracking Successive Approximation Counter Dual-slope integrating. Comparison(best to worst)
  • 38. Example ADC question: • A 10-bit digital slope integrating A/D converter has a full-scale input of 10V. If the clock period is 15 μS, how long will it take to convert an input of 4V? How long for an input of 10V? 10 bits means 210 =1024 levels. Full scale input of 10V means each level is 10V/1024=9.77mV 4V corresponds to 4/9.77 10-3=409.6 - round up to 410 A clock period of 15μs mean 4V will take 15μs 410 =6.15ms 10V will take 15μs 1024=15.36ms 38
  • 39. Example ADC question: • A 10-bit digital slope integrating A/D converter has a full-scale input of 10V. If the clock period is 15 μS, how long will it take to convert an input of 4V? How long for an input of 10V? 10V will take 15μs 1024=15.36ms • What increase in speed can be gained by using a 12-bit successive approximation converter instead of the digital slope converter, assuming a full- scale input voltage.? • A 12-bit SA converter will take 12 clock cycles = 180 μs, regardless of the input voltage • so for 10V full scale input, the speed increase is 15.36ms/180 μs =85.3 times. • So the SA converter is both faster and more accurate (12 bits gives 4096 levels, compared to 1024 levels for 10 bit) 39
  • 40. Span (or Range): difference between maximum and minimum analog values. Span= maximum value – minimum value Some common spans: range of 0 V to 5 V: span = 5 V range of –12 V to 12 V: span = 24 V range of 4 mA to 20 mA: span = 16 mA Offset: minimum analog value Bit Weight: analog value corresponding to a bit in the digital number Step Size (or Resolution): smallest analog change resulting from changing one bit in the digital number, or the analog difference between two consecutive digital numbers. Let AV be Analog Value; DN be Digital Number: AV = DN Step Size + Offset = (DN / 2n ) Span + Offset DN = (AV - Offset) / Step Size = (AV - Offset) 2n / Span ADC Parameter Specification 40
  • 41. How closely can we approximate the desired output signal 41
  • 42. Example 1 o Full scale measurement range = 0 to 10 volts o ADC resolution is 12 bits = 4096 quantization levels (codes) o ADC voltage resolution is =(10V - 0V) / 4096 codes = 10V /4096 codes =0.00244 volts/code = 2.44 mV/code • Example 2 o Full scale measurement range = -10 to +10 volts o ADC resolution is 14 bits: =16384 quantization levels (codes) o ADC voltage resolution is: =(10V - (-10V)) / 16384 codes =20V / 16384 codes = 0.00122 volts/code = 1.22 mV/code 42
  • 43. Quantization error occur due to the finite resolution N of the A/D converter limits the signal- to-noise ratio. All inputs within ±1/2 LSB of a code center resolve to that digital code. Thus, there will be a small difference between the code center and the actual input voltage due to this quantization. Mathematically, Qe=Vin-Vstaircase, where Vstaircase=D VQ ,VQ => Quantam volatge level If assume that this error voltage is uncorrelated and distributed uniformly, we can calculate the expected rms value of this quantization noise.“ Quantum voltage level= expectation value of the error voltage = The rms value of a full-scale peak-to-peak amplitude VF is: thus the signal-to-noise ratio is = SNR= 6.02N + 1.76 dB Quantization Error and Quantization Noise 43
  • 44. Quantization error voltage for ideal analog-to-digital converter. 44
  • 45. Dynamic range : is the ratio of the smallest possible output (the least significant bit or quantum voltage) to the largest possible output (full-scale voltage). `Mathematically : DR =20 log10 2^N = 6N. Signal-to-noise-and-distortion ratio ( SNDR) : is the ratio of the input signal amplitude to the rms sum of all other spectral components. SNDR =S/N+D Spurious-free dynamic range (SFDR): is the ratio of the input signal to the peak spurious or peak harmonic component. Spurs can be created at harmonics of the input frequency due to nonlinear- ties in the A/D converter, or at sub harmonics of the sampling frequency due to mismatch or clock coupling in the circuit. The SFDR of an A/D converter can be larger than the SNDR. 45
  • 46. Total Harmonic Distortion: Total harmonic distortion (THD) is the ratio of the rms sum of the first 5 harmonic components to the input signal. where V1 is the amplitude of the fundamental, and Vn is the amplitude of the n-th harmonic. Aperture delay : Aperture delay is the delay from when the A/D converter is triggered (perhaps the rising edge of the sampling clock) to when it actually converts the input voltage into the appropriate digital code. Aperture delay is also sometimes called aperture time. Transient Response: Transient response is the settling time for the A/D converter to full accuracy (to within ±1/2 LSB) after a step in input voltage from zero to full scale Overvoltage Recovery: Overvoltage recovery is the settling time for the A/D converter to full accuracy after a step in input voltage from outside the full scale voltage (for example, from 1:5VF to 0:5VF ) 46
  • 47. Aperture Jitter: Aperture jitter is the sample-to-sample variation in the aperture delay. The rms voltage error caused by rms aperture jitter decreases the overall signal-to-noise ratio, and is a significant limiting factor in the performance of high-speed A/D converters. If we assume that the input waveform is a sinusoid ,then , VIN = VFS sin ᾡt then the maximum slope of the input waveform is: which occurs at the zero crossings. If there is an rms error in the time at which we sample (aperture jitter, ta) during this maximum slope. then ,there will be an rms voltage error of Since the aperture time variations are random these voltage errors will behave like a random Noise source. Thus the signal-to-jitter-noise ratio : Effects of aperture jitter. 47
  • 48. Accuracy Accuracy is the total error with which the A/D converter can convert a known voltage, including the effects of quantization error, gain error, offset error, and nonlinearities. There are two ways to best improve the accuracy of A/D conversion: • increasing the resolution which improves the accuracy in measuring the amplitude of the analog signal. •increasing the sampling rate which increases the maximum frequency that can be measured. 48
  • 49. Offset Error Offset error is the deviation in the A/D converter's behavior at zero. The first transition voltage should be 1/2 LSB above analog ground. Offset error is the deviation of the actual transition voltage from the ideal 1/2 LSB. Offset error is easily trimmed by calibration. Compare the location of the first transitions in Figures 1 and 2. Gain Error Gain error is the deviation in the slope of the line through the A/D converter's end points at zero and full scale from the ideal slope of 2^N/VFS codes-per-volt. Like offset error, gain error is easily corrected by calibration. Compare the slope of the dashed lines in Figures 1 and 2. 49
  • 50. Differential Nonlinearity Differential nonlinearity (DNL) is the deviation of the code transition widths from the ideal width of 1 LSB i.e. difference b/w the actual code width of nonideal converter and the ideal case. Mathematically, DNL=actual step width-ideal step width ideal step width=Vref/8=.625V=1 LSB All code widths in the ideal A/D converter are 1 LSB wide, so the DNL would be zero everywhere. Integral Nonlinearity Integral nonlinearity (INL) is the distance of the code centers in the A/D converter characteristic from the ideal line. If all code centers land on the ideal line, the INL is zero everywhere. See the deviations of the code centers from the ideal line in Figure . Missing Codes Missing codes are output digital codes that are not produced for any input voltage, usually due to large DNL. In some converters, missing codes can be caused by non-monotonicity of the internal D/A. The large DNL in Figure 3 causes code 100 to be “crowded out.” 50
  • 51. 51 Fig . ADC characteristic, showing nonlinearity errors and a missing code. The dashed line is the ideal characteristic, and the dotted line is the best fit.
  • 52. ADC are used virtually everywhere where an analog signal has to be processed, stored, or transported in digital form. •Some examples of ADC usage are digital volt meters, cell phone, thermocouples, and digital oscilloscope. •Microcontrollers commonly use 8, 10, 12, or 16 bit ADCs, our micro controller uses an 8 or 10 bit ADC. 52
  • 53. Conclusion • Adc is main component of all the modern digital electronics devices, there are different type of adc Ic’s available in market on the behalf of their requirement like speed , converter type etc. • There are so many application in the area of communication , automatic devices etc. • Hence we concluded that adc is the main element of digital devices. 53
  • 54. References • C-mos Circuit Design, layout and simulation- By R.Jacob baker, chapter no. 28,29. • Fundamentals of Digital Circuits By - A. Anand Kumar • LINEAR INTEGRATED CIRCUIT By: D. ROY CHOUDHARY • http://elearning.vtu.ac.in • http://web.mit.edu/klund/www/papers/ • http://www.freescale.com/files/microcontrollers/doc/app_note/AN2438.pdf 54
  • 55. 55 VERY MUCH………………………. …………………………………………….. …………………………………………….. ………
  • 56. 56 References