Design and Implementation of Bluetooth MAC core
with RFCOMM on FPGA
Sreekumari.B1 & Jiju.K2

ANEESH R
ER & DCI-IT
CDAC, Th...
Bluetooth supports two types of physical link: Synchronous
Connection Oriented (SCO) link and Asynchronous
Connection Less...
bluetooth is cut down into several blocks to achieve the
functionality.

Figure 6: Link Establishment-TX routine
In page s...
E. Packet Composer and TX_BUFFER
TX_BUFFER is used to store the data bits, which are
transmitted to the physical layer. It...
VI.

SIMULATION RESULTS

The Bluetooth MAC units with RFCOMM profile at the
upper layer are simulated using MODELSIM SE 6....
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Design and Implementation of Bluetooth MAC core with RFCOMM on FPGA

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The System-on-Chip (SoC) design of digital circuits makes the technology to be reusable. The current paper describes an aspect of design and implementation of IEEE 802.15.1 (Bluetooth) protocol on Field Programmable Gate Array (FPGA) based SoC. The Bluetooth is a wireless technology designed as a short-range connectivity solution for personal, portable and handheld electronic devices.
This design aims on Bluetooth technology with serial
communication (RS-232) profile at the application layer.
The IP core consists of Bluetooth Medium Access Control
(MAC) and Universal Asynchronous Receiver/Transmitter
(UART). Each module of the design is described and
developed with hardware description language-Very High
Speed Integrated Circuit Hardware Description Language
(VHDL). The final version of SoC is implemented and
tested with ALTERA STRATIX II EP2S15672C3 FPGA.

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Transcript of "Design and Implementation of Bluetooth MAC core with RFCOMM on FPGA"

  1. 1. Design and Implementation of Bluetooth MAC core with RFCOMM on FPGA Sreekumari.B1 & Jiju.K2 ANEESH R ER & DCI-IT CDAC, Thiruvananthapuram, India aneeshr2020@gmail.com Power Electronics Group CDAC, Thiruvananthapuram, India sreekumarib@cdac.in1 jijuk@cdac.in2 II. Abstract- The System-on-Chip (SoC) design of digital circuits makes the technology to be reusable. The current paper describes an aspect of design and implementation of IEEE 802.15.1 (Bluetooth) protocol on Field Programmable Gate Array (FPGA) based SoC. The Bluetooth is a wireless technology designed as a short-range connectivity solution for personal, portable and handheld electronic devices. This design aims on Bluetooth technology with serial communication (RS-232) profile at the application layer. The IP core consists of Bluetooth Medium Access Control (MAC) and Universal Asynchronous Receiver/Transmitter (UART). Each module of the design is described and developed with hardware description language-Very High Speed Integrated Circuit Hardware Description Language (VHDL). The final version of SoC is implemented and tested with ALTERA STRATIX II EP2S15672C3 FPGA. Keywords - IEEE 802.15.1, Bluetooth, MAC, SoC, FPGA, Serial Port Profile I. INTRODUCTION The IEEE 802.15.1 protocol is called Bluetooth. It is a short range (10-100m) radio technology, which is developed for Personal Area Network (PAN). Bluetooth is a standard developed by a group of electronic manufacturers that allows any sort of electronic equipment—from computers and cell phones to keyboard and headphones—to make its own connections, without wires, cables or any direct action from a user. It offers the possibility of ad hoc network and delivers the ultimate synchronicity between all personal devices. Figure 1 shows the Bluetooth module with a microcontroller to establish a serial communication link. The proposed design of Bluetooth IP core aims for transmitting and receiving data serially. So the upper layer of Bluetooth IP core uses a RS-232 standard to achieve a reliable serial communication. Figure 1: A serial communication link using Bluetooth IEEE 802.15.1 PROTOCOL The Bluetooth physical layer is operating at 2.4 GHz and has very low power consumption. It uses a frequency hopping spread spectrum. That is it changes its carrier frequency after every 625 us. There are two types of Bluetooth devices: Master and Slave. The unit is said to be master if it is an originator and arbitrator in a given piconet. The frequency hopping sequence is selected according to the master device. The slaves in the piconet must to be synchronized with the master’s clock. The Bluetooth system provides a point-to-point connection (one Master and one slave) and point to multipoint connection (one master and more than one slave).The network Bluetooth defines two types of network:-Piconet and Scatternet. In the piconet topology one master and up to seven slaves participate in the network. The scatternet consists of more than one master and slaves. One master in a network can be a slave in the other network. One or more piconet combines to form a scatternet. A channel in Bluetooth is represented by a pseudo random hopping sequence. The hopping sequence is unique for each Bluetooth units in a piconet and is derived from Bluetooth device address (BD_ADDR). A Bluetooth device hops 1600 times per second, which means that each device changes its modulating frequency 1600 times per second. The hopping sequences change its value regularly after 625 us. Bluetooth uses a form of Time Division Multiple Access (TDMA) that is called Time Division Duplex TDMA (TDDTDMA). TDD-TDMA is a kind of half duplex communication in which a Bluetooth device transmits and receives the data not at the same time. The channel is divided into time slots, each of 625 us in length. The master device may transmit in all even numbered time slots and a slave device in odd numbered time slots. Figure 2 shows the data transmission between a master and a slave. Figure 2: Master-Salve communication 978-1-4673-2272-0/12/$31.00 ©2012 IEEE 422
  2. 2. Bluetooth supports two types of physical link: Synchronous Connection Oriented (SCO) link and Asynchronous Connection Less (ACL) link. The SCO link is symmetric and point-to-point link between the master and a specific slave. The SCO link typically supports time bound information like voice. The ACL link is a point-to-multipoint link between the master and slaves participating in the piconet. III. reception operation between MAC and PHY. TX, RX pins represents the transmission and reception from PHY. The UC_TX and UC_RX signals provide the transmission and reception signals from the RFCOMM. PROTOCOL ARCHITECTURE Figure 3 represents the protocol architecture for an IEEE 802.15.1 system with RFCOMM at the application layer. The proposed protocol aims on transmitting and receiving the data from the Bluetooth device to upper layer or other devices by using a serial communication profile. Figure 3: Protocol stack with RFCOMM The Physical (PHY) layer is the first layer of the Bluetooth system. The basic functionality of the PHY layer is to receive a bit stream from the Medium Access Control (MAC) sublayer and transmitting the bit stream via radio waves to an associated station and vice versa through antenna. The Baseband layer is the heart of the Bluetooth system. It performs the link establishment and associated operations for an efficient data transmission and reception. The Link Manager layer controls and monitors the link between the two devices and performs the security in Bluetooth. The Logical Link Control and Adaptation (L2CAP) layer provides the protocol multiplexing, Packet composing and de-composing. The Radio Frequency Communication (RFCOMM) layer emulates the serial communication architecture. The Baseband, Link Manager and L2CAP layer are defined by IEEE, and together called MAC layer of the Bluetooth system. IV. IP CORE DESIGN A. Top Level Entity Figure 4 shows the top level entity of a Bluetooth with RFCOMM. In this, FH_SS is a pseudo random number given to PHY to perform the Frequency hopping spread spectrum technique. Also it provides a CLK_1MHz, a 1MHz clock signal to PHY for synchronizing the transmission and Figure 4: Top level entity-Bluetooth with RFCOMM B. Link Establishment Procedure Figure 5: Link Establishment in Bluetooth Figure 5 represents the link establishment between a master and slave Bluetooth device. There are two major states: STANDBY and CONNECTION; in addition there are seven sub-states, inquiry, inquiry scan, page, page scan, master response, slave response and inquiry response. The sub-states are used to add new slave to a piconet. To move from one state to another a command from the link manager or internal signals in the link controller are used. The STANDBY state is the default state in the Bluetooth system. The controller may leave the STANDBY state to scan for page or inquiry message, or to a page or inquiry itself. In a Bluetooth system, an inquiry procedure is used in applications where the destination’s device address is unknown to the source. C. Link Establishment- TX Routine Figure 6 shows the detailed link establishment procedure used in transmission procedure. In the TX Routine, device acts as a master. Initially all the Bluetooth devices will be in stand by state. From this, it moves to inquiry state to find any Bluetooth devices are available within range. If any bluetooth device is within range it will respond to inquiry scan state with its devices access code. After the successful completion of the inquiry procedure it moves to page state to confirm the link establishment. 423
  3. 3. bluetooth is cut down into several blocks to achieve the functionality. Figure 6: Link Establishment-TX routine In page state, it transmits the slave device access code and waits for response in page scan state. After the successful completion of the page procedure it enters into the master response state to transmit the FHS packet and wait for the salve device access code in page scan state. Once it is completed, it enters into the connection state to transmit the data. D. Link Establishment- RX Routine Figure 7 shows the detailed link establishment procedure in RX routine. In RX routine device act as slave. Initially all the Bluetooth devices will be in stand by state. From this it moves to inquiry scan state, to search any Bluetooth devices are within the range. If any device found then it moves to the inquiry state to transmit the slave device access code. After the successful completion of the inquiry procedure it moves to page state to confirm the link establishment. Figure 7: Link Establishment-RX routine In page scan state it receives its own device access code. Once it is found, it enters to the slave response state to transmit its own devices access code and again moves to page scan state to receive the FHS packet. Once it is received the FHS packet, it adjust the 28-bit counter from the FHS packet. Once it is adjusted it moves to the page state to transmit the slave device access code and enters into the connection state to receive the data. V. IP CORE IMPLEMENTATION Figure 8: IP core-Block Level Diagram Figure 8 shows the block level representation of IEEE 802.15.1 IP core with serial port (RS-232) profile at the application layer. The Medium Access Control layer of the A. Clock Generation Every Bluetooth unit has an internal system clock which determines the timing and hopping of the transceiver. The clock generation module in the MAC layer provides the appropriate clock signals such as 1µs, 312.5 µs, 625µs.This module contains a 28-bit register which increments on every change in 312.5µs clock. Also it provides the appropriate baud rates clock signal for the RFCOMM. B. TX_DATA_BUFFER and RX_DATA_BUFFER The TX_DATA_BUFFER of size 480 bit is used in the master mode operation. The Bluetooth device takes the data from the TX_DATA_BUFFER and transmits along with device access code. The RX_DATA_BUFFER is used during the salve mode operation. The MAC layer collects the received data from the PHY and performs several operations and collects the payload from the received packet and stores into the RX_DATA_BUFFER. C. Baseband Control The baseband control is the heart of the Bluetooth system. It co-ordinates the transmission and reception operations. This module creates, maintains and monitors the link. Inside this module a well designed link establishment state machine is running and this controls the activities of the Bluetooth system. D. Access Code Correlator and RX_BUFFER The RX_BUFFER of size of size 480 bit is used to receive the data bits from the physical layer. It receives the packet according to the state that it resides. The RX_BUFFER receives the packet according to the 1µs clock. The packet from the RX_BUFFER is given to the access code correlator. The access code correlator fist checks for the preamble (1010 or 0101), Device Access Code (DAC) and trailer (0101 or 1010). Once it has successfully received the preamble and DAC, it checks the header information. In header section it checks 1/3 FEC on header information, and if that matches then will decompose the header information. First it checks the TYPE of packet and AM_ADDR. If the TYPE of the packet is data, then payload section is decomposed to extract data from the packet, otherwise appropriate operations are performed based on the state that it resides. The payload mainly contains the payload header, data and Cyclic Redundancy Check (CRC). The payload is 2/3 FEC encoded. If a data packet is received it checks the payload header and finds the length of the data field. First it performs 2/3 FEC on received data, if it is success then checks the CRC. If all the checking is done successfully, it extracts the data from the data field according to the length in the payload header. The extracted data is stored in the RX_DATA_BUFFER. 424
  4. 4. E. Packet Composer and TX_BUFFER TX_BUFFER is used to store the data bits, which are transmitted to the physical layer. It transmits the packet according to the state that it resides. The TX_BUFFER transmits the packet according to the 1µs clock. The TX_BUFFER if filled from the packet composer. For a data transmission the packet composer first adds the preamble (1010 or 0101), Device Access Code (DAC), Trailer (0101 or 1010). Then it adds header and header error correction to make a total header of 18-bits. Before the transmission the header information is 1/3 FEC encoded. The payload mainly consists of payload header, payload body and CRC bits. The payload header contains the length of payload and Flow control. The payload body contains the data to be transmitted. The 16-bit CRC is calculated by using data payload. Total payload is 2/3 FEC encoded before transmission. Once the packet is formed then it is loaded into the TX_BUFFER, and transmitted using 1 µs clock. F. Link Manager Protocol The link manager protocol is used for link setup and control. The bluetooth system uses link manager protocol to setup, manage, and end RF communication. Link control involves monitoring the channel status, exchanging control information and processing link control commands. The link manager supports two kinds of communication:-Asynchronous Connection Less (ACL) and Synchronous Connection Oriented (SCO). The ACL transmission is used for data transmission and SCO transmission is used for audio/video transmission. The link manager protocol messages are having higher priority than data. G. Logical Link Control and Adaptation Protocol (L2CAP) L2CAP protocol supports higher level protocol multiplexing, packet segmentation and reassembly, and conveys the Quality of Service (QoS) information. The L2CAP protocol is used to multiplex multiple logical channels on a single physical link. To identify which logical channel the packet belongs to, a connection identifier (CID) is included with each L2CAP packet. L2CAP reserves at least one logical channel as a control channel to setup and manage the logical connections. Figure 9: Internal diagram-Frequency hopping module Figure 9 represents the Frequency hopping module for a 79 hop system. The primary function of the module is to generate a pseudo random hopping sequence. The output from the frequency hopping module is given to the physical layer. I. Radio Frequency COMMunication (RFCOMM) RFCOMM is a simple transport protocol, which provides emulation of RS232 serial ports over the L2CAP protocol. The RFCOMM protocol supports up to 60 simultaneous connections between two BT devices. Serial port transmits and receives data lines are connected to a UART. The function of UART is to convert serial data to parallel data and vice versa. Figure 10 shows the internal diagram of UART. It mainly consists of Transmitter, Receiver, Baud rate generator and a Control mechanism. The Baud rate generator is used to generate different clock signals according to the baud rate register. The UART transmitter accepts the parallel data from the DATA_IN pin and transmits serially through TXD pin. The UART receiver receives the serial data through RXD pin and converts to parallel data which is available in DATA_OUT pin. A control mechanism is used for controlling the transmission and reception. The module is enabled only when a high pulse is applied to ENABLE pin. H. Frequency Hopping Module The Frequency hopping is a method of transmitting radio signals by rapidly switching a carrier among many frequency communication channels using a pseudo random number known to both transmitter and receiver. The inputs to the frequency hopping module are from based band control module. Figure 10: Internal diagram-UART 425
  5. 5. VI. SIMULATION RESULTS The Bluetooth MAC units with RFCOMM profile at the upper layer are simulated using MODELSIM SE 6.4. Figure 11, 12, 13 shows the simulation result of Frequency hopping module, TX routine and a RX routine. Figure 15: Internal Hardware-Frequency Hopping Module Figure 11: Simulation-Frequency Hopping Figure 16: Internal Hardware –connection Establishment unit VII. CONCLUSION Figure 12: Simulation-TX Routine The main objective of this work is to design and develop a System-on-Chip module with a Bluetooth IP core customized for Bio-Medical equipment, which is successfully implemented. The SoC is ported in an ALTERA STRATIX II EP2S15672C3 FPGA for testing and is functioning well. The logic utilization is shown in Table1. The minimum data rate of the system is 108.8 kbps. As a Bluetooth SPP device this IP core can be also used for other embedded applications. Figure 13: Simulation-RX Routine Table 1: Device Utilization REFERENCES [1] [2] [3] [4] [5] Figure 14: RTL View from Altera Quartus II Bluetooth, “Specification of Bluetooth System”. November 2003, Version 1.2. Shu Lin, Daniel J. Costello, “Error Control Coding: Fundamentals Applications” ”, ISBN – 0-13-283796-X, 198 K. Elissa, Hall, T.S., Hamblen, J.O., "System-on-a-programmable-chip development platforms in the classroom", Education, IEEE Transactions on, On page(s): 502 - 507, Volume: 47 Issue: 4, Nov. 2004. S.AL-Ashari,” System Verification from the Ground Up” Integrated Systems Design, 1999 Charles H. Roth, Jr. Digital System Design by using VHDL, PWS Publishing Company, 1998. 426

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