Integrated Software-Defined Radio (SDR) - VE2013

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This session combines the high speed analog signal chain from RF to baseband with FPGA-based digital signal processing for wireless communications. Topics include the high speed analog signal chain, direct conversion radio architecture, the high speed data converter interface, and FPGA-based digital signal processing for software-defined radio. The demo board uses the latest generation of Analog Devices’ high speed data converters, RF, and clocking devices, along with the Xilinx Zynq-7000 SoC. Other topics of discussion include the imperfections introduced by the modulator/demodulator with particular focus on the effect of temperature and frequency changes. In-factory and in-field algorithms that reduce the effect of these imperfections, with particular emphasis on the efficacy of in-factory set-and-forget algorithms, are examined.

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Integrated Software-Defined Radio (SDR) - VE2013

  1. 1. Integrated Software Defined Radio Reference Designs and Systems Applications Robin Getz, Title, Location
  2. 2. Legal Disclaimer  Notice of proprietary information, Disclaimers and Exclusions Of Warranties The ADI Presentation is the property of ADI. All copyright, trademark, and other intellectual property and proprietary rights in the ADI Presentation and in the software, text, graphics, design elements, audio and all other materials originated or used by ADI herein (the "ADI Information") are reserved to ADI and its licensors. The ADI Information may not be reproduced, published, adapted, modified, displayed, distributed or sold in any manner, in any form or media, without the prior written permission of ADI. THE ADI INFORMATION AND THE ADI PRESENTATION ARE PROVIDED "AS IS". WHILE ADI INTENDS THE ADI INFORMATION AND THE ADI PRESENTATION TO BE ACCURATE, NO WARRANTIES OF ANY KIND ARE MADE WITH RESPECT TO THE ADI PRESENTATION AND THE ADI INFORMATION, INCLUDING WITHOUT LIMITATION ANY WARRANTIES OF ACCURACY OR COMPLETENESS. TYPOGRAPHICAL ERRORS AND OTHER INACCURACIES OR MISTAKES ARE POSSIBLE. ADI DOES NOT WARRANT THAT THE ADI INFORMATION AND THE ADI PRESENTATION WILL MEET YOUR REQUIREMENTS, WILL BE ACCURATE, OR WILL BE UNINTERRUPTED OR ERROR FREE. ADI EXPRESSLY EXCLUDES AND DISCLAIMS ALL EXPRESS AND IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. ADI SHALL NOT BE RESPONSIBLE FOR ANY DAMAGE OR LOSS OF ANY KIND ARISING OUT OF OR RELATED TO YOUR USE OF THE ADI INFORMATION AND THE ADI PRESENTATION, INCLUDING WITHOUT LIMITATION DATA LOSS OR CORRUPTION, COMPUTER VIRUSES, ERRORS, OMISSIONS, INTERRUPTIONS, DEFECTS OR OTHER FAILURES, REGARDLESS OF WHETHER SUCH LIABILITY IS BASED IN TORT, CONTRACT OR OTHERWISE. USE OF ANY THIRD-PARTY SOFTWARE REFERENCED WILL BE GOVERNED BY THE APPLICABLE LICENSE AGREEMENT, IF ANY, WITH SUCH THIRD PARTY. 2
  3. 3. Today’s Agenda Software Defined Radio (SDR) Overview Math Behind SDR  Zero-IF or direct-conversion transmitter/receiver  Brief introduction to digital modulation How to Solve Channel Impairments  Imperfections introduced by the modulator/demodulator with particular focus on the effect of temperature and frequency changes  In-factory and in-field algorithms will be examined that can reduce the effect of these imperfections, and particular focus is placed on the efficacy of in-factory set-and-forget algorithms Solutions for SDR  FMComms1 board  Tools, drivers, and example HDL designs 3
  4. 4. What Is a Software Defined Radio? A software defined radio system (SDR) is a radio communication system where components that have been typically implemented in hardware (e.g., mixers, filters, amplifiers, modulators/demodulators, detectors) are instead implemented by means of software on a personal computer or embedded system. While the concept of SDR is not new (circa ~1970 DoD labs), many techniques which used to be only theoretically possible are now being implemented due to the rapidly evolving capabilities of analog and digital electronics.  Why SDR?  Makes RF hardware easier  Easy to add new features, since they are all in software  Easier to have one set of hardware handle multiple modulation techniques 4
  5. 5. Direct Conversion Technique (FMComms1) 5 Clock Generator / Sync Clock Distribution Frequency Synthesizer ADL5375 ADL5602 ADL5380AD8366AD9643 AD9548 AD9523-1 ADF4351 LPC(32Data+3CLKLVDS)FMCConnector(500MHz) FPGADevelopmentPlatform RF Out RF In` Slave Clock In Sync In DAC 16-Bit 1250MSPS* AD9122 Modulator 400 – 6000MHz 20dB Fixed Gain 50 – 4000MHz ADC 14-Bit 250MSPS 0.25dB Step Size 600MHz Bandwidth Demodulator 400 – 6000MHz Output: 1 – 1000MHzInput: 1 – 750MHz Output: 35 – 4400MHz ADL5605/6 700 - 1000MHz 1800 – 2700MHz π π Frequency Synthesizer Master Clock Out 16 + 1 LVDS Pair @ 1000 Mbps 500MHz (DDR) 16 + 1 LVDS Pair @ 500 Mbps 250MHz DDR π Pi network Solder bump jumperS S S S S 1 LVDS Pair 50MHz Ref Clock SMA connector I2C / USB to SPI SPI SPI SPI SPI SPI SPI SPI Power 5V @ 500mA ADL5523 400MHz to 4000MHz Low Noise Amplifier Tuned for Frequency π Tx Rx RF output power control is accomplished by adjusting baseband data Optional Front End Optional Front end 2 2 -9dB 0dB0dB Non-SMA connector • AD9122 DAC runs at 1000MSPS, due to max speed of AD9523-1
  6. 6. Direct Conversion (Zero-IF) TRx A direct-conversion transceiver, also known as homodyne, synchrodyne, or zero-IF transceiver, is a radio transceiver design that (de)modulates the radio signal using a local oscillator (LO) whose frequency is identical to, or very close to, the carrier frequency of the intended signal.  Carrier frequency = local oscillator (LO) frequency  Attractive due to simplicity of the signal path  Suitable for high levels of integration  Allows wider bandwidth designs 6
  7. 7. Homodyne Transmitter Advantages and Challenges Advantages:  Low component count leads to lower system cost and power consumption  Direct up-conversion produces less mixing product spurs  Requires fewer filters Challenges:  During the analog modulation process, gain and phase mismatches of IQ signals have a direct impact on sideband suppression performance  Out of band transmissions  LO / carrier leakage  I/Q mismatch causes image in the output spectrum • This results in degraded error vector magnitude (EVM) at the receiver, which in turn degrades the bit error rate (BER) 7
  8. 8. Homodyne Receiver Advantages and Challenges Advantages:  Low component count leads to lower system cost  No image reject filter needed  Filtering requirements more relaxed at baseband  Gain stages at baseband provide power savings Challenges:  DC offset appearing at baseband  Self mixing  Offset voltages  Images appearing symmetrically about zero frequency  I/Q mismatches in phase and amplitude  Even order nonlinearities  Two high frequency interferers close to the channel of interest can result in even order nonlinearities that fall within the band of interest 8
  9. 9. Back to Basics: Euler’s Formulas Sin ω0t is 90° out of phase with respect to cos ω0t  With perfect amplitude and phase matching the signal content at - ω0 cancels 9
  10. 10. Amplitude and Phase Mismatch Amplitude Mismatch Phase Mismatch ω0 −ω0 A+B 2 A-B 2 Desired Signal Image 10
  11. 11. Error Vector Magnitude—EVM ∑ ∑ = = − = M k M k kR kRkZ EVM 1 2 1 2 )( )()( 11  Noise and Imperfections in transmit and receive signal chains result in demodulated voltages which are displaced from their ideal location.  Error Vector Magnitude expresses this dislocation  Large EVM will result in Symbol Errors and degraded Bit Error Rate  Higher Order Modulation Schemes → Symbols Closer Together → EVM More Critical Ideal (Reference) Signal Phase Error (I/Q Error Phase) Magnitude Error (I/Q Error Mag) I Q Actual Signal φ Unit = %
  12. 12. Effects of Gain, Offset, and Phase Errors -1.5 -1 -0.5 0 0.5 1 1.5 -1.5 -1 -0.5 0 0.5 1 1.5 -1.5 -1 -0.5 0 0.5 1 1.5 -1.5 -1 -0.5 0 0.5 1 1.5 -1.5 -1 -0.5 0 0.5 1 1.5 -1.5 -1 -0.5 0 0.5 1 1.5 fLO +10% Quadrature Gain Error fLO 1o Quadrature Phase Error fLO +1% Quadrature Offset Error 12
  13. 13. Symbol Decision Threshold If the symbol lands on the edge or outside of the box, bit errors will occur
  14. 14. Effects of I/Q Mismatch f1f0 f2-f0-f1-f2 0 Desired Signal Ideal Gain Error IdealPhase Error ** EVM Degradation ** ** Images Occupy BW ** ** Interfere with Desired Signal ** 14
  15. 15. Direct Conversion Transmitter Architecture 15 ADL5375 ADL5602 RF Out DAC 16-Bit 1250MSPS* AD9122 Modulator 400 – 6000MHz 20dB Fixed Gain 50 – 4000MHz ADL5605/ADL5606 700 – 1000MHz 1800 – 2700MHz π π 16 + 1 LVDS Pair @ 1000 Mbps 500MHz (DDR) SPI 0dB0dB
  16. 16. Complex IF Using IF DACs A complex IF architecture uses IF DACs to synthesize an IF signal and its complex conjugate as the inputs to a quadrature modulator This makes a single sideband (SSB) upconverter that rejects the normal mixing product, easing the BPF filtering requirements 16 IF DAC IF DAC PA BPFΣ BPF RF RFIF IF RF RF 0 LO 90 LOFs Fs
  17. 17. Complex IF Imperfections  Complex IF systems create several images:  FDAC – FOUT: the main desired signal’s image  Harmonics (2nd, 3rd, etc.), real or folded  These must be low pass filtered prior to the quadrature modulator  Careful frequency planning must be done to avoid folded products falling too close to the desired signal that are then upconverted  Post-modulator, a band pass filter is used to filter the undesired products 17 IF DAC IF DAC Σ IF RF 0 LO 90 Fs IF Fs RFLO image harmonic
  18. 18. Causes of Non-Ideal Sideband Suppressions 18
  19. 19. Fixes for Non-Ideal Issues 19 MULTICHIP SYNCHRONIZATION D15P/D15N D0P/D0N DATA RECEIVER FIFO HB1 HB2 HB3 NCO AND MOD fDATA/2 PRE MOD HB1_CLK MODE HB2_CLK HB3_CLK INTP FACTOR PHASE CORRECTION INTERNAL CLOCK TIMING AND CONTROL LOGIC 16 16 10 16 16 I OFFSET Q OFFSET INV SINC AUX 1.2G DAC 1 16-BIT IOUT1P IOUT1N AUX 1.2G DAC 2 16-BIT IOUT2P IOUT2N REF AND BIAS FSADJ DACCLKP DACCLKN REFCLKP REFCLKN REFIO10 GAIN1 10 GAIN2 DAC_CLK SERIAL INPUT/OUTPUT PORT PROGRAMMING REGISTERS POWER-ON RESET SDO SDIO SCLK CS RESET IRQ 0 1 CLOCK MULTIPLIER (2× TO 16×) CLK RCVR CLK RCVR PLL CONTROL SYNC DAC CLK_SEL DAC_CLK PLL_LOCK DCI FRAME 08281-002 INVSINC_CLK AD9122 Block Diagram
  20. 20. Fixes for Non-Ideal Issues 20 Wanted Signal Unwanted Image LO Feedthrough
  21. 21. AD9122 Functional Block Diagram 21 MULTICHIP SYNCHRONIZATION D15P/D15N D0P/D0N DATA RECEIVER FIFO HB1 HB2 HB3 NCO AND MOD fDATA/2 PRE MOD HB1_CLK MODE HB2_CLK HB3_CLK INTP FACTOR PHASE CORRECTION INTERNAL CLOCK TIMING AND CONTROL LOGIC 16 16 10 16 16 I OFFSET Q OFFSET INV SINC AUX 1.2G DAC 1 16-BIT IOUT1P IOUT1N AUX 1.2G DAC 2 16-BIT IOUT2P IOUT2N REF AND BIAS FSADJ DACCLKP DACCLKN REFCLKP REFCLKN REFIO10 GAIN1 10 GAIN2 DAC_CLK SERIAL INPUT/OUTPUT PORT PROGRAMMING REGISTERS POWER-ON RESET SDO SDIO SCLK CS RESET IRQ 0 1 CLOCK MULTIPLIER (2× TO 16×) CLK RCVR CLK RCVR PLL CONTROL SYNC DAC CLK_SEL DAC_CLK PLL_LOCK DCI FRAME 08281-002 INVSINC_CLK
  22. 22. Premod/Filters/NCO 22 Increasing Interpolation Factor:  Decreases fDATA,  Decreases signal bandwidth  Increases power of DAC, decreases power of FPGA
  23. 23. Digital Inside DAC Increasing interpolation factor:  Decreases fDATA  Decreases signal bandwidth  Increases power of DAC  Decreases power of FPGA Trade off system level performance between FPGA processing and fixed processing Decreased system timing constraints on FPGA 23
  24. 24. AD9122 Interpolation at a DAC Output 24 1X 2X 4X
  25. 25. AD9122 Digital Up-Conversion, DAC Out (DC -> 600 MHz) 25 No upconversion f(DATA)/2 upconversion 8 x f(DATA)/7 upconversion
  26. 26. AD9122 Digital Up-Conversion at RF (Centre @ 2.4 GHz) 26 No upconversion f(DATA)/2 upconversion 8 x f(DATA)/7 upconversion
  27. 27. When is This Useful? No “cans” on top of Tx or Rx chains to isolate them Any interaction between Tx and Rx PLLs will “bleed into the other” when the frequencies are within 100 kHz (due to PCB size constraints) 27 Clock Distribution Frequency Synthesizer ADL5375 ADL5380 AD9523-1 ADF4351 Modulator 400 MHz to 6000 MHz Demodulator 400 – 6000MHz Output: 1 – 1000MHz Output: 35 – 4400MHz Frequency Synthesizer Master Clock Out SPI SPI SPI Figure A Rx and Tx PLL 50 kHz different Figure B Rx and Tx PLL 100 MHz different (RF is the same due to the DAC shift) ADF4351 Tx Synthesizer 35 MHz to 4400 MHz ADF4351 Rx Synthesizer 35 MHz to 4400 MHz
  28. 28. Receive Architectures Direct (Zero-IF) Conversion Cos(ωRF) Cos(ωRF)=1+Sin2(ωRF) Cos(ωSIG) Cos(ωSIG)=1+Sin2(ωSIG) LNA(t)=α1x(t)+α2x2(t) input(t)=A1Cos(ω1t)+A2Cos(ω2t) feedthrough(t)=α2A1A2Cos(ω2-ω1)t ADL5380AD8366AD9643 RF In` ADC 14-Bit 250MSPS 0.25dB Step Size 600MHz Bandwidth Demodulator 400MHZ to 6000MHz 16 + 1 LVDS Pair @ 500 Mbps 250MHz DDR SPI SPI ADL5523 400MHz to 4000MHz Low Noise Amplifier Tuned for Frequency π Rx -9dB 28
  29. 29. The Imperfect I/Q Demodulator I/Q DEMODULATOR LOIN RFIN 0 89.5 G1 G4 G3 G2 fVo s1 V fo s2 IIN QIN Imbalance In Phase Splitter Gain Imbalance (G1,G2,G3,G4) Offset Voltages 29
  30. 30. Imperfections in the I/Q Signal Path Control Tuning90 0 R +/- 5% R +/- 5% LPF LPF Voffset1 Voffset2 Voffset3 Voffset4 ADC ADC Offsets within the Dual Channel ADC PCB and Layout Mismatches Component Mismatches 30
  31. 31. Critical IQ Demodulator Specs—LO to RF Leakage If some of the LO leaks to the RF input, it mixes (multiplies) with itself in the mixer, generating unwanted dc offsets on top of the recovered baseband data stream ADCLNA ω Desired -70dBm 0dBm Leakage -60dBm ω -40dBm -30dBm(~20mVp-p) A B C Assume, Gain from A to C =30dB LO to RF leakage ~ 60dB FLO FLO X 31
  32. 32. DC Offset and Quadrature Error Correction DC offset and quadrature error correction implemented digitally at the end of the receive chain  Most efficient approach in order to compensate for all potential mismatches or errors in the signal path DC Correction  If DC free coding is used, a notch filter can be applied Quadrature Error Correction  Gain Correction  Calculate I^2 – Q^2 to determine the power difference between I and Q.  The power difference should be driven to zero.  Phase Correction  Perform a cross-multiply between I and Q.  Can be viewed as a mixer. The DC term is proportional to the phase difference between I and Q.  By definition this should be zero if they are perfectly orthogonal. 32
  33. 33. Summary Direct conversion or homodyne receivers have there own merits and challenges Gain, phase, and offset errors are a few of the challenges that can be addressed with quadrature error correction algorithms  Gain, phase, and offset errors cause degradations in receiver EVM and sensitivity  Quadrature error correction will improve EVM and sensitivity Direct conversion offers advantages in power, cost, and performance over IF sampling architectures Quadrature error correction enables realizable direct conversion solutions for macro level base stations/SDR platforms Analog Devices’ first generation of QEC is available integrated into the following products  AD9262 – dual 16b continuous time sigma delta ADC  AD9269 – dual 16b pipeline ADC 33
  34. 34. Clocking AD9523-1: multi-output, clock distribution function with low jitter performance, On-chip PLL and VCO with two VCO dividers On-chip VCO Two cascaded PLL stages:  First stage, PLL1, consists of an integer division PLL that uses an external voltage-controlled crystal oscillator (VCXO) from 15 MHz to 250 MHz.  Second stage, PLL2, is a frequency multiplying PLL that translates the first stage output frequency to a range of 2.940 GHz to 3.125 GHz. Clock Generator / Sync Clock Distribution AD9548 AD9523-1 Output: 1 – 1000MHzInput: 1 Hz - 750MHz 50MHz Ref Clock SPI SPI 122.88MHz VCXO On FMCOMMS1 34
  35. 35. FMComms1 Clocking DAC_DCO ADC_CLK DAC_REFCLK DAC_CLK N/C N/C N/C N/C LOGEN_TX_REFIN ADC_SYNC N/C LOGEN_RX_REFIN N/C Assumes DAC is doing no interpolation OUT1 or OUT2 OUT1 only 35
  36. 36. PLL2 Configuration 122.88MHz 983.04MHz 983.04MHz 122.88MHz 1024.00MHz 1024.00MHz  Current config:  122.88 MHz / 1 * 24 = 2949.12 MHz  2949.12 MHz / 3 = 983.04 MHz  983.04 MHz / 4 = 245.76 MSPS (ADC)  Possible config:  122.88 MHz / 1 * 25 = 3072.00 MHz  3072.00 MHz / 3 = 1024.00 MHz  1024.00 MHz / 5 = 204.8 MSPS (ADC)  1024.00 MHz / 8 = 128.0 MSPS (ADC)  Possible config (max ADC rate):  122.88 MHz / 10 * 244 = 2998.272 MHz  2998.272 MHz / 3 = 999.4240 MHz  999.4240 MHz / 4 = 249.856 MSPS (ADC) 36
  37. 37. Possible FMComms1 Clocking 37 DAC_DCO ADC_CLK DAC_REFCLK DAC_CLK N/C N/C N/C N/C LOGEN_TX_REFIN ADC_SYNC N/C LOGEN_RX_REFIN N/C N/C Assumes DAC is doing 8x interpolation Can be 1024/n: • 204.80 MHz • 170.67 MHz • 146.29 MHz • 128.00 MHz • 113.78 MHz • 102.40 MHz • 93.09 MHz • 85.33 MHz • 78.77 MHz • 73.14 MHz • 68.67 MHz • 64.00 MHz • 60.23 MHz • 56.89 MHz • 53.89 MHz • 51.20 MHz • 48.76 MHz • 46.55 MHz • 44.52 MHz • 42.67 MHz • 40.96 MHz Loose Zero Delay, and no long can sync multiple cards together OUT1 or OUT2 OUT1 only
  38. 38. Power FMC provides 12 V, and 3.3 V Switchers  ADP2323 LDOs  ADP3335  ADP3333  ADP151  ADP150  ADP1740 38
  39. 39. ADP2323: Ultrahigh Conversion Efficiency in Compact Solution Size  Compact dual output solution size: 24 mm x 21 mm  Heat dissipation is spread evenly with the use of external low-side Mosfet 39  Ultrahigh and flat efficiency ~95% with a 12 V input and a 5 V output at 3 A load (ADP2323)  Optional pulse frequency modulation (PFM) reduces the switching losses at light load condition  Possible configuration up to 6 output rails in evenly phase-shifted topology to reduce input ripple voltage/current and minimize input capacitor size 24mm 21mm 50 55 60 65 70 75 80 85 90 95 100 0 0.5 1 1.5 2 2.5 3 Efficiency[%] OutputCurrent [A] Efficiency at 12Vin, 300kHz Vout=5V Vout=1.2V Vin A1 A2 ADP2323 (A) INTVCC SCFG SYNC SCFG SYNC SCFG 100kΩ180kΩ Vin B1 B2 ADP2323 (B) SCFG SYNC SCFG SYNC Vin C1 C2 ADP2323 (C) SCFG SYNC ADP2323
  40. 40. ADP2323: Configurability for Multi-Rail Applications 40  Reduces input ripple voltage/current and size of the input capacitor through phase shift. Avoids beat frequency interference in multi-rail applications  Two/three ADP2323’s can be used for four/six output rails configuration Connect SCFG to INTVCC for clock output Connect SCFG with 100/180kΩ resistor to GND for 60/120° phase shift Vin A1 A2 ADP2323 (A) INTVCC SCFG SYNC SCFG SYNC SCFG 100kΩ180kΩ Vin B1 B2 ADP2323 (B) SCFG SYNC SCFG SYNC Vin C1 C2 ADP2323 (C) SCFG SYNC A1 B1 C1 60° 120 ° Without Phase Shift, Input Voltage Ripple = 142mV With Phase Shift, Input Voltage Ripple = 86mV Up to 40% input voltage ripple reduction Input Voltage Ripple Comparison with/without phase shift
  41. 41. New ADI Low Noise High PSRR LDOs Summary ADM7160 (ES)  Target power for >14B ADC  200 mA, 1.8, 2.5, 3.3 Vout  9 µV rms broadband noise  Low tempco ADP7182 Neg VOUT LDO (ES)  200 mA, –30 Vin  Adjustable from –1.22 V to –VIN  PSRR 60 dB @10 kHz at VO = –3.3 V ADP150 ADP151 (MP)  150 mA/200 mA, 5.5 Vin  9 µV rms broadband noise  20 nV/√Hz spectral eN @ 100 kHz  70 dB PSRR @ 10 kHz 41 ADP7102 ADP7104 (MP)  300 mA/500 mA, 20 Vin  15 µV rms broadband noise  35 nV/√Hz spectral eN @ 100 kHz  80 dB PSRR @ 10 kHz  Power good output ADM7150 (1st Si) RF LDO (ES)  1.5 nV/√Hz spectral noise @ 100 kHz  800 mA, 4.5 to 16 Vin  Vout Range: 1.5 V to 5.5 V  100 dB PSRR DC to 100 kHz  65 dB PSRR at 1 MHz  40 dB at 10 MHz MP Mass Production ES Engineering Samples, contact ADI
  42. 42. ADP7102/ADP7104 – Low Noise Performance  ADP7102/ADP7104  The ADP7104 noise does not increase with output voltage  No noise bypass required  ~15 µV rms for all outputs 42 0.01 0.1 1 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 uV/rt-Hz Freq (Hz) Noise Spectral Density 3.3V 5V RELEASED  ADP7102/ADP7104  No added bypass capacitor required  Stable with 1 µF output capacitor  PSRR = 70 dB @ 1 kHz, 500 mA  PSRR = 58 dB @ 10 kHz, 500 mA  PSRR = 50 dB @ 100 kHz, 500 mA  PSRR = 35 dB @ 1 MHz, 500 mA
  43. 43. Spectral Density Noise Performance vs. Frequency The ADP151 1/f noise superior to competition below 100 Hz Competition noise somewhat better than ADP151 above 100 Hz 43 0.001 0.01 0.1 1 10 10 100 1000 10000 100000 Noise Spectral Density 4.5V HMC860LP3E 3.3V HMC860LP3E ADP151-3.3V HMC976LP3E
  44. 44. ADP151’s Ultralow Noise Advantage When Powering the ADF4350 Integrated PLL/VCO Chip Next slide compares phase noise vs frequency when powered by ADP151, AA batteries, & the older generation ADP3334 LDO  The ADP151 offers 1/3 the output noise of the ADP3334 LDO RMS jitter is also improved  Reduces from 1.23 ps to 0.87 ps by using ADP151 vs. the ADP3334 ADP151 output noise 10 µV rms over 10 Hz to 100 kHz independent of Vout, no CNR required ADP151 reduces PLL output phase noise (equivalent to reduced timing jitter) 44 RELEASED
  45. 45. PLL Phase Noise (at 4.4 GHz) vs. Frequency Offset 45 -120 -110 -100 -90 -80 -70 -60 1,000 10,000 100,000 1,000,000 USB 1 x ADP3334 SUPPLY 1 x ADP3334 SUPPLY 1 x ADP150 AA BATTERY (2 x 1.5V) PhaseNoise(dBc/Hz) Hz ADP151 Low Noise LDO and 2 x AA Battery ADP3334 LDO
  46. 46. Traditional RF Evaluation Platforms (Antenna to Bits) 46  Discrete single product evaluation boards, connected with wires  6 power supplies  4 different USB applications  Not easy to replicate, or use as part of a SDR prototyping solution  Needed small form factor, open design
  47. 47. Current Prototyping Platforms FMComms1 FMC Board 47
  48. 48. FMCOMMS1 Connected to Xilinx Development System ML605 (Virtex-6) 48 Top Bottom
  49. 49. FMC-Comms Board – Tx, Rx, Clocks, Power 49 Rx Tx Rx Tx AD9548 Network Clock Generator/Synchronizer AD9523-1 Low Jitter Clock Generator AD9122 DAC, 16-Bit, 1250 MSPS* ADL5375 Modulator 400 MHz to 6000MHz ADL5602 20 dB Fixed Gain 50 MHz to 4000 MHz ADF4351 Tx Synthesizer 35 MHz to 4400 MHz AD9643 ADC 14-bit , 250 MSPS AD8366 0.25dB Step Size VGA 600MHz Bandwidth ADL5380 Demodulator 400 – 6000MHz ADF4351 Rx Synthesizer 35 MHz to 4400 MHz FMC ConnectorADC Inputs Clock Sync Clock Sync Inputs DAC Outputs +5 V Output for External Amp ADP2323 Dual 3 A Step- Down Switcher ADP7104 High Accuracy 500 mA LDO ADP1740 2 A LDO ADP1740 2 A LDO ADP7104 High Accuracy 500 mA LDO ADP151 Ultralow Noise 200 mA Linear Regulator ADP151 Ultra Low Noise 200 mA Linear Regulator ADG3304 4 Channel, Bidirectional, Logic Level Translator • AD9122 DAC runs at 1000MSPS, due to max speed of AD9523-1
  50. 50. FMCOMMS1-EBZ Block Diagram 50 Clock Generator / Sync Clock Distribution Frequency Synthesizer ADL5375 ADL5602 ADL5380AD8366AD9643 AD9548 AD9523-1 ADF4351 LPC(32Data+3CLKLVDS)FMCConnector(500MHz) FPGADevelopmentPlatform RF Out RF In Slave Clock In Sync In DAC 16-Bit 1250MSPS* AD9122 Modulator 400 – 6000MHz 20dB Fixed Gain 50 – 4000MHz ADC 14-Bit 250MSPS 0.25dB Step Size 600MHz Bandwidth Demodulator 400 – 6000MHz Output: 1 – 1000MHzInput: 1Hz – 750MHz Output: 35 – 4400MHz ADL5605/ADL5606 700 – 1000MHz 1800 – 2700MHz π π Frequency Synthesizer Master Clock Out 16 + 1 LVDS Pair @ 1000 Mbps 500MHz (DDR) 16 + 1 LVDS Pair @ 500 Mbps 250MHz DDR π Pi network Solder bump jumperS S S S S 1 LVDS Pair 50MHz Ref Clock SMA connector I2C/USB to SPI SPI SPI SPI SPI SPI SPI SPI Power 5V @ 500mA ADL5523 400 – 4000MHz Low Noise Amplifier Tuned for frequency π Tx Rx RF output power control is accomplished by adjusting baseband data Optional Front end Optional Front End 2 2 -9dB 0dB0dB Non-SMA connector • AD9122 DAC runs at 1000MSPS, due to max speed of AD9523-1
  51. 51. Reference Designs HDL:  ML605 (Microblaze)  KC705 (Microblaze)  VC707 (Microblaze)  ZC702 (ARM)  ZC706 (ARM)  Zed Board (ARM) Software:  Linux  Recommended solution  Drivers for all programmable parts (AD9122, AD9548, AD9523-1, ADF4351, AD9643, AD8366)  Streams data over network for Microblaze platforms  GTK+ based application for ARM based platforms  No-OS  Basic drivers http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl 51
  52. 52. System Level/Software Level Block Diagram 52 DAC ADC HDMI SPDIF I2S FMComms ADV7511 HDMI Tx ADAU1761 Audio Codec 512 MB DDR3 Zed Board
  53. 53. IIO Scope – Linux Application Visualize Data: Control Things from GUI: 53
  54. 54. Tweet it out! @ADI_News #ADIDC13 What We Covered Software Defined Radio (SDR) Overview How to Solve Channel Impairments  New features in ADI DACs and ADCs to solve these problems Solutions for SDR  FMComms1 board  Tools, drivers, and example HDL designs  Where to go to get things 54
  55. 55. Tweet it out! @ADI_News #ADIDC13 Part number Description AD9122 DUAL, 16-BIT, 1200 MSPS, TxDAC+® DIGITAL-TO-ANALOG CONVERTER ADL5375 400 MHz TO 6 GHz BROADBAND QUADRATURE MODULATOR ADL5602 50 MHz TO 4.0 GHz RF/IF GAIN BLOCK AD9548 QUAD/OCTAL INPUT NETWORK CLOCK GENERATOR/SYNCHRONIZER AD9523-1 LOW JITTER CLOCK GENERATOR WITH 14 LVPECL/LVDS/HSTL/29 LVCMOS OUTPUTS ADF4351 WIDEBAND SYNTHESIZER WITH INTEGRATED VCO AD9643 14-BIT, 170 MSPS/210 MSPS/250 MSPS, 1.8 V DUAL ANALOG-TO-DIGITAL CONVERTER (ADC) AD8366 DC TO 600 MHz, DUAL-DIGITAL VARIABLE GAIN AMPLIFIERS ADL5380 400 MHz TO 6000 MHz QUADRATURE DEMODULATOR ADG3304 LOW VOLTAGE 1.15 V TO 5.5 V, 4 CHANNEL, BIDIRECTIONAL, LOGIC LEVEL TRANSLATOR ADP2323 DUAL 3A, 20V SYNCHRONOUS STEP-DOWN REGULATOR WITH INTEGRATED HIGH-SIDE MOSFET ADP3335 HIGH ACCURACY ULTRALOW QUIESCENT CURRENT, 500 mA, ANYCAP® LOW DROPOUT ADP3333 HIGH ACCURACY ULTRALOW IQ, 300 mA, ANYCAP LOW DROPOUT REGULATOR ADP150 ULTRALOW NOISE, 150 MA CMOS LINEAR REGULATOR ADP151 ULTRA LOW NOISE, 200 mA CMOS LINEAR REGULATOR ADP1740 2 A, LOW VIN DROPOUT, LINEAR REGULATOR FMComms1-EBZ FMC COMMUNICATIONS Selection Table of Products Covered Today 55
  56. 56. Tweet it out! @ADI_News #ADIDC13 FMComms1 Demo in Exhibition Hall Ubuntu Linux on ZC702 FMComms1 on FMC HDMI Display and USB Keyboard/Mouse Full Transmit and Receive 56 Image of demo/board This demo board is available for purchase: www.analog.com/DC13-hardware
  57. 57. Tweet it out! @ADI_News #ADIDC13 Next Steps Come see the demo Buy the AD-FMComms1-EBZ Board (self assemble your own kit) $750 Or buy the Avnet Kit – it’s in stock $1499  Avnet ZedBoard 7020 baseboard  Xilinx ISE® WebPACK software with a device locked ChipScope license (device locked to XC7Z020)  Analog Devices AD-FMCOMMS1-EBZ FMC module  Linux drivers, applications software, HDL source, reference designs, full schematics, and Gerbers  Two pulse LTE blade antennas (2500 MHz to 2700 MHz)  8 GB SD card  Fan assembly, antenna, screws, and standoffs Ask questions on the EngineerZone  http://ez.analog.com/community/fpga Check out the Wiki  http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms1-ebz 57

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