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    Ms 2446 final Ms 2446 final Document Transcript

    • Technical ArticleMS-2446.www.analog.comPage 1 of 5 ©2013 Analog Devices, Inc. All rights reserved.The ABCs of Interleaved ADCsby Jonathan Harris, Applications Engineer, AnalogDevices, Inc.INTRODUCTIONAcross many segments of the market today, interleavingADCs offers several advantages in many applications. Incommunications infrastructure there is constantly a push forhigher sample rate ADCs to allow for multiband, multicarrierradios, in addition to wider bandwidth requirements forlinearization techniques like DPD (digital predistortion). Inmilitary and aerospace, higher sample rate ADCs allow formultipurpose systems that can be used for communications,electronic surveillance, and radar just to name a few. In yetanother segment, industrial instrumentation, the need isalways increasing for higher sample rate ADCs so that higherspeed signals can be measured adequately and accurately.It is first important to understand exactly what interleavingADCs is about. To understand interleaving, it is good to lookat what is actually happening and how it is being implemented.With a basic understanding, the benefits of interleaving canthen be discussed. Of course, as many know, there is no suchthing as a free lunch, so the challenges of interleaving needto be evaluated and assessed.ABOUT INTERLEAVINGWhen ADCs are interleaved, two or more ADCs with adefined clocking relationship are used to simultaneouslysample an input signal and produce a combined outputsignal that results in a sampling bandwidth at some multipleof the individual ADCs. Utilizing m number of ADCs allowsfor the effective sample rate to be increased by a factor of m.For the sake of simplicity and ease of understanding, we’llfocus on the case of two ADCs. In this case, if two ADCswith each having a sample rate of fS are interleaved, theresultant sample rate is simply 2fS. These two ADCs musthave a clock phase relationship for the interleaving to workproperly. The clock phase relationship is governed byEquation 1, where n is the specific ADC and m is the totalnumber of ADCs.∅ 𝑛 = 2𝜋 �𝑛−1𝑚� (1)As an example, two ADCs each, with a sample rate of100 MSPS, are interleaved to achieve a sample rate of200 MSPS. In this case, Equation 1 can be used to derive theclock phase relationship of the two ADCs and is given byEquation 2 and Equation 3.∅1 = 2𝜋 �1−12� = 0 𝑟𝑎𝑑𝑖𝑎𝑛𝑠 = 0 𝑜(2)∅2 = 2𝜋 �2−12� = 𝜋 𝑟𝑎𝑑𝑖𝑎𝑛𝑠 = 180 𝑜(3)Now that the clock phase relationship is known, theconstruction of samples can be examined. Figure 1 gives avisual representation of the clock phase relationship and thesample construction of two 100 MSPS interleaved ADCs.Notice the 180° clock phase relationship and how the samplesare interleaved. The input waveform is alternatively sampledby the two ADCs. In this case, the interleaving is implementedby using a 200 MHz clock input that is divided by a factor oftwo and the required phases of the clock to each ADC.Figure 1. Two Interleaved 100 MSPS ADCs—Basic DiagramAnother representation of this concept is illustrated inFigure 2. By interleaving these two 100 MSPS ADCs, thesample rate is increased to 200 MSPS. This extends eachNyquist zone from 50 MHz to 100 MHz, doubling theavailable bandwidth in which to operate. The increasedoperational bandwidth brings many advantages to applicationsacross many market segments. Radio systems can increasethe number of supported bands; radar systems can improvespatial resolution, and measurement equipment can achievegreater analog input bandwidth.Figure 2. Two Interleaved 100 MSPS ADCs—Clocking and Samples
    • MS-2446 Technical ArticlePage 2 of 5BENEFITS OF INTERLEAVINGThe benefits of interleaving span across multiple segments ofthe market. The most desired benefit of interleaving is theincreased bandwidth made possible by the wider Nyquistzone of the interleaved ADCs. Once again, taking theexample of two 100 MSPS ADCs interleaved to create asample rate of 200 MSPS, Figure 3 gives a representation ofthe much wider bandwidth allowed by interleaving the twoADCs. This creates advantages for many different applications.As cellular standards increase channel bandwidth and thenumber of operating bands, there are increased demands onthe available bandwidth in the ADC. In addition, in militaryapplications, the requirements for better spatial recognition,as well as increased channel bandwidths in backend com-munications require higher bandwidths from the ADC. Dueto the increased demands for bandwidth in these areas, thereis a need created to measure these signals accurately. Therefore,measurement equipment has increased needs for higherbandwidths in order to properly acquire and measure thesesignals that have higher bandwidth. The system requirementsin many designs inherently stay ahead of commercial ADCtechnology. Interleaving allows for some of this gap to be closed.Figure 3. Two Interleaved ADCs—Nyquist ZoneThe increased sample rate provides more bandwidth forthese applications but also allows for easier frequencyplanning and reduction in the complexity and cost of theanti-aliasing filter that is typically used at the ADC inputs.With all these great benefits, one has to wonder what theprice is to pay. As with most things, there is no such thing asa free lunch. Interleaved ADCs offer increased bandwidthand other nice benefits, but there are some challenges thatarise when dealing with interleaved ADCs.CHALLENGES WITH INTERLEAVINGThere are some challenges and things to look out for wheninterleaving ADCs. There are spurs that appear in the outputspectrum that result from the imperfections associated withinterleaving ADCs. These imperfections are basicallymismatches between the two ADCs that are beinginterleaved. There are four basic mismatches that result inspurs in the output spectrum. These are offset mismatch,gain mismatch, timing mismatch, and bandwidth mismatch.The easiest of these to understand is probably the offsetmismatch between the two ADCs. Each ADC will have anassociated dc offset value. When the two ADCs are interleavedand samples are acquired alternatively back and forth betweenthe two ADCs, the dc offset of each successive sample ischanging. Figure 4 gives an example of how each ADC hasits own dc offset and how the interleaved output will effectivelyswitch back and forth between these two dc offset values.The output switches between these offset values at a rateof fS/2 which will result in a spur in the output spectrumlocated at fS/2. Since the mismatch itself does not have afrequency component and is only at dc, the frequency of thespur that appears in the output spectrum only depends onthe sampling frequency and will always appear at a frequencyof fS/2. The magnitude of the spur is dependent upon themagnitude of the offset mismatch between the ADCs. Thegreater the mismatch, the larger the spur will be. In order tominimize the spur caused by the offset mismatch, it is notnecessary to completely null the dc offset in each ADC.Doing this would filter out any DC content in the signal andwould not work for systems using a ZIF (zero IF) architecturewhere the signal content is real and complex and includesdata at DC. Instead, a more appropriate technique would beto match the offset of one of the ADCs to the other ADC.The offset of one ADC is chosen as the reference, and theoffset of the other ADC is set to match that value as closelyas possible. The better matched the offset values are, thelower the resulting spur is at fS/2.The second mismatch to look at when interleaving isthe gain mismatch between the ADCs. Figure 5 gives arepresentation of the gain mismatch between two interleavedconverters. In this case, there is a frequency component tothe mismatch. In order to observe this mismatch, there hasto be a signal applied to the ADCs. In the case of the offsetmismatch, no signal is necessary to see the inherent dc offsetof the two ADCs. In the case of the gain mismatch, there isno way to see the gain mismatch unless a signal is presentand the gain mismatch can be measured. The gain mismatchwill result in a spur in the output spectrum that is related tothe input frequency, as well as the sampling rate, and willappear at fS/2 ± fIN. In order to minimize the spur caused by
    • Technical Article MS-2446Page 3 of 5the gain mismatch, a similar strategy as what is used for theoffset mismatch is employed. The gain of one of the ADCs ischosen as the reference, and the gain of the other ADC is setto match that gain value as closely as possible. The better thegain values of each ADC are matched to each other, the lessthe resulting spur will be in the output spectrum.Next, we must examine the timing mismatch between thetwo ADCs. The timing mismatch has two components,group delay in the analog section of the ADC and clockskew. The analog circuitry within the ADC has an associatedgroup delay and the value can be different between the twoADCs. In addition, there is clock skew that has an apertureuncertainty component in each of the ADCs and has acomponent related to the accuracy of the clock phasesthat are input to each converter. Figure 6 gives a visualrepresentation of the mechanism and effects of the timingmismatches in the ADCs. Similar to the gain mismatch spur,the timing mismatch spur is also a function of the inputfrequency and the sample rate and appears at fS/2 ± fIN.In order to minimize the resulting spur, the group delaythrough the analog section of each converter needs to beproperly matched with good circuit design techniques. Inaddition, the clock path designs need to be closely matchedto minimize aperture uncertainty differences. And lastly, theclock phase relationships need to be precisely controlledsuch that the two input clocks are as close to 180° apart aspossible. As with the other mismatches, the goal is toattempt to minimize the mechanisms that cause the timingmismatch.The last mismatch to look at is probably the most difficult tocomprehend and handle; it is the bandwidth mismatch. Asshown in Figure 7, the bandwidth mismatch has a gain and aphase/frequency component. This makes bandwidth mismatchmore difficult because it contains components from two ofthe other mismatch parameters. In the bandwidth mismatch,however, we see different gain values at different frequencies.In addition, the bandwidth has a timing component whichcauses signals at different frequencies to have differentdelays through each converter. The best way to minimizethe bandwidth mismatch is to have very good circuit designand layout practices that work to minimize the bandwidthmismatches between the ADCs. The better matched eachADC is, the less the resulting spur will be. Just as the gainand timing mismatches caused spurs in the output spectrumat fS/2 ± fIN, the bandwidth mismatch also results in a spur atthe same frequency.Figure 4. Offset MismatchFigure 5. Gain Mismatch
    • MS-2446 Technical ArticlePage 4 of 5Figure 6. Timing MismatchFigure 7. Bandwidth MismatchNow that we’ve discussed four different mismatches thatcause issues when interleaving ADCs, it is apparent that acommonality has emerged. Three of the four mismatchesproduce a spur in the output spectrum at fS/2 ± fIN. Theoffset mismatch spur can be easily identified since it aloneresides at fS/2 and can be compensated fairly easily. The gain,timing, and bandwidth mismatches all produce a spur atfS/2 ± fIN in the output spectrum so the question is how toidentify the contribution of each. Figure 8 gives a quickvisual guide to the process of identifying the sources of thespurs from the different mismatches of interleaved ADCs.Figure 8. Interrelated Nature of Interleaving MismatchesIf looking purely at gain mismatch alone, it is a lowfrequency, or dc, type of mismatch. The gain componentof the bandwidth mismatch can be separated from the gainmismatch by performing a gain measurement at lowfrequency near dc and then performing gain measurementsat higher frequencies. The gain mismatch is not a functionof frequency like the gain component of the bandwidthmismatch. A similar approach is used for the timing mismatch.A measurement is performed at low frequency near dc andthen subsequent measurements are performed at higherfrequencies to separate the timing component of bandwidthmismatch from the timing mismatch.CONCLUSIONThe newest communication system designs, cutting edgeradar technologies, and ultrahigh bandwidth measurementequipment seem to constantly outpace the available ADCtechnology. These requirements push both users andmanufacturers of ADCs to develop methods to keep pacewith these demands. Interleaving ADCs allows for greaterbandwidths to be achieved at a faster pace than the traditionalpath of increasing the conversion rate of a typical ADC. Bytaking two or more ADCs and interleaving them together,the available bandwidth is increased, and system designrequirements can be met at a faster pace. Interleaving ADCsdoes not come for free, however, and mismatches betweenthe ADCs cannot be ignored. Even though the mismatchesdo exist, knowing about them and how to appropriately dealwith them can enable designers to use these interleaved ADCsmore intelligently and meet the ever increasing demands oftheir latest system designs.
    • Technical Article MS-2446Page 5 of 5REFERENCESHad, Jim, Mark Looney, and Rob Reeder. “Pushing the Stateof the Art with Mulitchannel A/D Converters.” AnalogDialogue. Vol. 39, No. 5, May 2005.RESOURCESShare this article onOne Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.comTrademarks and registered trademarks are the property oftheir respective owners. TA11329-0-1/13www.analog.com©2013 Analog Devices, Inc. All rights reserved.