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Ms 2433 final
 

Ms 2433 final

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    Ms 2433 final Ms 2433 final Document Transcript

    • Technical ArticleMS-2433.www.analog.comPage 1 of 2 ©2013 Analog Devices, Inc. All rights reserved.Synchronizing Multiple ADCsUsing JESD204Bby Ian Beavers, Applications Engineer, AnalogDevices, Inc.IDEA IN BRIEFMany communications, instrumentation, and signalacquisition systems require the ability to simultaneouslysample analog input signals across multiple analog-to-digital converters (ADC). The sampled data then needsto be processed with the expectation of synchronizationacross these inputs that each have their own variousdifferent latencies. This has historically been a difficultchallenge for system designers to meet with LVDS andparallel output ADCs.JESD204B provides a framework for high speed serial datato be sent along one or more differential signal pairs, suchas an output of an ADC. There is an inherent scheme in theinterface to achieve coarse alignment across lanes withinthe JESD204B specification. Data is partitioned into frameswith boundaries that are continuously sent to the receiver.The JESD204B Subclass 1 interface has provisions for dataalignment down to the sample level across multiple seriallane links or multiple ADCs by using a system referenceevent signal (SYSREF) to synchronize internal framingclocks in both the transmitter and receiver. This creates adeterministic latency for the devices using the JESD204Blink. However, there are still many challenges that a systemdesigner must overcome to achieve full timing closure forsampling synchronization, such as PCB layout considerations,matched clock, and SYSREF generation to meet timing,SYSREF periodicity, and digital FIFO delays.The designer must decide how the device clock and SYSREFsignal will be created and distributed throughout the system.Ideally, the device clock and SYSREF should be of the sameswing level and offset to prevent inherent skew at thecomponent input pin. The update rate of the SYSREF eventwill need to be determined as either a single event at startupor a recurring signal that may occur at any time synchro-nization is needed. Taking the maximum clock and SYSREFsignal skew into consideration, careful PCB layout is neededto meet setup and hold timing across boards, connectors,backplanes, and various components. Finally, digital FIFOdesign and signals traversing across multiple clock domainscreate inherent digital buffer skew within JESD204Btransmitters and receivers that must be accounted for andremoved in back-end data processing.System clock generation can come from several sources suchas crystals, VCOs, and clock generation or clock distributionchips. While the particular system performance will dictatethe clocking needs, one, using multiple synchronous ADCs,must be able to produce a SYSREF signal that is sourcesynchronous to the input clock. This makes the clock sourceselection an important consideration in order to be able tolatch this system reference event with a known clock edge ata particular point in time. If the SYSREF signal and clock arenot phased locked, this cannot be achieved.An FPGA can be used to provide a SYSREF event to thesystem. However, unless it also uses and synchronizes tothe master sample clock that is sent to the ADCs, it will bedifficult to phase align the SYSREF signal from the FPGAto the clock. An alternate approach is to provide the SYSREFsignal from a clock generation or clock distribution chipthat can phase align this signal to multiple clocks that aresent throughout the system. Using this method, the SYSREFevent can be a one shot event at startup, or a recurring signaldepending upon the system requirements.As long as deterministic latency remains constant within thesystem across ADCs and FPGAs, additional SYSREF pulsesmay not be needed except to help frame particular systemdata. Hence, a periodic SYSREF pulse for clock alignmentcan be ignored or filtered until the time at which synchro-nization is lost. A marker sample for the occurrence ofSYSREF could alternately be maintained without resettingthe JESD204B link.In order to initiate a known deterministic starting point forthe ADC channels, the system engineer must be able to closetiming for the SYSREF event signal distributed across thesystem. This means that the expected setup and hold time,relative to the clock, must be met without violation. Use of arelatively long SYSREF pulse that spans multiple clock cyclescan be used to meet the hold time requirement, so long asthe setup time to the first required clock can also be met.Careful attention to PCB layout is critical in this effort tomaintain matched trace lengths for clocks and SYSREF withinthe system for minimum skew. This may be the most difficultpart of achieving synchronous sampling processing acrosschannels. The effort will only get progressively more
    • MS-2433 Technical ArticlePage 2 of 2challenging as ADC encode clock rates increase andmultiboard systems become more complex.SYSREF to clock board skew at components across boardsand connectors must be deterministically known for eachdevice by the system engineer. Any remaining inter-devicedigital and clock skew delays need to be effectively nulled inthe FPGA or ASIC. Back-end processing can change thesample order across ADCs and introduce any needed re-alignment to prepare the data for further synchronizedprocessing. Correction for inter-device sample skew canbe accomplished by delaying the fastest data samples andtransmitter latency to align with the slowest data samplesin the back-end FPGA or ASIC. For complex systems, thismay involve multiple FPGA or ASIC where each needs tocommunicate their total inter-device sample latency for finalalignment. By introducing appropriate elastic buffer delaysin the JESD204B receiver(s) to accommodate each specifictransmitter latency delay, the inter-device sample skews canbe aligned with known determinism across a system.Figure 1. Diagram Showing the AD9250, the AD9525, and FPGAThe AD9250 is a 250 MSPS 14-bit dual ADC from AnalogDevices, Inc., that supports the JESD204B interface in aSubclass 1 implementation. This subclass allows analogsample synchronization across ADCs using the SYSREFevent signal. The AD9525 is a low jitter clock generator thatnot only provides seven clock outputs up to 3.1 GHz but isalso able to synchronize a SYSREF output signal based onuser configurations. These two products, coupled with aselection of fanout buffer products from Analog Devices,provide the framework to accurately synchronize and alignmultiple ADC data sent to an FPGA or ASIC for processing.ABOUT THE AUTHORIan Beavers is an applications engineer for the High SpeedConverter Group at Analog Devices, Inc. (Greensboro, NC).He has worked for the company since 1999. Ian has over15 years of experience in the semiconductor industry. Heearned a bachelor’s degree in electrical engineering fromNorth Carolina State University and an MBA from theUniversity of North Carolina at Greensboro. He can bereached at Ian.Beavers@analog.com.RESOURCESShare this article onOne Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.comTrademarks and registered trademarks are the property oftheir respective owners. TA11325-0-1/13www.analog.com©2013 Analog Devices, Inc. All rights reserved.