Demystifying the JESD204B High-speed Data Converter-to-FPGA interface
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Demystifying the JESD204B High-speed Data Converter-to-FPGA interface

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Learn all about the JESD204 standard. This presentation provides an overview of the JESD204 serial interface standard from its origin up to the current "B" revision. Common "high-performance metrics" ...

Learn all about the JESD204 standard. This presentation provides an overview of the JESD204 serial interface standard from its origin up to the current "B" revision. Common "high-performance metrics" that are associated with high speed serial interfaces are also discussed. by Analog Devices, Inc.

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  • I will first begin with a discussion of the background of the JESD204 standard. We will discuss the standard’s development and the differences that exist between the revisions of the JESD204 standard. The standard is currently at revision B.Next, we will look at the link structure and lane configurations of the standard. I will discuss the differences between the different versions of the standard, but will primarily focus on the JESD204 A and B revisions. After taking a look at the link and lane configuration, we will dive into the key signals and layers in the JESD204 standard. Again, we will mostly focus on the JESD204 A and B versions of the specification. We are focusing here because these are the most recent iterations and therefore the most relevant.Once we have discussed the JESD204 specification, we will briefly look at practical layout considerations for the interface. These practices are applicable to many other high speed serial interfaces.
  • In beginning to look at the JESD204 interface, probably one of the first questions is why do we need it. Most converters currently use either CMOS or Parallel LVDS interfaces. Why aren’t these good enough? We are using differential signaling for Parallel LVDS, that should be good, right? Well, as the speed and resolution of converters increase the CMOS and Parallel LVDS schemes basically run out of gas. CMOS is too power hungry for converters above 200MSPS or so. It becomes impractical to use CMOS as speeds increase and resolution increases. Parallel LVDS is more power efficient, but it has the limitation of speed as well as I/O count as converter resolution increases. JESD204 offers a reduction in pin count for both the Tx and Rx side. The number of I/O required is dramatically reduced . Not only is the number of data lines reduced, but the clock is embedded further reducing the pin count.By achieving such reductions, smaller IC packages and board designs can be used and the system cost is brought down. The standard is also very scalable so as the speed and resolution of converters increase in the future, the standard can scale to meet those future demands.
  • So what is JESD204? The JESD204 standard defines a mult-gigabit serial data link between converters and a receiver, which is most commonly an FPGA but could also be an ASIC. The original standard was called JESD204 and was released in April 2006. It described 1 lane and 1 link between and converter(s) and a receiver. This version of the standard described a single serial lane that could support multiple converters. A common frame clock is used between the converter(s) and the FPGA; this clock also serves as the sampling clock for the converter.
  • The standard underwent a revision to the ‘A’ version in April of 2008. This expanded the scope to incorporate multiple links and multiple lanes. This allowed for multiple aligned serial lanes for multiple converters. It was defined to operated at speeds up to 3.125 Gbps. This was also the speed understood for the original JESD204 standard. And also like the original standard, a common frame clock is used between the converter(s) and the FPGA which also serves as the sampling clock for the converter.
  • In August of 2011, JESD204B was released. This update to the standard addeddevice clocks (which must be harmonically related). Also added were provisions to ensure deterministic latency in the system. This version supports multiple serial lanes for multiple converters as well, but the data rate of the interfaced was increasedup to 12.5 Gbps.
  • Let’s now take a look at some key aspects of the JESD204 standards. An 8b/10b embedded clock is utilized which uses DC balanced encoding. This guarantees significant transition frequency for use with clock and data recovery designs. This encoding allows both data and control characters to be used. The control characters can be used in specifying link alignment, maintenance, monitoring, etc. This encoding also allows for the detection of single bit error events that occur on the link.Serial lane alignment is achieved by using special training patterns with control characters that allow lanes to be aligned across a link. This allows for the trace to trace tolerance to be relaxed in comparison to synchronous parallel LVDS designs.Serial lane maintenance is accomplished by through super frame structure and by using specific characters to guarantee alignment. The link quality is monitored by the receiver and is done on a lane by lane basis. It is important to note that the link is established and dropped by the receiver based on error thresholds defined within the JESD204 specification.
  • Let’s move on now to discuss some key signals in JESD204 A and B systems as these are the most prevalent versions in use.The frame clock in JESD204a is a clock signal used in the system that is equal to the frame rate of the data on the link. The frame clock serves as the master timing reference for JESD204A systems. In JESD204B systems, a device clock is used to derive the frame rate of the data on the link. The frame clock is not used.The SYNC bar signal is a system synchronous, active low signal that goes from the receiver to the transmitter and denotes the state of synchronization. This signal is synchronous to the frame clock in JESD204A and to the Local Multi-Frame Clock in JESD204B. When the signal is low it implies the receiver and transmitter are synchronizing. Lanes are defined from lane 0 up to lane L – 1. These are the differential lanes that exist on the JESD204A/B link. Due to the high speed of data transfer these are typically high speed CML. It is important to remember that the 8b/10b code groups are transmitted over the link MSB first and LSB last. New in JESD204B is the optional SYSREF signal. This signal is responsible for resetting device clock dividers to ensure deterministic latency. It can be one-shot, gapped periodic, or periodic and is distributed to both the converters and receivers in the system. When used, SYSREF is the master timing reference in the JESD204B system.
  • The frame clock in JESD204A is a clock signal used in the system that is equal to the frame rate of the data on the link. The frame clock serves as the master timing reference for 204A systemsThe SYNC bar signal is a system synchronous, active low signal that goes from the receiver to the transmitter and denotes the state of synchronization. This signal is synchronous to the frame clock in JESD204A. When the signal is low it implies the receiver and transmitter are synchronizing. The SYNC bar and frame clock should have similar compliance to ensure proper capture and transmission timing. For example, LVDS, CMOS, or CML could be used so long as both SYNC bar and frame clock utilized the same signal type.Lanes are defined from lane 0 up to lane L – 1. These are the differential lanes that exist on the JESD204A link. Due to the high speed of data transfer these are typically high speed CML. It is important to remember that the 8b/10b code groups are transmitted over the link MSB first and LSB last.
  • The device clock in JESD204B is a clock signal that each transmitter and receiver derives from the master clock generator circuit. The device clock may have a different period than the frame or multiframe period. If it differs, then the device (transmitter or reciever) is responsible for generating the frame or multiframe clock from the device clock.The SYNC bar signal is much the same as in JESD204A, but in this case it is synchronous to the local multiframe clock.New in JESD204B is the optional SYSREF signal. This signal is responsible for resetting device clock dividers to ensure deterministic latency. It can be one-shot, gapped periodic, or periodic and is distributed to both the ADCs and receivers in the system. When used, SYSREF is the master timing reference in the JESD204B system.Just as in JESD204A, the lanes are defined from lane 0 up to lane L – 1. These are the differential lanes that exist on the JESD204B link. Again, these are typically high speed CML. The 8b/10b code groups are transmitted over the link similar to JESD204A with MSB first and LSB last.
  • The JESD204 standards is a layered specification. Here we take a look at the different layers within the specification.The transport layer maps conversion samples to and from framed non-scrambled octets. The scrambling layers can optionally take those octets and scramble or descramble them in order to reduce EMI effects by spreading the spectral peaks. Scrambling would be done in the transmitter and descrambling done in the receiver. The data link layer is where the optionally scrambled octets are encoded or decoded to or from 10-bit characters. This layer is also where control character generation or detection is done for lane alignment monitoring and maintenance. The physical layer is the serializer/deserializer or (SERDES) layer responsible for transmitting or receiving the characters at line rate speeds. This layer include drivers, receivers, clock and data recovery, etc.
  • This is just a simplified visual representation of the layers of the JESD204 specification. This allows you to see the data flow through the transmitter and receiver along with the timing reference signals used in the system. You can see the flow here goes from the Tx application layer through the transport layer and optional scrambling through to the data link layer through to the transmitter physical layer and on to the receiver physical layer via the high speed serial lanes then it proceeds through the data link layer on to the transport layer and optional descrambling and finally ends at the receiver application layer.
  • Let’s now dive into the transport layer of the JESD204. A single converter can be mapped to a single-lane link or can be mapped to a multi-lane link. The same holds true for multiple converters in the same device. The converters can be mapped to a single-lane link or into a multi-lane link. The conversion samples are recommend to be mapped into JESD204 words on 4-bit nibble boundaries. The figure at the right shows the mapping of converter samples into the serial lanes. It is parameterized such that it covers all of the aforementioned cases. For the sake of time, I would encourage you to download this presentation when it is made available and study this chart to further understand the mapping of the samples.
  • The optional scrambling layer resides between the transport layer and link layer. It is implemented in order to reduce spectral peak emissions on the high speed serial lanes between the transmitter and receiver. The block utilizes a self synchronous scrambling pattern that has the polynomial 1 + x^14 + x^15. The data is scrambled prior to the 8b/10b encoder and is descrambled in the receiver after decoding. Since the scrambling pattern is self synchronous, the two shift registers at the input and output must not be set to the same initial setting, otherwise, the scrambling function would not work. The descrambler is done such that it will always catch up and self-synchronize to the scrambler after two octets of data. This layer should have the ability to be bypassed since not all systems may require the data stream to be scrambled.
  • There are three distinct phases of link establishment:1. Code Group Synchronization (CGS)In this phase, each receiver must locate K28.5 characters in its input data stream using Clock and Data Recovery (CDR) techniques.Once a certain number of consecutive K28.5 characters have been detected on all link lanes, the receiver block de-asserts the SYNC~ signal to the transmitter block.In JESD204A, the transmit block captures the change in SYNC~ and after a fixed number of frame clocks, starts the Initial Lane Alignment Sequence (ILAS).In JESD204B, the transmit block captures the change in SYNC~ and starts the Initial Lane Alignment Sequence (ILAS) on the next LMFC boundary.2. Initial Lane Alignment Sequence (ILAS)The main purpose of this phase is to align all the lanes of the link and verify the parameters of the link.During ILAS, the link parameters are sent to the receiver device to designate how data will be sent to the receiver block.ILAS consists of 4 or more multi-frames. The last character or each multi-frame is a multi-frame alignment character /A/.The first, third, and fourth multi-frames begins with an /R/ character and end with an /A/ character. The data in between them is ramp data. The receiver uses the final /A/ of each lane to align the ends of the multi-frames within the receiver.The second multi-frame contains an /R/ and /Q/ character followed by link parameters.
  • There are three distinct phases of link establishment:2. ILAS - continuedAdditional multi-frames can be added to ILAS if needed by the receiver. After the last /A/ character of the last ILAS multi-frame, User Data starts.In systems were no inter-lane skew management is needed, ILAS can be bypassed given both the transmitter and receiver support the mode.3. User DataIn this phase, user data is streamed from the transmitter block to the receiver block.Data can be optionally scrambled, yet scrambling does not start until the very first octet following the ILAS.The receiver block processes and monitors the data it receives for errors including:Incorrect running disparity (8B/10B error)Not in Table (8B/10B error)Unexpected control-characterIncorrect ILASInter-lane skew error - This is monitored through a practice called character replacementIf any of these errors exists, it is reported back to the transmitter in one of a few ways.SYNC~ assertion – Resynchronization (SYNC~ pulled low) is called for at each error.SYNC~ reporting – The SYNC~ is pulsed high for a frame clock period if an error occurs.Reporting may also be done via interrupt if so equipped. This is not covered by the spec.This would happen at a very bad link disruption.The following slide shows the three phases of link establishment
  • During the initial lane alignment sequence, the data link layers are responsible for aligning the lanes in the receiver. The placement of of /A/ characters are used to align the lanes in the receiver. The JESD204 A and B specifications require that the /A/ characters be separated by at least 17 octets. This mitigates the affects of a large amount of system skew. In JESD204 A and B systems, skew is defined in three possible scenarios – 1) One transmitter block and one receiver block, 2) multiple transmitter blocks and one receiver block, and 3) one transmitter block and multiple receiver blocks.
  • Upon reaching the User Data phase, character replacement in the data link layer allows frame and lane alignment to be monitored and corrected if necessary. Character replacement is performed on both frame and mult-frame boundaries with different implementation between the transmitter and receiver. Let’s first take a look at transmitter character replacement. There are two cases, one for frame based character replacement and the other for multi-frame based character replacement.In frame based character replacement, if the last character of a frame is identical to the last character of the previous frame on a given lane, then the transmitter will substitute that character with an /F/ character. This is done also if the last character of the previous frame is 0xFC when scrambling is enabled.In multi-frame based character replacement, if the last character of a multi-frame is identical to the last character of the previous frame on a given lane, then the transmitter will substitute the character with an /A/ character. In this case, character replacement is also done if the last character of the previous multi-frame is 0x7C when scrambling is enabled.In receiver character replacement, the receiver must do the exact opposite of what is done in the transmitter. If an /F/ or /A/ character is detected it is replaced with the final character of the previous frame. When scrambling is enabled, the /F/ characters get replaced by 0xFC and the /A/ characters get replaced by 0x7C.If the receiver detects /F/ or /A/ characters in the wrong places, it can realign the lanes on the fly. However, data will be corrupted while it performs this operation.
  • Let’s take a closer look now at the implications of character replacement. The /F/ and /A/ characters may not come along very often, so it is possible that data could be bad for a while before the receiver recognizes that it is bad. This means that garbage data could potentially be sent for some period of time. However, if the error is in the CDR or the high speed link, the 8b/10b error detector should see it well in advance.If realignment is supported, each lane can realign to either an /F/ or /A/ character. The JESD204A specification does include information about realigning characters or alignment counters on the fly. Unless the transmitter or the receiver skips a character clock, there shouldn’t be a problem.So where would this make sense. In sparse data system or packet systems, this is beneficial so that data would not be lost. Also for systems with dense data transfer, realignment will be preceded by a stream of garbage data.
  • The JESD204 standard requires that at least four different types of errors be detected in addition to alignment errors. Incorrect running disparity on the link is monitored by both the transmitter and receiver. Not in Table errors are also monitored and when a character not in the 8B/10B code table of characters is transmitted, an error is generated. Control characters that are out of place also flag an error. Last, code group sync errors are flagged. These would include errors such as wrong length, wrong structure, or mismatched link parameters. A system designer may choose to support more error detection, but these four types of errors are required as a minimum by the standard.
  • Moving on to the JESD204 physical layer… This is where characters are transmitted and received at line rate speeds. The physical layer included serial/deserializer (SERDES) blocks, drivers, receivers, CDR, etc. These blocks are often designed using custom cells since the data transfer rates are very high. The JESD204 and JESD204A both support speeds up to 3.125 Gbps as I mentioned previously. The JESD204B specification supports three possible speed grades. Speed Grade 1 supports up to 3.125 Gbps and is based on the OIF-SxI5-0.10 specification. Speed Grade 2 supports up to 6.375 Gbps and is based on the CEI-6G-SR specification. I have also included links to both of these specifications at the end of the presentation slides. The third speed grade supports up to 12.5 Gbps and is based on the CEI-11G-SR specifcation. We will take a closer look at these three specifications in the next slide.
  • Here we have a table that gives the line rate, differential voltage, rise/fall time and total jitter for the signals in the physical layer of the JESD204 standard. The higher speeds have reduced the required signal amplitudes to make it easier to maintain a high slew rate. These high speed signals with fast rising and falling edges place tight constraints on board level design. Careful attention to trace impedance, lengths, layer stackup, etc is require for good system operation. One must have a good set of physical design rules to work from to have a properly working system.
  • I have mentioned deterministic latency a few times, so let’s take a closer look to understand it a little better. Latency is defined as deterministic when the time from the input of the JESD204 transmitter to the output of the JESD204 receiver is consistently the same number of clock cycles. When you have a parallel implementation, deterministic latency is simple since clocks are carried with the data. However, in serial implementation, multiple clock domains exist which can cause non-determinism. The JESD204 and JESD204A specifications contain no provisions for guaranteeing deterministic latency. In the ‘B’ version of the specification, there are 3 sub-classes of devices described. These three sub-classes are 1) No support for deterministic latency 2) deterministic latency using SYNC bar (up to 500 MSPS) and 3) deterministic latency using SYSREF (above 500 MSPS).
  • For converters operating at speeds of less than 500MSPS, the SYNC~ signal can be used to guarantee deterministic latency. Once the link synchronization has occurred, the receiver will de-assert SYNC~. The transmitter will capture this even with the frame clock. The latency in the transmitter from the point that it captures the SYNC~ until the beginning of the ILAS must be constant. With that latency know as well as the receiver knowing when it de-asserted SYNC~, the latency of the forward path is known and can be corrected. It is important to note that SYNC~ signaling is system synchronous and it must meet setup and hold times relative to the frame sample edge at the transmitter. If not, there could be issues with the link.
  • SYSREF is used for converters with sample rates above 500 MSPS. Unlike SYNC~, SYSREF is source synchronous meaning the timing of the system depends on the interaction of two devices. The SYSREF signal is intended to future proof the specification in order to account for higher sample rate converters as well as provide the best possible accuracy with the least amount of complexity. In the 204B standard, the SYSREF signal is used to align the internal dividers from the device clocks and to act as the master system reference which aligns all LMFCs (which are used to ensure deterministic latency). The signal can be low speed periodic, gapped periodic, or can be one shot. In the receiver, SYNC~ is asserted from the LMFC edge instead of the frame clock edge. Likewise, in the transmitter, the ILAS is launched from the LMFC edge instead of the frame clock edge. This makes the SYNC~ signal effectively asynchronous to the frame clock and system synchronous to the LMFC. When using SYSREF the system is effectively 100% source synchronous.
  • Now let’s take a look at the link parameters and control characters of the JESD204 standard.L – Number of lanes per converter deviceM – Number of converters per converter deviceS – Number of transmitted samples per converter per frameN’ – Number of transmitted bits per sample (JESD204 word size)N – Number of conversion bits per converter/K/ – K28.5 character used for code group synchronization/F/ – K28.7 character used for frame alignment/A/ – K28.3 character used for multi-frame alignment/R/ – K28.0 character used to begin multi-frame/Q/ – K28.4 character used to begin lane parameter data in Initial Lane AlignmentF – Number of octets per frameHD – High density user data format
  • Some terminology to keep handy when working with JESD204 includes the following terms:octet – a group of 8 bits, serving as input to 8B/10B encoder and output from the decodernibble – a set of 4 bits which is the base working unit of JESD204 specificationscharacter – a 10 bit symbol generated by the 8B/10B encoding schemecharacter clock – a clock running at the character rate used to process the characters of a systemcode group – a set of 10 bits in the serial data stream used to convey octetsRunning disparity – the measure of current DC imbalance on the link used to code and decode 8B/10B code groupsFrame – a set of consecutive octets in which the position of each octet can be identified by reference to a frame alignment signal
  • frame clock – a system clock which runs at the frames rate. In JESD204A systems, the frame clock is the absolute timing reference in the systemmulti-frame – a set of consecutive frames in which the positions of the frames can be identified relative to a multi-frame alignment characterMulti-frame clock or Local Multi-Frame Clock (LMFC) – a clock in the system which runs at the multi-frame rate and determines the location of multi-frame characters which are used for lane alignment. Typically this clock is a divided version of the frame clock which is local to the transmitter/receiver. In the coming JESD204B systems, it is expected that this clock will be the absolute timing reference.
  • lane – a differential pair between transmitter and receiverdata link or link – a set of data lanes which provide a conduit for data to be transferred from transmitter to receivermult-point link – a data communication link with three or more devices. These three devices may be two transmitters and one receiver or may be two receivers and one transmitter.transmitter – a single lane’s worth of encoding, serialization, and drivingtransmitter block – all transmitters for a linkreceiver – a single lane’s worth of capture, deserialization, and decodingreceiver block – all receivers for a linkconverter – a single converter in a packageconverter device – a package with one or more converters
  • Now that we understand the link parameters, let’s take a look at setting up a JESD204 link. First let’s determine the number of converters in the device, M. Next, what is the sample resolution of the device, N. A 12-bit converter would set N = 12. Then we set the word size N’. The converter sample resolution is broken down into nibbles. 12-bit converters have 3 nibbles while 14 and 16 bit converters have 4 nibbles. Multiply the number of nibbles by 4 to determine the value of N’. It can be advantageous to have N’ = 16 so that 8 to 16 bit converters can be handled with the same transmitter or receiver. A non-complete nibble is padded with either Control Bits (CS) or Tail bits (T) and must satisfy the equation N’ = N + CS + T. For example, a 12-bit convert with a 16-bit JESD204 word size leaves 4 bits for either control bits or tail bits.
  • Next, we need to ask how many samples will easily fit into a frame, S. This is determined by the frame rate and the transmitter/receiver internal characteristics. In low speed simple ADCs, S is often set to 1. For high speed, complex ADCs, the value of S should be based on two things. 1) the JESD204 data rate which equals (M x ADC sample rate)/(ADC decimation factor) and 2) the desired frame clockrate. The value of S is then determined by dividing the JESD204 data rate by the frame rate. Let’s look at some examples. Consider a simple ADC with no decimation with sample rate = to 156.25 MHz. The desired frame clock rate is 156.25 Mhz, which means S = 1. Now consider two ADCs with decimation = 2 and a sample rate of 625 MHz. The desired frame clock rate would be 156.25 MHz which means S = (2 x 625 MHz) / 2 / 156.25 Mhz = 4.
  • Now we must ask how many lanes are needed, L. This is determined by the maximum required line rate per lane. The line rate per lane can be calculated by the following equation where fs = sample rate per S samples: Lane Line Rate = (M x S x N’ x 10/8 x fs) / L. Let’s again look at some examples. Consider a single 14 bit ADC with 1 sample at 312.5 MHz (M=1, S=1, N’=16, and fs=312.5 MHz). With L = 1, the lane line rate = 6250Mbps and with L = 2, the lane line rate = 3125 Mbps. Consider now two 12 bit ADCs with 2 samples each (as in I/Q) with sample rate equal to 625 Mhz (M=2, S=2, and fs=625MHz). With N=12 and L=4, the lane line rate = 9375 Mbps. With N=16 and L=4, the lane line rate = 12500 Mbps. With N=12 and L=8, the lane line rate=4687.5Mbps. And with N = 16 and L=8, the lane line rate = 6250 Mbps.
  • Next we look at how many octets are transmitted per frame, F. This is calculated from the equation F = (M x S x N’) / (8 x L). For example, a single 14-bit ADC with 1 sample on one lane (M=1, S=1, N’=16, and fs=312.5MHz), F would be (1 x 1 x 16) / (8 x 1) = 2. Last, we ask if high density mode is being used, if so then HD = 1. When in low density mode partial conversion words at the end of a group of F octets are avoided by adding tail bits. If high density mode is used, then conversion words may break at the frame boundary.
  • Once we have all the link parameters set, we need to take a look at frequency relationships that need to be determined. First the line rate was calculated from step 5 on slide 26. Remember that was Lane Line Rate = (M x S x N’ x 10/8 x fs) / L. The character clock is then the Line Rate divided by 10. From earlier, we calculated the frame clock from the word size N’ and the number of samples per frame S. To then derive the multi-frame clock, divide the frame clock by K, where K is an integer number of frames and must be chosen so that the number of octets in a multi-frame not fall below 17.
  • We have discussed in a good bit of detail general methods for maintaining good signal quality. Let’s now take a look at how signal quality is measured. In serial differential interfaces, the eye diagram is a common measurement of the integrity of the signal. Shown here is the transmitter eye diagram for JESD204 operating at speeds up to 3.125 Gbps. The table at the top of the slide gives the details on timing, voltage levels, impedances, and return loss. The table to the bottom left of the slide gives timing as it relates to the figure at the bottom right. The figure at the bottom right is commonly referred to as an eye mask. The signal must not encroach onto the beige area of the figure, but must stay in the white at all times. The tables define the conditions for which the transmitter must meet the eye mask. I would encourage you download the slides when they are made available to study this further.
  • Here, the receiver eye mask and specifications are shown, again for speeds up to 3.125 Gbps. This is very similar to what was shown on the previous slide for the transmitter. The main difference you will note here is that the eye mask has relaxed limits for the transition areas and for the maximum and minimum voltage levels. This is due to the slowing down and attenuation of the signal as it crosses the physical media (i.e. board, connector, transmission line) between the transmitter and the receiver.
  • To summarize, the JESD204 standard has evolved and continues to evolve to meet current and new converter interface requirements. As it continues to evolve, improvements are being made to make a more scalable and robust standard. The JESD204 standard was introduced and is being used because of the increasing resolution and speed of converters. As the resolution and speed increase, the standard continues to scale and push the data rates from 3.125 Gbps up to 6.375 Gbps and even higher. As these speeds increase, physical design is of utmost importance. The use of good design practices for transmission lines becomes important. Properly terminating the system becomes a key consideration. One must know and understand the return current paths in a design. And, it is imperative to be able to measure and understand measurements of signal integrity so that a properly working JESD204 system can be designed and implemented. Finally, ADI is aware of the increasing demand in the marketplace for JESD204 compliant products and is positioning its ADC and DAC portfolio with new products to meet that demand. Be on the look out for new products with JESD204B.
  • I have included here a list of references used for this presentation. I encourage you to read through these when you have some spare time.
  • In order to access the material referenced, I have included some good links here to help you in your studies in understanding JESD204 and its application techniques. There are very good resources for JESD204 information listed here as well as some great websites with information on high speed design.
  • Last, I would like to acknowledge several folks here at Analog Devices for their contributions to this presentation.

Demystifying the JESD204B High-speed Data Converter-to-FPGA interface Presentation Transcript

  • 1. The World Leader in High Performance Signal Processing SolutionsDemystifying the JESD204 High SpeedConverter-to-FPGA InterfaceJonathan HarrisProduct Applications EngineerHigh Speed A/D Converter GroupApril 20121
  • 2. Seminar Overview Background and discussion of JESD204 standarddevelopment and revision notes Overview of the link structure and lane configurations in thedifferent revisions of the JESD204 standard (focus onJESD204A/B) Overview of the key signals and layers in the JESD204standard (focus on JESD204A/B) Brief discussion of practical layout considerations for highspeed converter interfaces2
  • 3. Why JESD204? Simplification of overall system design Smaller/lower number of trace routes, easier to route board designs Reduction in pin count – Both the Tx and Rx side Move from high pin count low speed parallel interfaces to low pincount high speed serial interfaces Embedded clock incorporated to even further reduce pin count Reduction in system costs Smaller IC packages and board designs lead to lower cost Easily scalable to meet future bandwidth requirements As geometries shrink and speed increases, the standard adapts3
  • 4. What is the JEDEC Standard 204 (JESD204) JESD204 is a standard defining a multi-gigabit serial data linkbetween converters and a receiver (commonly FPGA or ASIC) JESD204 (April 2006) – original standard defining 1 lane, 1 link Defined transmission of samples across a single serial lane formultiple converters at speeds up to 3.125 Gbps4
  • 5. What is the JEDEC Standard 204 (JESD204A) JESD204A (April 2008) – 1st revision expanding standard tomultiple links and multiple lanes Revision adds capability for multiple aligned serial lanes formultiple converters at speeds up to 3.125 Gbps5
  • 6. What is the JEDEC Standard 204 (JESD204B) JESD204B (August 2011) – 2nd revision utilizes a device clockand adds measures to ensure deterministic latency Supports multiple aligned serial lanes for multiple converters atspeeds up to 12.5 Gbps6
  • 7. Key Aspects of JESD204 Standards 8b/10b Embedded Clock DC balanced encoding which guarantees significant transitionfrequency for use with Clock and Data Recovery (CDR) designs Encoding allows both data and control characters - Control characterscan be used to specify link alignment, maintenance, monitoring, etc. Detection of single bit error events on the link Serial Lane Alignment Using special training patterns with control characters, lanes can bealigned across a “link” Trace to trace tolerance may be relaxed relative to synchronoussampling parallel LVDS designs Serial Lane Maintenance/Monitoring Alignment maintained through super-frame structure and use of specific“characters” to guarantee alignment. Link quality monitored at receiver on lane by lane basis. Link established and dropped by receiver based on error thresholds.7
  • 8. Key Signals in JESD204 SystemsJESD204A Frame Clock – A clock signal in thesystem equal to the frame rate of thedata on the link. In JESD204Asystems the frame clock is themaster timing reference. SYNC~ – A system synchronous,active low signal from the receiver tothe transmitter which denotes thestate of synchronization. Lane 0, … ,L-1 – Differential laneson the link. (Typically high speedCML) 8B/10B code groups are transmitted MSBfirst/LSB last.JESD204B Device Clock – A clock signal in thesystem which can be used to derivethe frame rate of the data on thelink. In JESD204B systems theframe clock is no longer the mastersystem reference. SYNC~ – Same as JESD204Aexcept synchronous to Local Multi-Frame Clock (LMFC) instead of theframe clock. Lane 0, … ,L-1 – Same asJESD204A. SYSREF (optional) – An optionalsource-synchronous, high slew ratetiming resolution signal responsiblefor resetting device clock dividers(including LMFC) to ensuredeterministic latency.8
  • 9. Key Signals in JESD204A Systems frame clock A clock signal in the system equal to the frame rate of the data on the linkThis is the master timing reference SYNC~ A system synchronous, active low signal from the receiver to thetransmitter which denotes the state of synchronizationSynchronous to the frame clock in JESD204AWhen SYNC~ is low, the receiver and transmitter are synchronizingSYNC~ and frame clock should have similar compliance in order toensure proper capture/transmission timing (i.e. LVDS, CMOS, CML)SYNC~ signals may be combined if multiple DACs/ADCs are involved Lane 0, … ,L-1 Differential lanes on the link. (Typically high speed CML)8B/10B code groups are transmitted MSB first/LSB last9
  • 10. Key Signals in JESD204B Systems Device clock Each transmitter and receiver derives its device clock from a master clockgenerator circuit May have different period than the frame or multiframe period – if so, the deviceis responsible for generating the frame or multiframe clock from the device clock SYNC~ Same as in JESD204A, but synchronous to the local multiframe clock SYSREF One-shot, “gapped periodic” or periodic - must be synchronous to device clock Distributed to both converters and ASIC/FPGA logic devices (receivers) in thesystem. When available, SYSREF is the master timing reference in JESD204B systemssince it is responsible for resetting the LMFC references in the system. Lane 0, … ,L-1 Differential lanes on the link. (Typically high speed CML)8B/10B code groups are transmitted MSB first/LSB last10
  • 11. Key Layers in JESD204 Standards Transport Layer Maps conversion samples to/from framed,non-scrambled octets Scrambling Layer Optional scrambling/descrambling ofoctets to reduce EMI effects by spreadingspectral peaks Data Link Layer Encoding/Decoding of optionallyscrambled octets to/from 10-bit characters Handles special control charactergeneration/detection for lane alignmentmonitoring and maintenance Physical Layer Serializer/Deserializer (SERDES) layerresponsible for Tx/Rx of characters at linerate speeds. Includes drivers, receivers,Clock & Data Recovery (CDR), etc.11
  • 12. JESD204 Simplified System ViewSimplified View of Data Flow in a JESD204 System12
  • 13. JESD204 Transport Layer The transport layer mapsconversion samples to/from framed,non-scrambled octets for 4 primarymappings. A single converter to a single-lane link A single converter to a multi-lane line Multiple converters in the same deviceto a single-lane link Multiple converters in the same deviceto a multi-lane link Conversion samples arerecommended to be mapped toJESD204 Words on 4-bit nibbleboundaries. The diagram on the right shows themapping of converter samples tooctets for each lane.13
  • 14. JESDx 204 Scrambling Layer Between the Transport layer and theLink Layer exists a datascrambler/descrambler The data scrambler is implemented tolower the spectral peak emissions on thelanes between the transmitter block andreceiver block. The scrambler uses a self synchronousscrambling pattern with polynomial =1+x14+x15 Data is scrambled prior to the 8B/10Bencoder and descrambled after decoding. As the scrambling pattern is self-synchronous, the two shift registers atinput and output need not be set to thesame initial state for scrambling to work. The descrambler will always “catch-up”and self-synchronize to the scramblerafter two octets of data. The scrambling block should have theability to be bypassed as not all systemswill require it.14ScramblerDescrambler
  • 15. Data Link Layer – How is a link established? There are three distinct phases of link establishment: 1. Code Group Synchronization (CGS) In this phase, each receiver must locate K28.5 characters in its input data stream usingClock and Data Recovery (CDR) techniques. Once a certain number of consecutive K28.5 characters have been detected on all linklanes, the receiver block de-asserts the SYNC~ signal to the transmitter block. In JESD204A, the transmit block captures the change in SYNC~ and after a fixednumber of frame clocks, starts the Initial Lane Alignment Sequence (ILAS). In JESD204B, the transmit block captures the change in SYNC~ and starts the InitialLane Alignment Sequence (ILAS) on the next LMFC boundary. 2. Initial Lane Alignment Sequence (ILAS) The main purpose of this phase is to align all the lanes of the link and verify theparameters of the link. During ILAS, the link parameters are sent to the receiver device to designate how datawill be sent to the receiver block. ILAS consists of 4 or more multi-frames. The last character or each multi-frame is amulti-frame alignment character /A/. The first, third, and fourth multi-frames begins with an /R/ character and end with an /A/character. The data in between them is ramp data. The receiver uses the final /A/ ofeach lane to align the ends of the multi-frames within the receiver. The second multi-frame contains an /R/ and /Q/ character followed by link parameters.15
  • 16. Data Link Layer – How is a link established? There are three distinct phases of link establishment: 2. ILAS - continued Additional multi-frames can be added to ILAS if needed by the receiver. After the last /A/ character of the last ILAS multi-frame, User Data starts. In systems were no inter-lane skew management is needed, ILAS can be bypassedgiven both the transmitter and receiver support the mode. 3. User Data In this phase, user data is streamed from the transmitter block to the receiver block. Data can be optionally scrambled, yet scrambling does not start until the very first octet followingthe ILAS. The receiver block processes and monitors the data it receives for errors including: Incorrect running disparity (8B/10B error) Not in Table (8B/10B error) Unexpected control-character Incorrect ILAS Inter-lane skew error - This is monitored through a practice called character replacement If any of these errors exists, it is reported back to the transmitter in one of a few ways. SYNC~ assertion – Resynchronization (SYNC~ pulled low) is called for at each error. SYNC~ reporting – The SYNC~ is pulsed high for a frame clock period if an error occurs. Reporting may also be done via interrupt if so equipped. This is not covered by the spec.The following slide shows the three phases of link establishment16
  • 17. Data Link Layer – Link EstablishmentDDADK=K28.5 code group synchronization comma characterA=K28.3 lane alignment symbolF=K28.7 frame alignment symbolR=K28.0 start of Multi-FrameQ=K28.4 start of link configuration dataC= JESD204 link configuration parametersD=Dx.y data symbolLMFC=Local Multi-Frame ClockD D D A R Q C CD D AD R D D D ADADADR D D D ADCode Group Synchronization Initial Lane Alignment Sequence User DataKKKMulti-Frame = K FramesRFDFDFDFDFDFDFDFDFDFDFDFDFDFMulti-Frame = K Frames Multi-Frame = K Frames Multi-Frame = K FramesMulti-Frame = K Frames Multi-Frame = K Frames Multi-Frame = K FramesReceiverDe-assertsSYNC~
  • 18. Data Link Layer – Lane Alignment During ILAS, the Data Link layers are responsible for aligning lanes in thereceiver: Placement of /A/ characters in ILAS are used to align lanes in the receiverblock. JESD204 A and B specifications require that /A/ characters be separatedby >17 octets. This allows a large amount of system skew to be mitigated. Skew is defined in JESD204 A and B for three possible setups: One transmitter block and one receiver block. Multiple transmitter blocks and one receiver block. (Multiple converters drivingone Logic Device) One transmitter block and multiple receiver blocks. (one Logic Device drivingmultiple DACs)18
  • 19. Data Link Layer – Character Replacement Once the User Data phase has been reached, Character Replacement in theData Link Layer allows frame and lane alignment to be monitored andcorrected. Character Replacement is performed on both Frame and Multi-FrameBoundaries: Transmitter Character Replacement: Frame based – If the last character of a frame is identical to the last character of theprevious frame on a given lane (or equals 0xFC if scrambling is enabled), then thetransmitter will substitute the character with an /F/ character. Multi-frame based – If the last character of a multiframe is identical to the last character ofthe previous frame on a given lane (or equals 0x7C if scrambling is enabled), then thetransmitter will substitute the character with an /A/ character. Receiver Character Replacement: The receiver must do the exact opposite from the transmitter. If an /F/ or /A/ character is detected, it is replaced with the final character of the previousframe If scrambling is enabled, /F/ characters are replaced with 0xFC and /A/ characters with0x7C. If /A/ and /F/ characters are found in incorrect places, then the receiver canrealign the lanes on the fly. Data will be corrupted during this operation.19
  • 20. Data Link Layer – Character Replacement Implications of character replacement/realignment /A/ and /F/ characters may not come along that often, so if data goes bad itmay take a while for the receiver to know. Garbage data might be sent for some period of time. If the error is in the CDR or high speed link somewhere, the 8B/10B errordetector is expected to see it well in advance. If realignment is supported, each lane can realign to an /A/ or /F/character. The JESD204A specification makes comments about realigning characters oralignment counters on the fly. Unless either transmitter or receiver skipped a character clock, this should notbe a problem. Where would this make sense? This makes sense for sparse data systems, or packet systems, where datacan be lost. For systems with dense data transfer, realignment will be preceded by astream of garbage data.20
  • 21. Data Link Layer – Monitoring Errors Apart from alignment errors, other errors may occur on the link and need tobe reported to the transmitter. Incorrect running disparity- As the transmitter and receiver are both keeping track of the running disparityof the 8B/10B code, the receiver can tell when it is not correct. Not in Table Error If the current character of the 8B/10B code is not in the table of 8B/10Bcharacters, this error is generated. Unexpected control-character A control-character that is not expected has been found in a given position. Code Group Sync error Wrong length, wrong structure, mismatched link parameters, etc. These four errors are required by the JESD204A/B specification as aminimum error set to be detected. The designer may chose to supportmore.21
  • 22. JESD204 Physical Layer The Physical Layer (PHY) is where characters are transmittedand received at line rate speeds This layer includes Serial/Deserializer (SERDES) blocks, drivers,receivers, Clock and Data Recovery (CDR)Often designed using custom cells due to high speed of data transfer JESD204 and JESD204A supported speeds up to 3.125 Gbps JESD204B will supports 3 speed grades Speed Grade 1: up to 3.125 GbpsBased on Optical Internetworking Forum OIF-SxI5-0.10 specification Speed Grade 2: up to 6.375 GbpsBased on Optical Internetworking Forum CEI-6G-SR specification Speed Grade 3: up to 12.5 GbpsBased on Optical Internetworking Forum CEI-11G-SR specification22
  • 23. JESD204 Physical Layer Comparison23Parameter OIF-SxI5-01.0 CEI-6G-SR CEI-11G-SRLine Rate ≤ 3.125 Gbps ≤ 6.375 Gbps ≤ 12.5 GbpsOutput Differential Voltage(mVppd)500 (min)1000 (max)400 (min)750 (max)360 (min)770 (max)Output Rise/Fall Time (ps) > 50 > 30 > 24Output Total Jitter (pp UI) 0.35 0.30 0.30 High speed, fast rising signals place tighter constraints onboard level design Careful attention needed for trace impedance, trace lengths,layer stackup, etc. A good set of physical design rules is imperative
  • 24. Deterministic Latency in JESD204B Latency can be defined as deterministic when the time from theinput of the JESD204 transmitter to the output of the JESD204receiver is consistently the same number of clock cycles In parallel implementations, deterministic latency is rathersimple – clocks are carried with the data In serial implementations, multiple clock domains exist whichcan cause non-determinism JESD204 and JESD204A do not contain provisions forguaranteeing deterministic latency JESD204B specifies three device sub-classes: Device Sub-class 0 – No support for deterministic latency Device Sub-class 1 – Deterministic latency using SYSREF (above 500 MSPS) Device Sub-class 2 – Deterministic latency using SYNC~ (up to 500 MSPS)24
  • 25. Deterministic Latency Using SYNC~Deterministic latency can be guaranteed using onlyFrame Clock and SYNC~ in lower speed converters. When link synchronization is achieved, the RX de-asserts SYNC~ to theTX and the TX captures it with the frame clock. The latency in the transmitter from the SYNC~ capture point to thebeginning of the ILAS must be constant (same requirement as specifiedby JESD204A section 5.3.5.4). Since the RX has information about when it de-asserted SYNC~ and theTX turn around delay is required to be constant, once the RX receives theILAS, then the latency of the forward path is known and can be corrected. Note: SYNC~ signaling is system synchronous (timing of system maydepend on interaction of multiple devices) and must meet setup and holdtime relative to the frame sample edge at the transmitter or issues willoccur.25
  • 26. Deterministic Latency Using SYSREF As the sample rates are pushed higher, it is desirable to use source synchronousinterfaces (timing of system depends on interaction of two devices) whereverpossible. The optional SYSREF (source synchronous) signal is used in the JESD204Bspecification in order to: Future proof the specification for higher sample rate converters. Provide the highest level of accuracy with the lowest complexity. In JESD204B, SYSREF will: Align internal dividers from device clocks at converters. Act as the master system reference to align all Local Multi-Frame Clocks (LMFC). These LMFCsources are used throughout the system to ensure deterministic latency. Either be low speed periodic, gapped periodic, or one-shot. In the RX, SYNC~ is launched from the LMFC edge instead of the frame clock edge. In the TX, ILAS (and hence /A/ character timing) is launched from the LMFC edgeinstead of the frame clock edge. SYNC~ is effectively now asynchronous to frame clock and system synchronous tothe LMFC. System is effectively 100% source synchronous.26
  • 27. JESD204 Link Parameters/Characters Link Parameters L – Number of lanes per converter device M – Number of converters per converter device S – Number of transmitted samples per converter per frame N’ – Number of transmitted bits per sample (JESD204 word size) N – Number of conversion bits per converter F – Number of octets per frame HD – High density user data format 8B/10B Control Characters /K/ – K28.5 character used for code group synchronization /F/ – K28.7 character used for frame alignment /A/ – K28.3 character used for multi-frame alignment /R/ – K28.0 character used to begin multi-frame /Q/ – K28.4 character used to begin lane parameter data in InitialLane Alignment27
  • 28. JESD204 Terminology octet – a group of 8 bits, serving as input to 8B/10B encoderand output from the decoder nibble – a set of 4 bits which is the base working unit ofJESD204 specifications character – a 10 bit symbol generated by the 8B/10Bencoding scheme character clock – a clock running at the character rate used toprocess the characters of a system code group – a set of 10 bits in the serial data stream used toconvey octets Running disparity – the measure of current DC imbalance onthe link used to code and decode 8B/10B code groups28
  • 29. JESD204 Terminology Frame – a set of consecutive octets in which the position ofeach octet can be identified by reference to a frame alignmentsignal frame clock – a system clock which runs at the frames rate.In JESD204A systems, the frame clock is the absolute timingreference in the system multi-frame – a set of consecutive frames in which thepositions of the frames can be identified relative to a multi-frame alignment character Multi-frame clock or Local Multi-Frame Clock (LMFC) – a clockin the system which runs at the multi-frame rate anddetermines the location of multi-frame characters which areused for lane alignment. Typically this clock is a dividedversion of the frame clock which is local to thetransmitter/receiver. In JESD204B systems, this clock is theabsolute timing reference.29
  • 30. JESD204 Terminology lane – a differential pair between transmitter and receiver data link or link – a set of data lanes which provide a conduitfor data to be transferred from transmitter to receiver mult-point link – a data communication link with three or moredevices. These three devices may be two transmitters andone receiver or may be two receivers and one transmitter. transmitter – a single lane’s worth of encoding, serialization,and driving transmitter block – all transmitters for a link receiver – a single lane’s worth of capture, deserialization,and decoding receiver block – all receivers for a link converter – a single converter in a package converter device – a package with one or more converters30
  • 31. Setting up JESD204 Link Parameters1) How many converters do you have in the device (M)?2) What is the converter sample resolution in the device (N)?i.e. a 12-bit converter would set N = 123) What is the JESD204 word size (N’)?• The converter sample resolution is broken down into nibbles. 12bit converters have 3 nibbles while 14 and 16 bit converters have4 nibbles. Multiply the number of nibbles by 4 to determine thevalue of N’. It can be advantageous to have N’ = 16 so that 8-16bit converters can be handled with the same transmitter/receiver.• A non-complete nibble is padded with either Control Bits (CS) orTail bits (T) and must satisfy: N’ = N + CS + T• A 12-bit converter with a 16-bit JESD204 word size leaves 4 bits foreither control bits and/or tail bits31
  • 32. Setting up JESD204 Link Parameters4) How many samples easily fit into a frame (S)?• Determined by the frame rate and the transmitter/receiverinternal characteristics. For low speed simple converters, oftenS is set to 1. For high speed, complex converters, the value of Sshould be based on:• the JESD204 data rate = (M x ADC sample rate) / (ADC decimationfactor)• the desired frame clock rate• The value of S is determined by:• S = (JESD204 data rate) / Frame Clock Rate (FC)• Example 1: Simple ADC (no decimation) with sample rate =156.25 MHz (JESD204 data rate = 156.25 MHz), the desired frameclock rate = 156.25 MHz then S = 1• Example 2: A dual ADC (with decimation = 2) with sample rate =625 MHz, the desired frame rate = 156.25 MHz thenS = (2 x 625 MHz) / 2 / 156.25 MHz = 432
  • 33. Setting up JESD204 Link Parameters5) How many lanes are needed (L)?• Determined by the maximum required line rate per lane. The linerate per lane can be calculated by the following equation (whereFC = frame clock rate):• Lane Line Rate = (M x S x N’ x 10/8 x FC) / L• Example 1: A single 14-bit ADC with 1 sample @ 312.5 MHz (M =1, S = 1, N’ = 16, and FC = 312.5 MHz)• With L = 1, the lane line rate = 6250 Mbps• With L = 2, the lane line rate = 3125 Mbps• Example 2: Two 12-bit ADCs with 2 samples per frame clock (I/Q)@ 625 MHz (M = 2, S = 2, and fs = 625 MHz)With N = 12, L = 4, the lane line rate = 9375 MbpsWith N = 16, L = 4, the lane line rate = 12500 MbpsWith N = 12, L = 8, the lane line rate = 4687.5 MbpsWith N = 16, L = 8, the lane line rate = 6250 Mbps33
  • 34. Setting up JESD204 Link Parameters6) How many octets are transmitted per Frame (F)?• This is calculated by the following equation:F = (M x S x N’) / (8 x L)• Example: A single 14-bit ADC with 1 sample on one lane (M = 1,S = 1, N’ = 16, and fs = 312.5 MHz)F = (1 x 1 x 16) / (8 x 1) = 27) Is High Density mode being used (HD)?• If samples are ever split between lanes, then HD = 134
  • 35. Clock Frequency Relationships JESD204 Once link parameters are set, certain frequency relationshipsneed to be determined Line Rate (Bit Rate) – effective data rate of the serial linkCalculated from step 5 Character ClockCalculated from: Line Rate / 10 Frame ClockCalculated from steps 3 and 4 Multi-Frame Clock (MFC)Calculated from: Frame Clock / K Where K is an integer number of frames and must be chosen such that thenumber of octets in a multi-frame not fall below 1735
  • 36. Signal Integrity Measurements – Tx Eye DiagramSymbol Parameter Condition Min Max UnitUI Unit Interval Baud Rate (BR)= 1/UI 320 3200 psTR/TF Rise and Fall Times 20-80% into 100 Ω load 50 Eye Mask psVdcm Transmitter Common ModeVoltageRequired only if DC complianceis claimed0.72 1.23 VZdse Single-Ended Impedance At DC 35 65 ΩZddiff Differential Impedance At DC 75 125 ΩRLdse Single-Ended Return Loss From 0.004*BR to 0.75*BRrelative to 50 Ω7.5 dBRLddiff Differential Return Loss From 0.004*BR to 0.75*BRrelative to 100 Ω7.5 dB36Parameter Value UnitXT1 0.175 UIXT2 0.45 UIYT1 0.50 UIYT2 0.25 UIDJ 0.17 pp UITJ 0.35 pp UI
  • 37. Signal Integrity Measurements – Rx Eye Diagram37Parameter Value UnitXR1 0.28 UIXR2 0.39 UIYR1 0.5 UIYR2 0.0875 UIDJ 0.32 pp UITJ 0.56 pp UISymbol Parameter Condition Min Max UnitVrcm Input Common Mode Voltage Required only if DC compliance is claimed 0.70 Vtt VVtt Termination Voltage Required only if DC compliance is claimed 1.10 1.30 VZtt Vtt Source Impedance At DC - 30 ΩZrdiff Receiver Differential impedance At DC 75 125 ΩRLrdiff Differential Return Loss From 0.004*BR to 0.75*BR relative to 100 Ω 10 dB
  • 38. Summary JESD204 has evolved and continues to evolve into a solid standardto meet current and new converter interface requirements As the standard progresses, improvements are being made tomake the serial link more scalable and robust As resolution and speed of converters increase the standard mustprogress towards faster data rates Current speeds are pushing data rates up to 3.125 Gbps and futurespeeds are looking toward 6.375 Gbps and higher As the standard progress towards faster data rates, physical designbecomes increasingly important Good design of transmission lines becomes imperative Proper terminations are a necessity Understanding of return current paths is crucial Measuring and understanding measurements of signal integrityimportant to design a robust JESD204 system ADI is positioning its ADC and DAC portfolio to meet customerdemands for JESD204 compatible products38
  • 39. Backup Slides – Additional Information39
  • 40. References JESD204 Serial Interface for Data Converters, April 2006. JESD204A Serial Interface for Data Converters, April 2008. JESD204B Serial Interface for Data Converters, August 2011. System Interface Level 5: Common Electrical Characteristicsfor 2.488-3.125 Gbps Parallel Interfaces - OIF-SxI5-01.0,October 2002. Common Electrical I/O (CEI) – Electrical and JitterInteroperability agreements for 6G+ bps and 11G+ bps I/O –OIF-CEI-02.0, February 2005. (particularly CEI-6G-SR) “Right The First Time, A Practical Handbook on High SpeedPCB and System Design”, Lee Ritchey, 2006.40
  • 41. Helpful Information and Links http://www.jedec.org/sites/default/files/docs/JESD204B.pdf Free Download - registration required http://www.oiforum.com/public/documents/OIF-SxI5-01.0.pdf Optical Internetworking Forum 0IF-SxI5-01.0 specification http://www.oiforum.com/public/documents/OIF_CEI_02.0.pdf Optical Internetworking Forum OIF-CEI-02.0 (includes CEI-6G-SR) http://www.analog.com/jesd204 Analog Devices JESD204 parts and information www.xilinx.com/support/documentation/user_guides/ug024.pdf Some useful information about using JESD204A from Xilinx http://www.speedingedge.com/ Good information about high speed design from Lee Ritchey http://www.signalintegrity.com/ More good information about high speed design from HowardJohnson41
  • 42. Acknowledgements Matthew Courcy, Analog Devices Brad Jeffries, Analog Devices Matthew McShea, Analog Devices Robert Sneed, Analog Devices Rob Reeder, Analog Devices David Buchanan, Analog Devices Michael Cobb, Analog Devices42
  • 43. Deterministic Latency Using SYNC~K=K28.5 code group synchronization comma characterA=K28.3 lane alignment symbolF=K28.7 frame alignment symbolR=K28.0 start of Multi-FrameQ=K28.4 start of link configuration dataC= JESD204 link configuration parametersD=Dx.y data symbolLMFC=Local Multi-Frame Clock – determines alignment character (/A) locationsKKKKKK R D D D A R Q C CD D ADKKKL Transit LanesTX LMFCTX DeviceSYNC~ @TXRX DeviceDeterministic Delay from SYNC~ to TX LMFC (ILAS) start(and /A character generation) in Frame Clock DomainKKKKKK R D D D A R Q C CD D AD R D DKKKRX LMFCKKKKKK R D D D A R Q C CD D AD R D DKKKL Receive Lanes(earliest arrival)L Receive Lanes(latest arrival)K KKKKKKK KKKKKKKK R D D D A R Q C CD D AD R D DKKKL AlignedReceive Lanes KKKKK KKSYNC~ @RXDeterministic Delay from SYNC~ to RX LMFC inFrame Clock DomainKK2 Character Elastic Buffer Delay of Latest Arrival6 Character Elastic Buffer Delay of Earliest ArrivalR D D D ADDe-assertion of SYNC~ based on RX LMFC + Tdelay determined by 1) Max A-Priori TXDelay + 2) Max A-Priori RX Delay + 3) Extra Timing Margin
  • 44. Deterministic Latency Using SYSREFK=K28.5 code group synchronization comma characterA=K28.3 lane alignment symbolF=K28.7 frame alignment symbolR=K28.0 start of Multi-FrameQ=K28.4 start of link configuration dataC= JESD204 link configuration parametersD=Dx.y data symbolLMFC=Local Multi-Frame Clock – determines alignment character (/A) locationsKKKKKK R D D D A R Q C CD D ADKKKL Transit LanesTX LMFCTX DeviceSYNC~ @TXRX DeviceKKKKKK R D D D A R Q C CD D AD R D DKKKRX Delayed LMFCKKKKKK R D D D A R Q C CD D AD R D DKKKL Receive Lanes(earliest arrival)L Receive Lanes(latest arrival)K KKKKKKK KKRX Delayed LMFC aligned to 1) Max A-Priori TX Delay + 2) Max A-Priori RXDelay + 3) Extra Timing MarginKKKKKK R D D D A R Q C CD D AD R D DKKKL AlignedReceive Lanes KKKKK KKSYNC~ @RXDeterministic Delay from SYSREF to RX Delayed LMFCstart (and /A character generation) in Frame Clock DomainKK2 Character Elastic Buffer Delay of Latest Arrival6 Character Elastic Buffer Delay of Earliest ArrivalSYSREF @TXKKKKK KAsynchronous De-assertion of SYNC~ causes start of ILAS on nextLMFC boundary and must not occur near TX LMFC boundary.SYSREF orSYSREF2 @RXRX LMFCDeterministic Delay from SYSREF to LMFC start(and /A character generation) in Frame Clock DomainDeterministic Delay from SYSREF to RX LMFC startin Frame Clock DomainKKKKK KKKKKKKK KKKKKKK KAsynchronous De-assertion of SYNC~must occur directly after RX LMFCR D D D AD