Integrated Software Defined Radio (Design Conference 2013)
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Integrated Software Defined Radio (Design Conference 2013)

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This session combines the high speed analog signal chain from RF to baseband with FPGA-based digital signal processing for wireless communications. Topics include the high speed analog signal chain, ...

This session combines the high speed analog signal chain from RF to baseband with FPGA-based digital signal processing for wireless communications. Topics include the high speed analog signal chain, direct conversion radio architecture, the high speed data converter interface, and FPGA-based digital signal processing for software-defined radio. Demonstrations use the latest generation Analog Devices’ high speed data converters, RF, and clocking devices, along with the Xilinx Zynq-7000 SoC. Other topics of discussion include the imperfections introduced by the modulator/ demodulator with particular focus on the effect of temperature and frequency changes. In-factory and in-field algorithms that reduce the effect of these imperfections, with particular emphasis on the efficacy of in-factory set-and-forget algorithms, are examined.

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Integrated Software Defined Radio (Design Conference 2013) Presentation Transcript

  • 1. Integrated Software Defined RadioReference Designs and Systems Applications
  • 2. Legal Disclaimer Notice of proprietary information, Disclaimers and Exclusions Of WarrantiesThe ADI Presentation is the property of ADI. All copyright, trademark, and other intellectual property andproprietary rights in the ADI Presentation and in the software, text, graphics, design elements, audio and allother materials originated or used by ADI herein (the "ADI Information") are reserved to ADI and itslicensors. The ADI Information may not be reproduced, published, adapted, modified, displayed, distributedor sold in any manner, in any form or media, without the prior written permission of ADI.THE ADI INFORMATION AND THE ADI PRESENTATION ARE PROVIDED "AS IS". WHILE ADI INTENDS THEADI INFORMATION AND THE ADI PRESENTATION TO BE ACCURATE, NO WARRANTIES OF ANY KIND AREMADE WITH RESPECT TO THE ADI PRESENTATION AND THE ADI INFORMATION, INCLUDING WITHOUTLIMITATION ANY WARRANTIES OF ACCURACY OR COMPLETENESS. TYPOGRAPHICAL ERRORS ANDOTHER INACCURACIES OR MISTAKES ARE POSSIBLE. ADI DOES NOT WARRANT THAT THE ADIINFORMATION AND THE ADI PRESENTATION WILL MEET YOUR REQUIREMENTS, WILL BEACCURATE, OR WILL BE UNINTERRUPTED OR ERROR FREE. ADI EXPRESSLY EXCLUDES ANDDISCLAIMS ALL EXPRESS AND IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR APARTICULAR PURPOSE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTYRIGHTS. ADI SHALL NOT BE RESPONSIBLE FOR ANY DAMAGE OR LOSS OF ANY KIND ARISING OUT OFOR RELATED TO YOUR USE OF THE ADI INFORMATION AND THE ADI PRESENTATION, INCLUDINGWITHOUT LIMITATION DATA LOSS OR CORRUPTION, COMPUTERVIRUSES, ERRORS, OMISSIONS, INTERRUPTIONS, DEFECTS OR OTHER FAILURES, REGARDLESS OFWHETHER SUCH LIABILITY IS BASED IN TORT, CONTRACT OR OTHERWISE. USE OF ANY THIRD-PARTYSOFTWARE REFERENCED WILL BE GOVERNED BY THE APPLICABLE LICENSE AGREEMENT, IFANY, WITH SUCH THIRD PARTY.©2013 Analog Devices, Inc. All rights reserved.2
  • 3. Today’s AgendaSoftware Defined Radio (SDR) OverviewMath Behind SDR Zero-IF or direct-conversion transmitter/receiver Brief introduction to digital modulationHow to Solve Channel Impairments Imperfections introduced by the modulator/demodulator with particular focus onthe effect of temperature and frequency changes In-factory and in-field algorithms will be examined that can reduce the effect ofthese imperfections, and particular focus is placed on the efficacy of in-factoryset-and-forget algorithmsSolutions for SDR FMComms1 board Tools, drivers, and example HDL designs3
  • 4. What Is a Software Defined Radio?A software defined radio system (SDR) is a radio communicationsystem where components that have been typically implemented inhardware(e.g., mixers, filters, amplifiers, modulators/demodulators, detectors) are instead implemented by means of software on a personalcomputer or embedded system.While the concept of SDR is not new (circa ~1970 DoD labs), manytechniques which used to be only theoretically possible are nowbeing implemented due to the rapidly evolving capabilities of analogand digital electronics. Why SDR? Makes RF hardware easier Easy to add new features, since they are all in software Easier to have one set of hardware handle multiple modulation techniques4
  • 5. Direct Conversion Technique (FMComms1)5ClockGenerator /SyncClockDistributionFrequencySynthesizerADL5375 ADL5602ADL5380AD8366AD9643AD9548 AD9523-1ADF4351LPC(32Data+3CLKLVDS)FMCConnector(500MHz)FPGADevelopmentPlatformRFOutRFIn`Slave Clock InSync InDAC16-Bit1250MSPS*AD9122Modulator400 – 6000MHz20dB Fixed Gain50 – 4000MHzADC14-Bit250MSPS0.25dB Step Size600MHz BandwidthDemodulator400 – 6000MHzOutput: 1 – 1000MHzInput: 1 – 750MHzOutput: 35 – 4400MHzADL5605/6700 - 1000MHz1800 – 2700MHzπ πFrequencySynthesizerMaster Clock Out16 + 1 LVDSPair @1000 Mbps500MHz (DDR)16 + 1 LVDSPair @500 Mbps250MHz DDRπ Pi networkSolder bump jumperSSSSS1 LVDSPair50MHzRef ClockSMA connectorI2C / USBto SPISPISPI SPI SPISPISPISPIPower5V @500mAADL5523400MHz to 4000MHzLow Noise AmplifierTuned for FrequencyπTxRxRF output power control isaccomplished by adjustingbaseband dataOptional Front EndOptional Front end22-9dB0dB0dBNon-SMA connector• AD9122 DAC runs at 1000MSPS, due to max speed ofAD9523-1
  • 6. Direct Conversion (Zero-IF) TRxA direct-conversion transceiver, also known ashomodyne, synchrodyne, or zero-IF transceiver, is a radiotransceiver design that (de)modulates the radio signal using a localoscillator (LO) whose frequency is identical to, or very close to, thecarrier frequency of the intended signal. Carrier frequency = local oscillator (LO) frequency Attractive due to simplicity of the signal path Suitable for high levels of integration Allows wider bandwidth designs6
  • 7. Homodyne Transmitter Advantages andChallengesAdvantages: Low component count leads to lower system cost and power consumption Direct up-conversion produces less mixing product spurs Requires fewer filtersChallenges: During the analog modulation process, gain and phase mismatches of IQsignals have a direct impact on sideband suppression performance Out of band transmissions LO / carrier leakage I/Q mismatch causes image in the output spectrum• This results in degraded error vector magnitude (EVM) at thereceiver, which in turn degrades the bit error rate (BER)7
  • 8. Homodyne Receiver Advantages andChallengesAdvantages: Low component count leads to lower system cost No image reject filter needed Filtering requirements more relaxed at baseband Gain stages at baseband provide power savingsChallenges: DC offset appearing at baseband Self mixing Offset voltages Images appearing symmetrically about zero frequency I/Q mismatches in phase and amplitude Even order nonlinearities Two high frequency interferers close to the channel of interest can result ineven order nonlinearities that fall within the band of interest8
  • 9. Back to Basics: Euler’s FormulasSin 0t is 90 out of phase with respect to cos 0t With perfect amplitude and phase matching the signal content at- 0 cancels9
  • 10. Amplitude and Phase MismatchAmplitude Mismatch Phase Mismatch00A+B2A-B2Desired SignalImage10
  • 11. Error Vector Magnitude—EVMMkMkkRkRkZEVM1212)()()(11 Noise and Imperfections in transmit and receive signal chains result in demodulatedvoltages which are displaced from their ideal location. Error Vector Magnitude expresses this dislocation Large EVM will result in Symbol Errors and degraded Bit Error Rate Higher Order Modulation Schemes  Symbols Closer Together  EVM More CriticalIdeal (Reference) SignalPhase Error (I/Q Error Phase)Magnitude Error (I/Q Error Mag)IQActualSignalfUnit = %
  • 12. Effects of Gain, Offset, and Phase Errors-1.5 -1 -0.5 0 0.5 1 1.5-1.5-1-0.500.511.5-1.5 -1 -0.5 0 0.5 1 1.5-1.5-1-0.500.511.5-1.5 -1 -0.5 0 0.5 1 1.5-1.5-1-0.500.511.5fLO+10% QuadratureGain ErrorfLO1oQuadraturePhase ErrorfLO+1% QuadratureOffset Error12
  • 13. What Is Causing the Poor Quality of This DemodulatedConstellation? Very poor LO Quadrature Phase Split (in DMOD) DC Offset of the complete constellation (probably LO to RF leakage in Tx) Noise has enlarged the footprint of the constellation points (poor Receiver Noise Figure)SymbolDecisionThresholdIf the symbol landson the edge or outsideof the box, bit errors willoccur13
  • 14. Effects of I/Q Mismatchf1f0 f2-f0-f1-f2 0DesiredSignalIdealGain Error IdealPhase Error** EVM Degradation **** Images Occupy BW ** ** Interfere with Desired Signal **14
  • 15. Direct Conversion Transmitter Architecture15ADL5375 ADL5602RFOutDAC16-Bit1250MSPS*AD9122Modulator400 – 6000MHz20dB Fixed Gain50 – 4000MHzADL5605/ADL5606700 – 1000MHz1800 – 2700MHzπ π16 + 1 LVDSPair @1000 Mbps500MHz (DDR)SPI0dB0dB
  • 16. Complex IF Using IF DACsA complex IF architecture uses IF DACs to synthesize an IF signaland its complex conjugate as the inputs to a quadrature modulatorThis makes a single sideband (SSB) upconverter that rejects thenormal mixing product, easing the BPF filtering requirements16IF DACIF DACPA BPFBPFRF RFIFIFRFRF 0LO 90LOFsFs
  • 17. Complex IF Imperfections Complex IF systems create several images: FDAC – FOUT: the main desired signal’s image Harmonics (2nd, 3rd, etc.), real or folded These must be low pass filtered prior to the quadrature modulator Careful frequency planning must be done to avoid folded products falling too close tothe desired signal that are then upconverted Post-modulator, a band pass filter is used to filter the undesired products17IF DACIF DACIFRF 0LO 90FsIF FsRFLOimageharmonic
  • 18. Causes of Non-Ideal Sideband Suppressions18
  • 19. Fixes for Non-Ideal Issues19MULTICHIPSYNCHRONIZATIOND15P/D15ND0P/D0NDATARECEIVERFIFO HB1 HB2 HB3NCOANDMODfDATA/2PREMODHB1_CLKMODEHB2_CLKHB3_CLKINTPFACTORPHASECORRECTIONINTERNAL CLOCK TIMING AND CONTROL LOGIC1616101616I OFFSETQ OFFSETINVSINCAUX1.2GDAC 116-BITIOUT1PIOUT1NAUX1.2GDAC 216-BITIOUT2PIOUT2NREFANDBIAS FSADJDACCLKPDACCLKNREFCLKPREFCLKNREFIO10GAIN110GAIN2DAC_CLKSERIALINPUT/OUTPUTPORTPROGRAMMINGREGISTERSPOWER-ONRESETSDOSDIOSCLKCSRESETIRQ01CLOCKMULTIPLIER(2× TO 16×)CLKRCVRCLKRCVRPLLCONTROLSYNCDAC CLK_SELDAC_CLKPLL_LOCKDCIFRAME08281-002INVSINC_CLKAD9122 Block Diagram
  • 20. Fixes for Non-Ideal Issues20Wanted SignalUnwanted ImageLO Feedthrough
  • 21. AD9122 Functional Block Diagram21MULTICHIPSYNCHRONIZATIOND15P/D15ND0P/D0NDATARECEIVERFIFO HB1 HB2 HB3NCOANDMODfDATA/2PREMODHB1_CLKMODEHB2_CLKHB3_CLKINTPFACTORPHASECORRECTIONINTERNAL CLOCK TIMING AND CONTROL LOGIC1616101616I OFFSETQ OFFSETINVSINCAUX1.2GDAC 116-BITIOUT1PIOUT1NAUX1.2GDAC 216-BITIOUT2PIOUT2NREFANDBIAS FSADJDACCLKPDACCLKNREFCLKPREFCLKNREFIO10GAIN110GAIN2DAC_CLKSERIALINPUT/OUTPUTPORTPROGRAMMINGREGISTERSPOWER-ONRESETSDOSDIOSCLKCSRESETIRQ01CLOCKMULTIPLIER(2× TO 16×)CLKRCVRCLKRCVRPLLCONTROLSYNCDAC CLK_SELDAC_CLKPLL_LOCKDCIFRAME08281-002INVSINC_CLK
  • 22. Premod/Filters/NCO22Increasing Interpolation Factor: Decreases fDATA, Decreases signal bandwidth Increases power ofDAC, decreases power of FPGA
  • 23. Digital Inside DACIncreasing interpolation factor: Decreases fDATA Decreases signal bandwidth Increases power of DAC Decreases power of FPGATrade off system levelperformance between FPGAprocessing and fixedprocessingDecreased system timingconstraints on FPGA23
  • 24. AD9122 Interpolation at a DAC Output241X2X4X
  • 25. AD9122 Digital Up-Conversion, DAC Out(DC -> 600 MHz)25Noupconversionf(DATA)/2upconversion8 x f(DATA)/7upconversion
  • 26. AD9122 Digital Up-Conversion at RF(Centre @ 2.4 GHz)26Noupconversionf(DATA)/2upconversion8 x f(DATA)/7upconversion
  • 27. When is This Useful?No ―cans‖ on top of Tx or Rxchains to isolate themAny interaction between Tx andRx PLLs will ―bleed into theother‖ when the frequencies arewithin 100 kHz (due to PCB sizeconstraints)27ClockDistributionFrequencySynthesizerADL5375ADL5380AD9523-1ADF4351Modulator400 MHz to 6000 MHzDemodulator400 – 6000MHzOutput: 1 – 1000MHzOutput: 35 – 4400MHzFrequencySynthesizerMaster Clock OutSPI SPISPIFigure ARx and Tx PLL 50 kHz different Figure BRx and Tx PLL 100 MHz different(RF is the same due to the DAC shift)ADF4351Tx Synthesizer35 MHz to 4400 MHzADF4351Rx Synthesizer35 MHz to 4400 MHz
  • 28. Receive ArchitecturesDirect (Zero-IF) ConversionCos(ωRF) Cos(ωRF)=1+Sin2(ωRF)Cos(ωSIG) Cos(ωSIG)=1+Sin2(ωSIG)LNA(t)=α1x(t)+α2x2(t)input(t)=A1Cos(ω1t)+A2Cos(ω2t)feedthrough(t)=α2A1A2Cos(ω2-ω1)tADL5380AD8366AD9643RFIn`ADC14-Bit250MSPS0.25dB Step Size600MHz BandwidthDemodulator400MHZ to 6000MHz16 + 1 LVDSPair @500 Mbps250MHz DDRSPISPIADL5523400MHz to 4000MHzLow Noise AmplifierTuned for FrequencyπRx-9dB28
  • 29. The Imperfect I/Q DemodulatorI/Q DEMODULATORLOINRFIN089.5G1G4G3G2fVo s1V fo s2IINQINImbalanceIn PhaseSplitterGainImbalance(G1,G2,G3,G4)OffsetVoltages29
  • 30. Imperfections in the I/Q Signal PathControlTuning900R +/- 5%R +/- 5%LPFLPFVoffset1Voffset2Voffset3Voffset4ADCADCOffsetswithin theDual ChannelADCPCB andLayoutMismatchesComponentMismatches30
  • 31. Critical IQ Demodulator Specs—LO to RFLeakageIf some of the LO leaks to the RF input, it mixes (multiplies) withitself in the mixer, generating unwanted dc offsets on top of therecovered baseband data streamADCLNADesired-70dBm0dBmLeakage-60dBm-40dBm-30dBm(~20mVp-p)A B CAssume,Gain from A to C =30dBLO to RF leakage ~ 60dBFLOFLOX31
  • 32. DC Offset and Quadrature Error CorrectionDC offset and quadrature error correction implementeddigitally at the end of the receive chain Most efficient approach in order to compensate for all potentialmismatches or errors in the signal pathDC Correction If DC free coding is used, a notch filter can be appliedQuadrature Error Correction Gain Correction Calculate I^2 – Q^2 to determine the power difference between I and Q. The power difference should be driven to zero. Phase Correction Perform a cross-multiply between I and Q. Can be viewed as a mixer. The DC term is proportional to the phasedifference between I and Q. By definition this should be zero if they are perfectly orthogonal.32
  • 33. SummaryDirect conversion or homodyne receivers have there own meritsand challengesGain, phase, and offset errors are a few of the challenges that canbe addressed with quadrature error correction algorithms Gain, phase, and offset errors cause degradations in receiver EVM andsensitivity Quadrature error correction will improve EVM and sensitivityDirect conversion offers advantages in power, cost, andperformance over IF sampling architecturesQuadrature error correction enables realizable direct conversionsolutions for macro level base stations/SDR platformsAnalog Devices’ first generation of QEC is available integrated intothe following products AD9262 – dual 16b continuous time sigma delta ADC AD9269 – dual 16b pipeline ADC33
  • 34. ClockingAD9523-1: multi-output, clockdistribution function with lowjitter performance,On-chip PLL and VCO with twoVCO dividersOn-chip VCOTwo cascaded PLL stages: First stage, PLL1, consists of an integerdivision PLL that uses an externalvoltage-controlled crystal oscillator(VCXO) from 15 MHz to 250 MHz. Second stage, PLL2, is a frequencymultiplying PLL that translates the firststage output frequency to a range of2.940 GHz to 3.125 GHz.ClockGenerator /SyncClockDistributionAD9548 AD9523-1Output: 1 – 1000MHzInput: 1 Hz - 750MHz50MHzRef ClockSPI SPI122.88MHz VCXOOn FMCOMMS134
  • 35. FMComms1 ClockingDAC_DCOADC_CLKDAC_REFCLKDAC_CLKN/CN/CN/CN/CLOGEN_TX_REFINADC_SYNCN/CLOGEN_RX_REFINN/CAssumes DAC isdoing nointerpolationOUT1 or OUT2OUT1 only35
  • 36. PLL2 Configuration122.88MHz983.04MHz983.04MHz122.88MHz1024.00MHz1024.00MHz Current config: 122.88 MHz / 1 * 24 = 2949.12 MHz 2949.12 MHz / 3 = 983.04 MHz 983.04 MHz / 4 = 245.76 MSPS (ADC) Possible config: 122.88 MHz / 1 * 25 = 3072.00 MHz 3072.00 MHz / 3 = 1024.00 MHz 1024.00 MHz / 5 = 204.8 MSPS (ADC) 1024.00 MHz / 8 = 128.0 MSPS (ADC) Possible config(max ADC rate): 122.88 MHz / 10 * 244 = 2998.272 MHz 2998.272 MHz / 3 = 999.4240 MHz 999.4240 MHz / 4 = 249.856 MSPS (ADC)36
  • 37. Possible FMComms1 Clocking37DAC_DCOADC_CLKDAC_REFCLKDAC_CLKN/CN/CN/CN/CLOGEN_TX_REFINADC_SYNCN/CLOGEN_RX_REFINN/CN/CAssumes DAC isdoing 8xinterpolationCan be 1024/n:• 204.80 MHz• 170.67 MHz• 146.29 MHz• 128.00 MHz• 113.78 MHz• 102.40 MHz• 93.09 MHz• 85.33 MHz• 78.77 MHz• 73.14 MHz• 68.67 MHz• 64.00 MHz• 60.23 MHz• 56.89 MHz• 53.89 MHz• 51.20 MHz• 48.76 MHz• 46.55 MHz• 44.52 MHz• 42.67 MHz• 40.96 MHzLoose Zero Delay, andno long can syncmultiple cards togetherOUT1 or OUT2OUT1 only
  • 38. PowerFMC provides 12 V, and 3.3 VSwitchers ADP2323LDOs ADP3335 ADP3333 ADP151 ADP150 ADP174038
  • 39. ADP2323: Ultrahigh Conversion Efficiency inCompact Solution Size Compact dual output solutionsize: 24 mm x 21 mm Heat dissipation is spreadevenly with the use of externallow-side Mosfet39 Ultrahigh and flat efficiency~95% with a 12 V input and a5 V output at 3 A load(ADP2323) Optional pulse frequencymodulation (PFM) reducesthe switching losses at lightload condition Possible configuration up to6 output rails in evenlyphase-shifted topology toreduce input ripplevoltage/current and minimizeinput capacitor size24mm21mm505560657075808590951000 0.5 1 1.5 2 2.5 3Efficiency[%]OutputCurrent [A]Efficiency at 12Vin, 300kHzVout=5VVout=1.2VVinA1A2ADP2323 (A)INTVCCSCFGSYNCSCFGSYNCSCFG100kΩ180kΩVinB1B2ADP2323 (B)SCFGSYNCSCFGSYNCVinC1C2ADP2323 (C)SCFGSYNCADP2323
  • 40. ADP2323: Configurability for Multi-RailApplications40 Reduces input ripple voltage/current and size of the input capacitorthrough phase shift. Avoids beat frequency interference in multi-railapplications Two/three ADP2323’s can be used for four/six output rails configurationConnect SCFG toINTVCC for clockoutputConnect SCFG with100/180kΩ resistorto GND for 60/120°phase shiftVinA1A2ADP2323 (A)INTVCCSCFGSYNCSCFGSYNCSCFG100kΩ180kΩ VinB1B2ADP2323 (B)SCFGSYNCSCFGSYNCVinC1C2ADP2323 (C)SCFGSYNCA1B1C160°120 °Without Phase Shift, Input Voltage Ripple = 142mVWith Phase Shift, Input Voltage Ripple = 86mVUp to 40%input voltageripplereductionInput Voltage Ripple Comparison with/without phase shift
  • 41. New ADI Low Noise High PSRR LDOs SummaryADM7160 (ES) Target power for >14B ADC 200 mA, 1.8, 2.5, 3.3 Vout 9 µV rms broadband noise Low tempcoADP7182 Neg VOUT LDO (ES) 200 mA, –30 Vin Adjustable from –1.22 V to –VIN PSRR 60 dB @10 kHz at VO = –3.3 VADP150 ADP151 (MP) 150 mA/200 mA, 5.5 Vin 9 µV rms broadband noise 20 nV/√Hz spectral eN @ 100 kHz 70 dB PSRR @ 10 kHz41ADP7102 ADP7104 (MP) 300 mA/500 mA, 20 Vin 15 µV rms broadband noise 35 nV/√Hz spectral eN @ 100 kHz 80 dB PSRR @ 10 kHz Power good outputADM7150 (1st Si) RF LDO (ES) 1.5 nV/√Hz spectral noise @ 100 kHz 800 mA, 4.5 to 16 Vin Vout Range: 1.5 V to 5.5 V 100 dB PSRR DC to 100 kHz 65 dB PSRR at 1 MHz 40 dB at 10 MHzMP Mass Production ES Engineering Samples, contact ADI
  • 42. ADP7102/ADP7104 – Low Noise Performance ADP7102/ADP7104 The ADP7104 noise does notincrease with output voltage No noise bypass required ~15 µV rms for all outputs420.010.111.E+01 1.E+02 1.E+03 1.E+04 1.E+05uV/rt-HzFreq (Hz)Noise Spectral Density3.3V5VRELEASED ADP7102/ADP7104 No added bypass capacitor required Stable with 1 µF output capacitor PSRR = 70 dB @ 1 kHz, 500 mA PSRR = 58 dB @ 10 kHz, 500 mA PSRR = 50 dB @ 100 kHz, 500 mA PSRR = 35 dB @ 1 MHz, 500 mA
  • 43. Spectral Density Noise Performance vs. FrequencyThe ADP151 1/f noise superior to competition below 100 HzCompetition noise somewhat better than ADP151 above 100 Hz430.0010.010.111010 100 1000 10000 100000Noise Spectral Density4.5V HMC860LP3E3.3V HMC860LP3EADP151-3.3VHMC976LP3E
  • 44. ADP151’s Ultralow Noise Advantage WhenPowering the ADF4350 Integrated PLL/VCO ChipNext slide compares phase noise vs frequency when powered byADP151, AA batteries, & the older generation ADP3334 LDO The ADP151 offers 1/3 the output noise of the ADP3334 LDORMS jitter is also improved Reduces from 1.23 ps to 0.87 ps by using ADP151 vs. the ADP3334ADP151 output noise 10 µV rms over 10 Hz to 100 kHz independentof Vout, no CNR requiredADP151 reduces PLL output phase noise (equivalent to reducedtiming jitter)44RELEASED
  • 45. PLL Phase Noise (at 4.4 GHz)vs. Frequency Offset45-120-110-100-90-80-70-601,000 10,000 100,000 1,000,000USB 1 x ADP3334SUPPLY 1 x ADP3334SUPPLY 1 x ADP150AA BATTERY (2 x 1.5V)PhaseNoise(dBc/Hz)HzADP151 Low Noise LDOand 2 x AA BatteryADP3334 LDO
  • 46. Traditional RF Evaluation Platforms(Antenna to Bits)46 Discrete single productevaluationboards, connectedwith wires 6 power supplies 4 different USBapplications Not easy toreplicate, or use aspart of a SDRprototyping solution Needed small formfactor, open design
  • 47. Current Prototyping PlatformsFMComms1 FMC Board47
  • 48. FMCOMMS1 Connected to Xilinx DevelopmentSystem ML605 (Virtex-6)48TopBottom
  • 49. FMC-Comms Board – Tx, Rx, Clocks, Power49RxTxRxTxAD9548Network ClockGenerator/SynchronizerAD9523-1Low Jitter ClockGeneratorAD9122DAC, 16-Bit,1250 MSPS*ADL5375Modulator400 MHz to 6000MHzADL560220 dB Fixed Gain50 MHz to 4000 MHzADF4351Tx Synthesizer35 MHz to 4400 MHzAD9643ADC14-bit , 250 MSPSAD83660.25dB Step Size VGA600MHz BandwidthADL5380Demodulator400 – 6000MHzADF4351Rx Synthesizer35 MHz to 4400 MHzFMCConnectorADC Inputs Clock SyncClock SyncInputsDAC Outputs +5 V Output forExternal AmpADP2323Dual 3 A Step-Down SwitcherADP7104High Accuracy500 mA LDOADP17402 A LDOADP17402 A LDOADP7104High Accuracy500 mA LDOADP151Ultralow Noise200 mA Linear RegulatorADP151Ultra Low Noise200 mA LinearRegulatorADG33044 Channel, Bidirectional,Logic Level Translator• AD9122 DAC runs at 1000MSPS, due to maxspeed of AD9523-1
  • 50. FMCOMMS1-EBZ Block Diagram50ClockGenerator /SyncClockDistributionFrequencySynthesizerADL5375 ADL5602ADL5380AD8366AD9643AD9548 AD9523-1ADF4351LPC(32Data+3CLKLVDS)FMCConnector(500MHz)FPGADevelopmentPlatformRFOutRFInSlave Clock InSync InDAC16-Bit1250MSPS*AD9122Modulator400 – 6000MHz20dB Fixed Gain50 – 4000MHzADC14-Bit250MSPS0.25dB Step Size600MHz BandwidthDemodulator400 – 6000MHzOutput: 1 – 1000MHzInput: 1Hz – 750MHzOutput: 35 – 4400MHzADL5605/ADL5606700 – 1000MHz1800 – 2700MHzπ πFrequencySynthesizerMaster Clock Out16 + 1 LVDSPair @1000 Mbps500MHz (DDR)16 + 1 LVDSPair @500 Mbps250MHz DDRπ Pi networkSolder bump jumperSSSSS1 LVDSPair50MHzRef ClockSMA connectorI2C/USBto SPISPISPI SPI SPISPISPISPIPower5V @500mAADL5523400 – 4000MHzLow Noise AmplifierTuned for frequencyπTxRxRF output power controlis accomplished byadjusting basebanddataOptional Front endOptional Front End22-9dB0dB0dBNon-SMA connector• AD9122 DAC runs at 1000MSPS, due to max speed ofAD9523-1
  • 51. Reference DesignsHDL: ML605 (Microblaze) KC705 (Microblaze) VC707 (Microblaze) ZC702 (ARM) ZC706 (ARM) Zed Board (ARM)Software: Linux Recommended solution Drivers for all programmableparts(AD9122, AD9548, AD9523-1, ADF4351, AD9643, AD8366) Streams data over network forMicroblaze platforms GTK+ based application for ARMbased platforms No-OS Basic drivershttp://wiki.analog.com/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl51
  • 52. System Level/Software Level Block Diagram52DACADCHDMISPDIFI2SFMCommsADV7511HDMI TxADAU1761AudioCodec512 MB DDR3Zed Board
  • 53. IIO Scope – Linux ApplicationVisualize Data: Control Things from GUI:53
  • 54. Tweet it out! @ADI_News #ADIDC13What We CoveredSoftware Defined Radio (SDR) OverviewHow to Solve Channel Impairments New features in ADI DACs and ADCs to solve these problemsSolutions for SDR FMComms1 board Tools, drivers, and example HDL designs Where to go to get things54
  • 55. Tweet it out! @ADI_News #ADIDC13Part number DescriptionAD9122 DUAL, 16-BIT, 1200 MSPS, TxDAC+® DIGITAL-TO-ANALOG CONVERTERADL5375 400 MHz TO 6 GHz BROADBAND QUADRATURE MODULATORADL5602 50 MHz TO 4.0 GHz RF/IF GAIN BLOCKAD9548 QUAD/OCTAL INPUT NETWORK CLOCK GENERATOR/SYNCHRONIZERAD9523-1 LOW JITTER CLOCK GENERATOR WITH 14 LVPECL/LVDS/HSTL/29 LVCMOS OUTPUTSADF4351 WIDEBAND SYNTHESIZER WITH INTEGRATED VCOAD9643 14-BIT, 170 MSPS/210 MSPS/250 MSPS, 1.8 V DUAL ANALOG-TO-DIGITAL CONVERTER (ADC)AD8366 DC TO 600 MHz, DUAL-DIGITAL VARIABLE GAIN AMPLIFIERSADL5380 400 MHz TO 6000 MHz QUADRATURE DEMODULATORADG3304 LOW VOLTAGE 1.15 V TO 5.5 V, 4 CHANNEL, BIDIRECTIONAL, LOGIC LEVEL TRANSLATORADP2323 DUAL 3A, 20V SYNCHRONOUS STEP-DOWN REGULATOR WITH INTEGRATED HIGH-SIDE MOSFETADP3335HIGH ACCURACY ULTRALOW QUIESCENT CURRENT, 500 mA, ANYCAP® LOW DROPOUTADP3333 HIGH ACCURACY ULTRALOW IQ, 300 mA, ANYCAP LOW DROPOUT REGULATORADP150 ULTRALOW NOISE, 150 MA CMOS LINEAR REGULATORADP151 ULTRA LOW NOISE, 200 mA CMOS LINEAR REGULATORADP1740 2 A, LOW VIN DROPOUT, LINEAR REGULATORFMComms1-EBZ FMC COMMUNICATIONSSelection Table of Products Covered Today55
  • 56. Tweet it out! @ADI_News #ADIDC13FMComms1 Demo in Exhibition HallUbuntu Linux on ZC702FMComms1 on FMCHDMI Display and USBKeyboard/MouseFull Transmit and Receive56Image of demo/boardThis demo board is available for purchase:www.analog.com/DC13-hardware
  • 57. Tweet it out! @ADI_News #ADIDC13Next StepsCome see the demoBuy the AD-FMComms1-EBZ Board(self assemble your own kit) $750Or buy the Avnet Kit – it’s in stock $1499 Avnet ZedBoard 7020 baseboard Xilinx ISE® WebPACK software with a device locked ChipScope license (device locked to XC7Z020) Analog Devices AD-FMCOMMS1-EBZ FMC module Linux drivers, applications software, HDL source, reference designs, full schematics, and Gerbers Two pulse LTE blade antennas (2500 MHz to 2700 MHz) 8 GB SD card Fan assembly, antenna, screws, and standoffsAsk questions on the EngineerZone http://ez.analog.com/community/fpgaCheck out the Wiki http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms1-ebz57