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High Speed Data Connectivity: More Than Hardware (Design Conference 2013)
 

High Speed Data Connectivity: More Than Hardware (Design Conference 2013)

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In wireless communications and data acquisition systems, there is more to consider when designing and implementing a complete solution beyond simply physically connecting a high speed analog module to ...

In wireless communications and data acquisition systems, there is more to consider when designing and implementing a complete solution beyond simply physically connecting a high speed analog module to an FPGA platform. Available hardware description language (HDL) components and software are critical to establish an interface, which is necessary for practical system integration. This session starts with a top-level overview of various physical interfaces that are typically used and provides an in-depth focus on high speed serial JESD204B. Prototype HDL used for these types of boards is covered, along with the specific board components and how they are used to interface to high speed ADCs and DACs. Linux device drivers for the HDL components as well as for the ADI components are presented. This includes a short introduction into the Industrial I/O (IIO) framework, the benefits it offers, and how it can be used in end designs.

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    High Speed Data Connectivity: More Than Hardware (Design Conference 2013) High Speed Data Connectivity: More Than Hardware (Design Conference 2013) Presentation Transcript

    • High Speed Data ConnectivityMore Than Hardware
    • Legal Disclaimer Notice of proprietary information, Disclaimers and Exclusions Of WarrantiesThe ADI Presentation is the property of ADI. All copyright, trademark, and other intellectual property andproprietary rights in the ADI Presentation and in the software, text, graphics, design elements, audio and allother materials originated or used by ADI herein (the "ADI Information") are reserved to ADI and its licensors.The ADI Information may not be reproduced, published, adapted, modified, displayed, distributed or sold inany manner, in any form or media, without the prior written permission of ADI.THE ADI INFORMATION AND THE ADI PRESENTATION ARE PROVIDED "AS IS". WHILE ADI INTENDS THEADI INFORMATION AND THE ADI PRESENTATION TO BE ACCURATE, NO WARRANTIES OF ANY KIND AREMADE WITH RESPECT TO THE ADI PRESENTATION AND THE ADI INFORMATION, INCLUDING WITHOUTLIMITATION ANY WARRANTIES OF ACCURACY OR COMPLETENESS. TYPOGRAPHICAL ERRORS ANDOTHER INACCURACIES OR MISTAKES ARE POSSIBLE. ADI DOES NOT WARRANT THAT THE ADIINFORMATION AND THE ADI PRESENTATION WILL MEET YOUR REQUIREMENTS, WILL BE ACCURATE, ORWILL BE UNINTERRUPTED OR ERROR FREE. ADI EXPRESSLY EXCLUDES AND DISCLAIMS ALL EXPRESSAND IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. ADI SHALL NOT BERESPONSIBLE FOR ANY DAMAGE OR LOSS OF ANY KIND ARISING OUT OF OR RELATED TO YOUR USE OFTHE ADI INFORMATION AND THE ADI PRESENTATION, INCLUDING WITHOUT LIMITATION DATA LOSS ORCORRUPTION, COMPUTER VIRUSES, ERRORS, OMISSIONS, INTERRUPTIONS, DEFECTS OR OTHERFAILURES, REGARDLESS OF WHETHER SUCH LIABILITY IS BASED IN TORT, CONTRACT OR OTHERWISE.USE OF ANY THIRD-PARTY SOFTWARE REFERENCED WILL BE GOVERNED BY THE APPLICABLE LICENSEAGREEMENT, IF ANY, WITH SUCH THIRD PARTY.©2013 Analog Devices, Inc. All rights reserved.2
    • Today’s AgendaHigh speed converter interface styles and standardsA closer look at the JESD204B converter-to-FPGA serial interfaceFPGA converter systems design support offerings Evaluation and reference design boards Software and device drivers HDL interface blocks Online technical support and documentation3
    • Microcontrollers to FPGAs to ASICs: Trade-OffsMicrocontroller DSP FPGA ASIC4Development CostPotential I/O PerformanceEase of DevelopmentBOM CostPotential Signal Processing and Converter Performance
    • ADC Output Configurations Parallel CMOS Fdata max = 150 MSPS DDR LVDS Fdata max = 420 MSPS Interface available in lowercost FPGAs Pins = ADC resolution plusDCO High pin count5ADC ADC ADCNPLL PLLFdataFdataFdataFs Fs FsFCLKDCODCO Fdata max = 1 + Gbps Serial LVDS Fs max = Fdata × # of datalanes/ADC resolution On-chip PLL required Medium to low-end FPGAtypically required Pins = # of data lanes plusFrame CLK and Data CLK Fdata = 6.25+ Gbps Encoded serial CML Fs max = data packetlength + overhead On-chip PLL required GT(x) ports on FPGArequired Aria, Kintex platforms, inaddition to high end Virtexand Stratix Two pins/lane, number oflanes depends on channels,speed, resolutionPARALLEL SERIAL LVDS SerDes/JESD204
    • Interface Styles and Standards:Control vs. DataHigh speed converters almost always have a separate controlinterface from the data interface Often SPI Occasionally I2C or pin-programmable Used to access register map of converter Runs much slower than data interface SPI often runs at <40 MHz (5 Mbps)Lower speed/precision converters may combine data and control Over SPI or I2COr, they may not have a control interface at all Pin-programmable No options6Often requires dedicated software device drivers to set up and control the converter
    • 7Why the Need for a High SpeedConverter-to-FPGA Serial Interface?Today’s solution Solution withJESD204A/JESD204Bserial interfaceFPGA34 WIRES18 WIRESTight timingrequirementsLarge number of I/OsTOANTENNA 134 WIRES18 WIRESTOANTENNA 2FPGATOANTENNA 1TOANTENNA 2Relaxedtiming requirementswith sync controlMinimum number of I/Os8SERIAL PAIRS1 to 2SERIAL PAIRS1 to 2SERIAL PAIRS14B ADC250 MSPSDUAL 16B DACDUAL16B DAC1.2 GSPS14B ADC250 MSPSDUAL 16B DACDUAL16B DAC1.2 GSPS14B ADC250 MSPS14B ADC250 MSPSQUAD16B DAC2 GSPS
    • Why the Need for a High SpeedConverter-to-FPGA Serial Interface?Simplification of overall system design Smaller/lower number of trace routes, easier toroute board designs Easier synchronizationReduction in pin count – both the Tx and Rx side Move from high pin count low speed parallel interfacesto low pin count high speed serial interfaces Embedded clock incorporated to even further reduce pin countReduction in system costs Smaller IC packages and board designs lead to lower costEasily scalable to meet future bandwidth requirements As geometries shrink and speed increases, the standard adapts8
    • What is JESD204?JESD204, a JEDEC defined standard forhigh speed, point to point, serial interface,used to interconnect two (or more) devices. ADC to digital receiver. Digital source to DAC. Digital source to digital receiver.How is it different than previous data converter interfaces? A single primary serial interface can be used to pass all data, clocking, andframing information. The clock and frame information are embedded in the data stream. No need to worry about set up and hold time between data and clock. One PCB trace (differential) can route all bits.9FPGADACDACADCADCClock
    • What is the JEDEC Standard 204 (JESD204)?JESD204 is a standard defining a multigigabit serial data linkbetween converters and a receiver (commonly FPGA or ASIC)JESD204 (April 2006) – original standard defining one lane, one link Defined transmission of samples across a single serial lane for multipleconverters at speeds up to 3.125 Gbps10
    • What is the JEDEC Standard 204 (JESD204A)?JESD204A (April 2008) – first revision expanding standardto multiple links and multiple lanes Revision adds capability for multiple aligned serial lanes formultiple converters at speeds up to 3.125 Gbps11
    • What is the JEDEC Standard 204 (JESD204B)?JESD204B (August 2011) – third version utilizes a device clockand adds measures to ensure deterministic latency Supports multiple aligned serial lanes for multiple converters at speedsup to 12.5 Gbps12MultipleConvertersUp to12.5 GbpsMultipleLanes
    • Key Aspects of JESD204x Standards 8b/10b Embedded Clock DC balanced encoding whichguarantees significant transitionfrequency for use with clock anddata recovery (CDR) designs Encoding allows both data andcontrol characters – control characterscan be used to specify link alignment, maintenance, monitoring, etc. Detection of single bit error events on the link Serial Lane Alignment Using special training patterns with control characters, lanes can be aligned acrossa “link” Trace-to-trace tolerance may be relaxed, relative to synchronous sampling parallelLVDS designs Serial Lane Maintenance/Monitoring Alignment maintained through super-frame structure and use of specific“characters” to guarantee alignment Link quality monitored at receiver on lane by lane basis Link established and dropped by receiver based on error thresholds13
    • Key Signals in JESD204A SystemsFrame Clock A clock signal in the system equal tothe frame rate of the data on the link. This is the master timing reference.SYNC~ A system synchronous, active low signalfrom the receiver to the transmitter which denotes the state of synchronization. Synchronous to the frame clock in JESD204A. When SYNC~ is low, the receiver and transmitter are synchronizing. SYNC~ and frame clock should have similar compliance in order to ensureproper capture/transmission timing (i.e., LVDS, CMOS, CML). SYNC~ signals may be combined if multiple DACs/ADCs are involved.Lane 0, … , L-1 Differential lanes on the link (typically high speed CML). 8B/10B code groups are transmitted MSB first/LSB last.14
    • Key Signals in JESD204B Systems Device Clock A clock signal in the system which is aharmonic of the frame rate of the dataon the link. In JESD204B systems, theframe clock is no longer the mastersystem reference. SYNC~ Same as JESD204A except synchronous to local multiframe clocks (LMFC) insteadof the frame clock. Lane 0, … , L-1 Same as JESD204A. SYSREF (Optional) An optional source-synchronous, high slew rate timing resolution signal responsiblefor resetting device clock dividers (including LMFC) to ensure deterministic latency. One shot, “gapped periodic” or periodic. Distributed to both ADCs/DACs and ASIC/FPGA logic devices in the system. When available, SYSREF is the master timing reference in JESD204B systemssince it is responsible for resetting the LMFC references.15
    • Deterministic Latency in JESD204xLatency can be defined as deterministic when the time from theinput of the JESD204x transmitter to the output of the JESD204xreceiver is consistently the same number of clock cyclesIn parallel implementations, deterministic latency is rather simple –clocks are carried with the dataIn serial implementations, multiple clock domains exist, which cancause nondeterminismJESD204 and JESD204A do not contain provisions for guaranteeingdeterministic latencyJESD204B looks to address this issue by specifying three devicesubclasses: Device Subclass 0 – no support for deterministic latency Device Subclass 1 – deterministic latency using SYSREF (above 500 MSPS) Device Subclass 2 – deterministic latency using SYNC~ (up to 500 MSPS)16
    • LVDS vs. CML17 The increased speed of the CML driver leads to a reduction in thenumber of drivers by enabling more channels per lane. With JESD204 providing up to an 80% lane reduction, the powerincrease of JESD204 CML is comparable to an LVDS implementation. LVDS Max data rate < 3.125 Gbps Low power consumption CML Max data rate ≤ 12.5 Gbps Higher power consumptioncompared to LVDS
    • High Speed Data Connectivity: SummaryHigh speed converters may only attach to FPGAs/ASICsHigh speed converter interfaces Converters typically feature a control and data path Data path: Require interface logic (HDL) Serial interfaces tend to be more sophisticated and, therefore, require moreknow-how and interface logic. Dedicated control interfaces typically 3-wire, 4-wire SPI SPI interface → uses standard IP cores However, often more than 100 registers, with lots of control bits Complexity is with the software and initialization values18DOCSHWHELPHDLSWRapid DevelopmentIntegration
    • FPGA Converter SystemsDesign Support Offerings19Evaluation andReference DesignBoardsSoftware andDevice DriversHDL InterfaceBlocksOnline TechnicalSupport andDocumentationFPGA DesignSupport
    • Evaluationand ReferenceDesign Boards
    • Native FMC Interface CardsFPGA Mezzanine Card, orFMC, as defined in VITA 57,provides a specificationdescribing an I/O mezzaninemodule with connection toan FPGA or other device withreconfigurable I/O capability.Analog Devices converterproducts can be found onmany boards, which useindustry standard FMCconnectors.21http://wiki.analog.com/resources/alliances/xilinx
    • AD-FMCJESDADC1-EBZAD-FMCJESDADC1-EBZ 2× dual, 14-bit, 250 MSPS ADC(AD9250) Clock tree (AD9517) 4 channels total Synchronized sampling acrossADCs Requires HPC-FMC (4 lanes ofGTX) for full performance Can work on LPC (1 lane) withreduced sample rate, and 1×AD9250 Works with Xilinx® 204B HDL ADI/Xilinx reference design ADI drivers available (Linux andNo-OS)22AD-FMCJESDADC1-EBZ
    • Using FPGA Evaluation Boards with ADIConvertersAdapter boards exist to allow customers to use some of ourstandard evaluation boards with various FPGA evaluation boards Customers are encouraged to use our evaluation platforms first, to becomefamiliar with the parts and their expected performance Adapter boards provide electrical connections only Reference designs exist (check wiki.analog.com)High speed ADCs Adapter boards for Xilinx (FMC-HPC) evaluation boards are available SPI is routed through FPGA evaluation board connector FPGA (firmware) controls SPI ADI part numbers: CVT-ADC-FMC-INTPZ23
    • FMC-ADC Interposer24High speedJESD204 and SPIinterfaceHigh speed parallelinterface(CMOS or LVDS)
    • AD-DAC-FMC-ADP25The AD-DAC-FMC-ADP adapterboard allows any of AnalogDevices DPG2-compatiable highspeed DAC evaluation boards tobe used on a Xilinx evaluationboard with an FMC connector.The adapter board uses the lowpin count (LPC) version of theFMC connector, so it can beused on either LPC or HPChosts.http://wiki.analog.com/resources/alliances/xilinx
    • System Demonstration Platform (SDP)InterposersFMC-SDP Interposer The FMC-SDP interposerallows any Analog DevicesSDP evaluation board orCircuits from the Lab®reference boards to be usedon a Xilinx evaluation boardwith an FMC connector. The interposer uses the lowpin count (LPC) version of theFMC connector, so it can beused on either LPC or HPChosts. The interposer can onlybe used with FPGA boardsthat support 3.3VIO for theFMC connection.26
    • Precision ADC Pmod Examples27PmodAD1—Two 12-bit ADC inputsAnalog Devices AD7476PmodAD2 —4 channel,12-bit ADCAnalog Devices AD7991Sampling rate: 1 MSPSResolution: 12-bitNo. of channels: 2Interface: SPIADC type: SARSampling rate: 1 MSPSResolution: 12-bitNo. of channels: 4Interface: I2CADC type: SARPmodAD4 —1 channel,16-bit ADCAnalog Devices AD7980PmodAD5 —4 channel,24-bit ADCAnalog Devices AD7193Sampling rate: 1 MSPSResolution: 16-bitNo. of channels: 1Interface: SPIADC type: PulSAR®Sampling rate: 4.8 kSPSResolution: 24-bitNo. of channels: 4Interface: SPIADC type: Σ-Δ
    • HDL Interface Blocks
    • FPGA ProjectsAnalog Devices provided HDL reference designs Native FMC converter cards FMC interposers—converter evaluation board combinations Pmods SDP or Circuits from the Lab® type cardsEach reference design consists of Complete FPGA design project Including HDL and Verilog IP cores for the various components Documentation on the Wiki No-OS device drivers, setup, and test code Linux device drivers where applicableSource of all information is the Analog Devices Wiki29
    • HDL IP Interface Core What function does it typicallyprovide: Drives converter control signals Samples data Abstracts and mediates data up in thehierarchy Pre and postprocessing Conversions Format, scale, offset, etc. Sign extention Extracting, selecting data Interface timing validation PN number checker Status, error tracking Overrange, DMA status Allows engineers to insert customIP, while maintaining the interfaceson both ends30ADCNFdataFsDCOAXIAXILiteAXIDMAConverterIPCoreCustomIP
    • Example HDL Blocks: HDMI Tx/Rx and SPDIF31 This reference designprovides the videoand audio interfacebetween the FPGAand ADV7511/ADV7611HDMI Tx/Rx. HDMI transmitter alsofound on various Xilinxevaluation boards: ZC702 ZC706 ZedBoard KC705, etc. Linux DRM, V4L2, ASoCdevice drivers available.ADI IP CoreXilinx IP Core
    • HDL Blocks: AD-FMCJESDADC1-EBZJESD204B serial interfaceReference design for: Virtex-7, Kintex-7, Virtex-6 KC705 ZC706 VC707 ML60532ADI IP CoreXilinx IP Core
    • Effect of FR4 Channel Loss at 3.25 Gbps33 At higher line rates, pre-emphasisand equalization techniques areused to compensate channel loss,due to the limited bandwidth of themedia. Equalization works at the receiverend while pre-emphasis on thetransmitter side. Selectively boost the high frequencycomponents in order to compensate thechannels high frequency roll off. Quality of the line cannot bedetermined by measuring the far-end eye opening at the receiverpins. Real-time oscilloscopes formultigigabit SerDes measurementscost $$$.3.25 Gbps – Ideal Source3.25 Gbps – After 40” FR4How to verify link reliability?
    • The Statistical Eye (2D Post Equalization) The Rx Eye Scan in Xilinx GTH, GTX, andGTP transceivers of 7 series FPGAsprovides a mechanism to measure andvisualize the receiver eye margin after theequalizer. Statistical eye scan functionality on per-lanebasis is based on comparison between thedata sample in the nominal center of theeye and the offset sample captured by anindependent and identical circuitry at aprogrammable horizontal and vertical offset. Bit error (BER) is defined as a mismatchbetween these two samples. Taking BER measurements at all horizontaland vertical offsets allows drawing a 2Deye diagram while enabling BER to bemeasured with high confidence down to10-15.34Nominal SampleOffset Sample
    • JESD204B High-Speed ADC Demo35Analog Devices’AD-FMCJESDADC1-EBZ 14-bit / 250MSPS4-ch ADCAD9250 HighSpeedJESD204BSerdes OutputsData Eye @5GbpsAnalog Input(Single-Tone FFT withfIN = 90.1 MHz)Ethernet dataconnection to PC forVerification ofAnalog Signal onVisualAnalog™Xilinx Kintex-7 FPGA KC705 Eval KitRecovered Eye(after EQ/CDR)
    • Software andDevice Drivers
    • Linux Kernel Basics Advantages of Linux Broad use as an open source desktop, server, and embedded OS Feature-rich Symmetric multiprocessing Preemptive multitasking Good RT performance Shared libraries Countless device drivers Memory management Support for almost any networking and protocol stack Support for multiple file systems Linux kernel is a free and open-source software Licensed under the GNU Public License Therefore, easy to extend and modify37Memory DevicesApplicationsCPUKernel
    • Linux Support for Xilinx FPGA Hard and SoftCoresFPGA Hard Core: Zynq Dual core ARM Cortex™-A9 PowerPC (PPC) Pros Avoids extra co-processor Fast data exchange between FPGA and CPU Less power, board space, and system cost Cons: May require external memoryFPGA Soft Core: Microblaze Pros Avoids extra co-processor Fast data exchange between FPGA and CPU A soft core can be customized to meet systemdemands Cons: Requires some extra gates and externalmemory May not be as fast as a hard core Power consumption38Linux is an ideal OS and a significant part of theecosystem for FPGA hard and soft cores
    • Linux Driver Model BasicsThe Linux driver modelbreaks all things down into: Buses Devices ClassesA bus can be described assomething with devicesconnected to it.A device class describescommon types of devices,like sound, network, or inputdevices, sometimes referredas subsystems.Examples of busesin Linux are: ACPI I2C IDE MDIO bus PCI/Express Platform (MEM mapped) PNP SCSI SERIO SPI USB39HardwareI2CHWMONSPIIIO
    • Linux Driver Model Basics Each device class defines a set ofsemantics and a programminginterface that devices of that classadhere to. Device drivers are typically theimplementation of that programminginterface for a particular device on aparticular bus. Device classes are agnostic withrespect to what bus a device resideson. The unified bus model includes a set ofcommon attributes which all busescarry, and a set of common callbacks,such as ideal device discovery duringmandatory bus probing, bus shutdown,bus power management, etc.Summarize: The Linux driver model provides acommon, uniform data model fordescribing a bus and the devicesthat can appear under the bus. Device drivers are agnostic withrespect to what processor platformthey run on, in case they areregistered with a common bus thatthe target platform supports.40
    • IIO—a New Kernel Subsystem for ConvertersThe Linux industrial I/O subsystem isintended to provide support for devices that,in some sense, are analog-to-digital or digital-to-analog converters Devices that fall into this category are: ADCs DACs Accelerometers, gyros, IMUs Capacitance-to-Digital converters (CDCs) Pressure, temperature, and light sensors, etc. Can be used on ADCs ranging from a SoC ADC to>100 MSPS industrial ADCs Mostly focused on user-space abstraction, but alsoin-kernel API for other drivers exists IIO to Linux input or HWMON subsystem bridges41
    • IIO Subsystem Overview42SYSTEM CALL INTERFACEVIRTUAL FILE SYSTEM (VFS)APPLICATIONCHARACTER DEVICEDRIVERHARDWAREKernel AreaApplicationAreaHardwareSYSFSDEVICE DRIVERIIO BUFFER IIO CORE IIO TRIGGERIIO SubsystemBUS DRIVERSIIO Device Drivers
    • AXI ADC Linux DriverEach and every IIO device,typically a hardware chip, has adevice folder under: /sys/bus/iio/devices/iio:deviceX. Where X is the IIO index of thedevice. Under every of thesedirectory folders resides a set offiles, depending on thecharacteristics and features of thehardware device in question.These files are consistentlygeneralized and documented inthe IIO ABI documentation. Inorder to determine which IIOdeviceX corresponds to whichhardware device, the user canread the name file: /sys/bus/iio/devices/iio:deviceX/name.43
    • IIO DevicesLinux—everything is a file IIO control via sysfs IIO data via device nodes /dev/iio:deviceXAttributes/files: Control converter modes Enable/disable channels Query data format, byte-order, alignment, index Query and set Sampling frequency Test modes Reference levels etc…44User Applicationint main(…){fd = open(/dev/iio:…);read(fd, buf, RCNT);…}
    • Example Device Driver: VGA/PGA Gain Control45out_voltage1_hardwaregain/sys/bus/iio/iio:device0/dev name out_voltage0_hardwaregain/sys/bus/iio/iio:device0 # cat namead8366-lpc/sys/bus/iio/iio:device0 # echo 6 > out_voltage1_hardwaregain/sys/bus/iio/iio:device0 # cat out_voltage1_hardwaregain5.765000 dBDevice attributesVery convenient for configuring andcontrolling devices using shell scriptsShell Commands:AD83660.25dB Step Size600MHz BandwidthSPI
    • AD9517-1 Multi-Output Clock Generator/Distribution Control46Outputs individuallycontrollable Enable/disable Set/get frequencyIIO device driver, but alsoregisters with the Linuxclock consumer/producerframework
    • JESD204B Receiver Interface Linux DeviceDriver47Ease of use Rx Eye Scan Nondestructive Implemented all in gates No runtime overheadDirect read access toJESD204 link parameters(ILA)Interface configuration viadevice treeaxi_jesd204b_rx4_0: axi-jesd204b-rx4@77a00000 {compatible = "xlnx,axi-jesd204b-rx4-1.00.a";reg = < 0x77a00000 0x10000 >;jesd,lanesync_en;jesd,scramble_en;jesd,frames-per-multiframe = <32>;jesd,bytes-per-frame = <2>;clocks = <&clk_ad9517 0>;clock-names = "out0";} ;Xilinx LogiCORE™ IP JESD204 core
    • Analog Devices 2D Statistical Eye ScanApplication Runs Natively on ZYNQ ZC70648 Graphical front end (GUI) JESD204B receiver interface Linux device driver
    • Data to VisualAnalog VisualAnalog™ is asoftware package thatcombines a powerful set ofsimulation, productevaluation, and dataanalysis tools with a user-friendly graphical interface Measure and visualize SNR, SFDR, THD, power,etc. IIO command client Control Linux IIO devicedrivers and capture data via aTCP network connection49
    • Online TechnicalSupport and Documentation
    • Analog Devices WikiThis Wiki provides developersusing Analog Devices productswith: Software and documentation HDL interface code Software device drivers Reference project examples forFPGA connectivityIt also contains user guides forsome Analog Devicesevaluation boards to helpdevelopers get up and runningfasthttp://wiki.analog.com/51
    • At Analog Devices, werecognize that our products arejust one part of the designsolution.We are supporting seamlessintegration of ecosystems andtools by offering HDL interfacecode, device drivers, andreference project examples forFPGA connectivity.This community is for thediscussion of these referencedesigns. http://ez.analog.com/community/fpga52FPGA Reference Designs Support Community
    • Analog Devices creates andmaintains Linux device driversfor various ADI products.Some software drivers are alsoavailable for ADI products thatconnect to microcontrollerplatforms without an OS.The purpose of this communityis to provide support for thesedrivers.To see the list of availabledrivers supported, visitthe Analog Devices Wikihttp://wiki.analog.comhttp://ez.analog.com/community/linux-device-drivers53LINUX and Microcontroller Device DriversSupport Community
    • Design Resources Covered in this SessionDesign Tools and Resources:Ask technical questions and exchange ideas online in ourEngineerZone™ Support Community Choose a technology area from the homepage: ez.analog.com Access the Design Conference community here: www.analog.com/DC13community57Name Description URLVisualAnalog http://www.analog.com/visualanalogAnalog DevicesWikiSoftware and documentationHDL interface codeSoftware device driversReference project examples for FPGA connectivityhttp://wiki.analog.com/[other]
    • Tweet it out! @ADI_News #ADIDC13Selection Table of Products Covered Today58Part number DescriptionAD-FMCJESDADC1-EBZFMC-based AD9250 evaluation boardCVT-ADC-FMC-INTPZ FMC to high speed ADC evaluation board adaptorAD-DAC-FMC-ADP FMC to high speed DAC evaluation board adaptorSDP-FMC-IB1Z SDP-to-FMC interposer board
    • Tweet it out! @ADI_News #ADIDC13Visit the AD9250-FMC JESD204B Demo in theExhibition Room AD9250-FMC250-EBZ card, connected to Xilinx development system(ZC706), streaming data to VisualAnalog (over Ethernet), to measureconverter performance (SNR, SFDR). Alternatively data can be visualized on a Linux desktop environment. HDMImonitor, mouse, keyboard connected to the ZC706. Concurrently measure and visualize the receiver eye margin on allJESD204B lanes. GO to Xilinx to find out more on LogiCORE™ IP JESD204 core.59This demo board is available for purchase:http://www.analog.com/DC13-hardware
    • What We CoveredOverview high speed converter interface styles and standardsDetailed look at the JESD204B interface standardAnalog Devices FPGA design support offerings60