Frequency Synthesis and Clock Generation for High Speed Systems (Design Conference 2013)
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Frequency Synthesis and Clock Generation for High Speed Systems (Design Conference 2013)

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Frequency synthesis and clock generation are now key elements in all aspects of high speed data acquisition and RF design.The primary types of frequency synthesizers—phase-locked loops (PLL) and ...

Frequency synthesis and clock generation are now key elements in all aspects of high speed data acquisition and RF design.The primary types of frequency synthesizers—phase-locked loops (PLL) and direct digital synthesizers (DDS)—are discussed along with the applications for which each is appropriate. Also covered are detailed aspects of synthesizer design. Other applications, such as clock distribution and translation are addressed, and problems associated with poor clocking are identified. Examples of poor clocking are shown along with the results of doing it properly.

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Frequency Synthesis and Clock Generation for High Speed Systems (Design Conference 2013) Frequency Synthesis and Clock Generation for High Speed Systems (Design Conference 2013) Presentation Transcript

  • Frequency Synthesis and ClockGenerationAdvanced Techniques of Higher Performance Signal Processing
  • Legal Disclaimer Notice of proprietary information, Disclaimers and Exclusions Of WarrantiesThe ADI Presentation is the property of ADI. All copyright, trademark, and other intellectual property andproprietary rights in the ADI Presentation and in the software, text, graphics, design elements, audio and all othermaterials originated or used by ADI herein (the "ADI Information") are reserved to ADI and its licensors. The ADIInformation may not be reproduced, published, adapted, modified, displayed, distributed or sold in any manner, inany form or media, without the prior written permission of ADI.THE ADI INFORMATION AND THE ADI PRESENTATION ARE PROVIDED "AS IS". WHILE ADI INTENDS THE ADIINFORMATION AND THE ADI PRESENTATION TO BE ACCURATE, NO WARRANTIES OF ANY KIND ARE MADEWITH RESPECT TO THE ADI PRESENTATION AND THE ADI INFORMATION, INCLUDING WITHOUT LIMITATIONANY WARRANTIES OF ACCURACY OR COMPLETENESS. TYPOGRAPHICAL ERRORS AND OTHERINACCURACIES OR MISTAKES ARE POSSIBLE. ADI DOES NOT WARRANT THAT THE ADI INFORMATION ANDTHE ADI PRESENTATION WILL MEET YOUR REQUIREMENTS, WILL BE ACCURATE, OR WILL BEUNINTERRUPTED OR ERROR FREE. ADI EXPRESSLY EXCLUDES AND DISCLAIMS ALL EXPRESS AND IMPLIEDWARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT OFANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. ADI SHALL NOT BE RESPONSIBLE FOR ANY DAMAGEOR LOSS OF ANY KIND ARISING OUT OF OR RELATED TO YOUR USE OF THE ADI INFORMATION AND THE ADIPRESENTATION, INCLUDING WITHOUT LIMITATION DATA LOSS OR CORRUPTION, COMPUTER VIRUSES,ERRORS, OMISSIONS, INTERRUPTIONS, DEFECTS OR OTHER FAILURES, REGARDLESS OF WHETHER SUCHLIABILITY IS BASED IN TORT, CONTRACT OR OTHERWISE. USE OF ANY THIRD-PARTY SOFTWAREREFERENCED WILL BE GOVERNED BY THE APPLICABLE LICENSE AGREEMENT, IF ANY, WITH SUCH THIRDPARTY.©2013 Analog Devices, Inc. All rights reserved.2
  • 3Today’s AgendaApplications areas for clocks and frequency synthesisDesign and application of phase-locked loops (PLLs)Design and application of direct digital synthesis (DDS)Clock generation and distributionIssues of clocking data converters
  • 4Five Types of Clocking Chips Analog PLLs Uses an analog multiplier as the phase detector Not in Wide Use Digital PLLs Use a digital phase frequency detector (PFD), analog loop filter, voltage controlled oscillator (VCO) Simple architecture Very high performance and low noise All-Digital PLLs Use a digital phase frequency detector (PFD), digital loop filter, NCO Increased flexibility for faster locking Excellent jitter cleaning Extremely flexible Direct Digital Synthesis Extremely flexible frequency generation Very fast frequency sweeping and hopping Very popular in military and instrumentation applications General oscillators Crystal oscillators Voltage-controlled oscillators (VCO)
  • 5What is a clock and what arethe common frequencies? Unlike a data waveform, a clock signal is a square wave whosefrequency is usually constant. Common frequencies include: 1 pps (pulse per second) used by GPS 8 kHz (commonly used in wired communcations) and is commonly referred toas a BITS clock 19.44 MHz is a common reference clock in synchronous optical (SONET)networks, and is still used in OTU (Optical Transport Unit) networks that arereplacing SONET 122.88 MHz is commonly used in wireless communications 125 and 156.25 MHz are common Ethernet reference clocks 32.768 kHz is the common watch crystal oscillator
  • 3.6Basic Phase Locked Loop (PLL) Model(B) STANDARD NEGATIVE FEEDBACKCONTROL SYSTEM MODEL(A) PLL MODELERROR DETECTOR LOOP FILTER VCOFEEDBACK DIVIDERPHASEDETECTORCHARGEPUMP FO = N FREF
  • August 2006 ADI Confidential Information7/2REFA /R1PhaseFreqDet(PFD)32 MHz< FPFD <44 MHzChargePumpLoop Filter(External)VCO/4 or 5/BOUTFeedback Divider(N Divider)/P/2 /R2ReferenceMonitor andcontrol LogicREFBREFFLAGVCOdivDigital PLL Block Diagram
  • 3.8Phase/Frequency Detector (PFD)Driving a Charge Pump (CP)D1 Q1CLR1CLR2D2 Q2V+V−HIHI+IN−INDELAYUPDOWNCP OUTIIU1U2U3PFDCPD1 Q1CLR1CLR2D2 Q2V+V−HIHI+IN−INDELAYUPDOWNCP OUTIIU1U2U3PFDCP(A) OUT OF FREQUENCY LOCK AND PHASE LOCK(B) IN FREQUENCY LOCK, BUTSLIGHTLY OUT OF PHASE LOCK0+I+I0(A) OUT OF FREQUENCY LOCK AND PHASE LOCK(B) IN FREQUENCY LOCK, BUTSLIGHTLY OUT OF PHASE LOCK0+I+I0UP100DOWN010CP OUT+ I−I0UP100DOWN010CP OUT+ I−I0(C) IN FREQUENCY LOCK AND PHASE LOCK
  • 3.9Adding an Input Reference Dividerand a Prescaler to the Basic PLL(A)(B)REFERENCEDIVIDERRREFERENCEDIVIDERRPRESCALERP
  • All-Digital PLL Detailed Block Diagram(AD9557 Shown)10SPI/I2CSERIAL PORTEEPROMREF MONITORINGAUTOMATICSWITCHING÷N1 ÷N2÷N3÷2 ÷M0OUT0OUT0OUT1OUT110-BITINTEGERDIVIDERSMAX 1.25GHz÷M1×2×2LFPFD/CPRF DIVIDER 1÷3 TO ÷11XO OR XTAL XO FREQUENCIES10MHz TO 180MHzXTAL: 10MHz TO 50MHzRF DIVIDER 2÷3 TO ÷11FOUT = 360kHz TO 1.25GHzINTEGER DIVIDEROUTPUT PLL (APLL)FRAC1/MOD117-BITINTEGER24b/24bRESOLUTION DIGITAL PLL (DPLL)÷2REGISTERSPACE2kHzTO1.25GHzR DIVIDER (20-BIT)SYNC RESET PINCONTROL M0 M1 M2 M3 IRQSPI/I2CDIGITALLOOPFILTERTUNINGWORDCLAMP ANDHISTORYFREERUNTWPLL2STATUSLF CAPPFD/CP LF3.34GHzTO4.05GHzDPFD30-BITNCOROMANDFSMMULTI-FUNCTION I/O PINS(CONTROL AND STATUSREAD BACK)SYSTEMCLOCKMULTIPLIER÷2AD9557REFAREFAREFBREFB09197-135All-Digital PLL CoreDigital PLL
  • 3.11Key PLL SpecificationsRF Input Frequency (Minimum/Maximum)Phase Noise and Phase JitterReference SpursFrequency Lock TimeOutput Frequency ErrorPhase Lock TimeOutput Phase ErrorLoop Bandwidth and Phase Margin
  • 3.12Integer-N Compared toFractional-N SynthesizerREFDIVIDERRPFD FILTER VCON COUNTERFREFF1FOUT10MHzR =500.2MHzN = 4501900.2MHzREFDIVIDERRPFD FILTER VCO"N" COUNTERFREFF1FOUT10MHzR =101MHz900.2MHzN =900.2"N" = NINTEGER +NFRACTIONNMODULUS= 900 +NFRACTION5FOUT = FREF (N/R)(A) INTEGER N(B) FRACTIONAL N
  • 13Common Uses for PLLs Frequency translation Jitter Cleanup Redundant clocking Holdover Clock Distribution
  • /2REFA19.44MHz/R1PhaseFreqDet(PFD)10 kHz< FPFD < 50MHzChargePumpLoop Filter(External)VCO/4 or 5/B156.25MHzFeedback Divider(N Divider)/P/2 /R2ReferenceMonitor andcontrol LogicREFBREFFLAGVCOdiv14Frequency Translation Example:19.44 MHz (SONET) to 156.25 MHz (10 Gb/s Ethernet): R divider=162, B=15625, VCO divider = 3, P divider = 4 Phase detector frequency: 120 kHz VCO frequency: 1875 MHz
  • 15Jitter Clean-upClean signal from mainclock boardBackplanehas lots ofnoisesources Clock received by linecard is contaminatedClock received from back plane isused to establish phase andfrequency of the outputSignal purity of the output isdependent upon the Localoscillator (Crystal, TCXO, orOCXO) used HOW?Digital PLL w/ aProgrammableDigital loopFilter capable of<1 Hz BW
  • Switchover and HoldoverHoldover:Holdover is the ability to provide output signals even when the reference input disappears.Holdover can be initiated either as directed by controller/processor elements in a system, orvia a provided monitoring function which will automatically switch into holdover mode whenthe reference input goes quiet.Switchover:Switchover provides additional security beyond the holdover function. If one of the referencesfails, the clock device will use one of the alternate references instead. An important aspect ofall the switchover functions provided in ADI clock devices is that no runt pulses and no extralong pulses result from this change. Downstream PLLs will not lose lock as a result, of orduring, switchover - even when no predefined relationship exists between the phases of thevarious reference input signals. Switchover can be initiated either as directed bycontroller/processor elements in a system, or via a provided monitoring function which willautomatically implement switchover when the active reference input goes quiet.
  • Switchover, Synchronization, and HoldoverNOTEoutput is synchronized to primaryreferenceBut what happens when theprimary reference disappears?The PLL will maintain the output clock in holdover until anotherreference input is available. The output phase may or may not slew(depending on the application) so that either the input-output phaseis the maintained or there is no output clock phase slewing.AD9548
  • 3.18TOOLS – Design, Simulation, Evaluation Full Range of Evaluation Boards for DDS, Clock Generation and Distribution, PLLs Available.Full suite of Windows-Compatible Software Availablehttp://www.analog.com/en/evaluation-boards-kits/resources/index.htmlhttp://www.analog.com/en/rf-tools/topic.htmlhttp://ez.analog.com/welcome
  • 3.19CLK Design and Simulation Softwarewww.analog.com/adisimclk
  • 3.20PLL Design and Simulation SoftwareVERSION 3.5www.analog.com/adisimpll
  • 3.21DDS Design Tool - ADIsimDDSwww.analog.com/adisimdds
  • Forums in22Get fast answers tonew questionsSearch existing contentfor immediate answershttp://ez.analog.com/community/ddshttp://ez.analog.com/community/clock_and_timinghttp://ez.analog.com/community/rf
  • 3.23Eval Software Frequency Planning Wizard:Enter your desired input and outputs…Input Frequency Window Output Frequency Window
  • 3.24The software configures the part for you…The Results Window
  • 3.25…and the registers are loaded.
  • Clocking Applications forPhase-locked Loops (PLLs)
  • 27AD9516 Family 1.5 -3.0 GHz, 8/5-Channel ClockDistribution ICsClock Outputs1.2 GHz LVPECL800 MHz LVDS250 MHz CMOSPLL Core250 MHz REFIN1.6 GHz PLLJitter Clean-upProgrammable DividersAny integer 1 to 32Phase offset controlEach divider independentProgrammable Delay AdjustFullscale from 1ns to 10ns32 delay steps64-LFCSPtypically replacesFive(5) discrete ICsAD9510 Shown Below, Broadband RMS Jitter <1ps
  • 28Application – Wireless Transceiver CardADCTRXClock Distribution ICADCADCADCDDC orASICDACDUC orFPGADACUser’sReferenceClockClock to A-D ConvertersClock to D-A ConvertersClock toDigital ChipsCritical Clock Functions on Transceiver Card:• clean-up jitter on user’s input reference• up-convert user reference frequency to highestfrequency needed, usually driven by DAC clockrequirements• generate multiple frequencies for RX & TX• provide low jitter clocks for converters• generate mix of LVPECL, LVDS, CMOS clocks• adjust phase or delay between clock channels• offer isolation between clock channelsTRX Cards
  • 29DigitalCrossPointClockGeneration/DistributionPowerSequencingLine CardSwitch CardXCVRCDRSERDESBackplaneSwitch& EQDigitalEngineOptical TransceiverTIALDDPINLaserLimitingAMPSignalConditionerApplication – Line CardSwitch CardLine CardBackplaneNew ADI clock products suchas the AD9557 and AD9548 aretailored for networkapplications.Specific AD9548 example onnext page
  • SyncE / IEEE1588 Hybrid(with Hooks for Pure IEEE1588)BackplaneLine CardAD9557AD9547TCXO /OCXO Recovered clocksfrom Line cardsBITSGPSTiming CardXO AD9553/7(Optional)TxRxCPU / FPGA / DSPIEEE1588Protocol / AlgorithmSPI/I2CMAC/PHYSyncE Clock Recovering+IEEE1588 Time StampTime StampsFrequencySynchronization1 PPSTiming Card 2Line Card nTime of Day Offset Adjustment1 PPSTime of DayClock/Frequency ControlAD9548
  • Using DDS For Clock Generation
  • 32Generating Clocks using DDSLimiterReconstructionFilterFsysclock(fc) DAC out Filter outClock outIdeal TimeDomainResponseIdealFrequencyDomainResponse"Real World"FrequencyResponset01 1 3 5 7Odd harmonic series1 3 5 7t tf ffffffcfc 2fc2fcDDSThe DDS chip can synchronize to a user’s reference. An on-chip clock multiplier cangenerate the fast clock needed to clock the NCO/DAC. A frequency tuning word may bewritten to set the output clock rate. External filtering removes unwanted images.A squaring function then converts sine wave to square wave.
  • 3.33A Flexible DDS SystemfcSERIALOR BYTELOADREGISTERnnFREQUENCY CONTROLPHASEREGISTERLPFDACPARALLELDELTAPHASEREGISTERM CLOCKn nPHASE ACCUMULATORnPHASETRUNCATION12-19 BITSAMPLITUDETRUNCATION2n=foM • fcN-BITSn = 24 - 48 BITSPHASE-TOAMPLITUDECONVERTERM = TUNING WORDSYSTEM CLOCK(10-14)6-bitphasewheel01234630243129……5-bitamplituderesolutionfovector dataraw DDS-DAC outputfiltered outputcompared output
  • 3.34Signal Flow Through the DDS ArchitectureREFERENCECLOCKPHASEACCUMULATOR(n-BITS)PHASE-TO-AMPLITUDECONVERTERDACMTUNING WORD SPECIFIESOUTPUT FREQUENCY AS AFRACTION OF REFERENCECLOCK FREQUENCYIN DIGITAL DOMAIN ANALOGNDDS CIRCUITRY (NCO)TOFILTER2n=foM • fc2n=foM • fcfc2n=foM • fcM = JUMP SIZE
  • 3.35AD9858 1GSPS DDSwith Phase Detector and Multiplier
  • 3.36DDS Single Loop UpconversionUsing the AD9858DDS1GHzDAC1032LPFDIVIDER1/2/4PHASE/FREQUENCYDETECTOR150MHzCHARGE PUMP0.5mA-2mA0.5mA STEPSLOOPFILTER ~DIVIDERKDC - 400MHzVCOf = K fREFDDS/DACCLOCKFREQUENCYTUNING WORDPART OFAD9858:fREFDC - 150MHz
  • DDS vs. PLLComparing: Advantage The rest of the storyFreq. Resolution DDS Fractional N PLLs shrink the gap, Programmable Modulusimproves DDS precisionFreq. Agility DDS Fast hopping PLLs shrink the gapPhase Resolution &AgilityDDS Digital PLLs can provide some level of phase control.Amplitude Resolution& AgilityDDSPower Consumption PLL Gap shrinks with geometry; interleaved coresOutput FrequencyRangePLLPrice PLL* Gap shrinks with geometry; in no small part this is due tothe breadth of adoption of PLL technology,Broad Spectral Purity PLLAncillary circuitry PLLFreq. Up-conversion PLL Super Nyquist operation and hybrids37
  • Hybrid configurationsDDSRefCLK PLL Upconverting PLLDDSRefCLK PLL RefCLK multipying PLLPLLDDSRefCLK DDS in feedback pathPLLDDSRefCLK DDS as a DCO38
  • 39Clocking Data ConvertersAbsolute accuracy needed for reproduction CD sound output would be off-tuneClock jitter leads to distortion
  • Effective Aperture Delay TimeMeasured with Respect to ADC InputSAMPLINGCLOCKANALOG INPUTSINEWAVEZERO CROSSING+FS-FS0V+te–tete
  • 41Jitter – common noise source introduced atSHA in A-D ConverterClock jitter is the sample to sample variationin the encode clock (both the external jitter as wellas the internal jitter).Fullscale SNR is jitter-limited by: See AN-501 and AN-756SHA = Sample & Hold AmplifierjitterrmsrmsjitterftNSSNR21log20log20
  • 4245.050.055.060.065.070.075.080.085.090.0100 100050 fs100 fs200 fs400 fs800 fsFullscale Analog Input (sinewave)84dB78dBAIN = 200 MHzEach line showsconstant RMSclock jitter infemtoseconds (fs)72dB66dB60dB300MHz400MHz500MHzSNR of ADC @ 200 MHzAIN varies with clock jitterSignaltoNoiseRatio(SNR)indBADCAnalogInputSampling ClockSNRDigitalOutputAs analog signal increases, clock jitter limits SNRjitterjitftSNR21log20
  • 2.43Additive RMS Jitter of Logic Gates/DriversFPGA (driver gates only) 33-50 ps**74LS00 4.94 ps *74HCT00 2.20 ps *74ACT00 0.99 ps *MC100EL16 PECL 0.7 ps **AD951x family 0.22 ps **NBSG16, Reduced Swing ECL (0.4V) 0.2 ps **ADCLK9xx, ECL Clock Driver Family <0.1 ps*** Calculated values based on degradation in ADC SNR** Manufacturers specification
  • By Architecture & PerformanceNon-PLLPLLExtVCOPLLIntVCOWideband RMS jitterADCLK944ADCLK905ADCLK907ADCLK925ADCLK946ADCLK948ADCLK950ADCLK954ADCLK914ADCLK846ADCLK854AD9512AD9514AD9515AD9513AD9508AD9510AD9511AD9516-5AD9520-5AD9522-5AD9516-0:4AD9517-0:4AD9518-0:4AD9520-0:4AD9522-0:4AD9523AD9524AD952550 fs 150 fs100 fs 200 fs 250 fs 300 fsAdditiveJitterAbsoluteJitterAD9523-1681012668101212814141212105561249332221 18Indicates # of outputsFront end loop of AD9523/4Uses external OscillatorAbsolute jitter includesoscillator performance andreference qualityAdditive jitter excludesoscillator performance andreference qualityADF4351ADF4360ADF4002, ADF4106Stand-Alone PLL+ Ext VCXO1 ps
  • 45Voltage-controlled OscillatorsProvide simplicity and versatilitySimple RC-adjustable oscillators for undemanding applicationsHigher frequencies require specialized design
  • 46Voltage-controlled OscillatorsADF5508
  • 3.47LOOPFILTERVCXOSystem Clock Distribution ExamplesADC FIFO122.88 MHz122.88 MHzLVPECL CMOSDELAY = 4.3nsHIGH SPEED MEASUREMENT SUBSYSTEMREFCLK491.52 MHzLVPECL30.72 MHzDACDACFPGALVDSCMOSCMOSQUADRATURE TRANSMIT SOURCE61.44 MHz61.44 MHzPHASE = 90DELAY = 10ns122.88MHzLVPECL491.52 MHzCLEAN_REFCLK30.72 MHzCALIBRATION15.36 MHzClock ICs simplify board designby integrating phase control,delay adjust, frequency dividers,and logic translationPHASE = 0TOYOCOM491.52 MHzAD9513/AD9514/AD9515 easy to designin. Require only a +3.3V supply. Allfunctionality selected by tying input pins toVS, GND, VREF, or NC
  • 3.48AD9512 1.2GHz Clock Distribution ICDelay 1-10ns1:5 FanoutBufferDivide by 1-32LVDS ORCMOSLVDS ORCMOS225 fs rms225 fs rms350 fs rms1-3 ps rmsArms jitter added tosignal at A225 fs rmsDivide by 1-32Divide by 1-32Divide by 1-32Divide by 1-32 LVPECLBufferLVPECLBufferLVPECLBufferTOTAL JITTER = J12 + J22 + J32 +...+JN2
  • 49ADI’s Complete Clock PortfolioDigital and All-Digital PLLs Used for frequency multiplication/translation Redundant Clocking and HoldoverSynthesizers Used for clock generationClock Distribution Used for sending the identical clock to multiple chips Also used for logic level translation (i.e., LVPECL to LVDS) May include frequency dividers (/2, /4, etc.) May include skew adjustmentVoltage-controlled oscillators
  • 50What we coveredAs system complexity and performance demands increase,frequency synthesis devices have had to keep pace with greaterperformance and versatilityDesign and application of phase-locked loops (PLLs)Design and application of direct digital synthesis (DDS)Software tools greatly simplify design and set-up of complexfrequency synthesis devicesClocks for data converters need to have low jitter to keep distortionat a minimumSpecialized clock generation and distribution allows precisefrequency tuning and phase control
  • Visit the DDS, PLL and CLK simulators in thedemonstration roomADIsimCLK, ADIsimPLL andADIsimDDS can quicklyconfigure the complex registersand settings on frequencysynthesis devices to provideoptimum performanceImage of demo/board51VERSION 3.5