High Speed & RF Design and Layout: RFI/EMI Considerations (Design Conference 2013)
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High Speed & RF Design and Layout: RFI/EMI Considerations (Design Conference 2013)

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At very high frequencies, every trace and pin is an RF emitter and receiver. If careful design practices are not followed, the unwanted signals can easily mask those a designer is trying to handle. ...

At very high frequencies, every trace and pin is an RF emitter and receiver. If careful design practices are not followed, the unwanted signals can easily mask those a designer is trying to handle. The design choices begin at the architecture level and extend down to submillimeter placement of traces. There are tried and proven techniques for managing this process. The practical issues of real system design is covered in this session, along with ways to minimize signal degradation in the RF environment.

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High Speed & RF Design and Layout: RFI/EMI Considerations (Design Conference 2013) High Speed & RF Design and Layout: RFI/EMI Considerations (Design Conference 2013) Presentation Transcript

  • High Speed & RF Design and Layout:RFI/EMI ConsiderationsAdvanced Techniques of Higher Performance Signal Processing
  • Legal Disclaimer Notice of proprietary information, Disclaimers and Exclusions Of WarrantiesThe ADI Presentation is the property of ADI. All copyright, trademark, and other intellectual property andproprietary rights in the ADI Presentation and in the software, text, graphics, design elements, audio and allother materials originated or used by ADI herein (the "ADI Information") are reserved to ADI and itslicensors. The ADI Information may not be reproduced, published, adapted, modified, displayed, distributedor sold in any manner, in any form or media, without the prior written permission of ADI.THE ADI INFORMATION AND THE ADI PRESENTATION ARE PROVIDED "AS IS". WHILE ADI INTENDS THEADI INFORMATION AND THE ADI PRESENTATION TO BE ACCURATE, NO WARRANTIES OF ANY KIND AREMADE WITH RESPECT TO THE ADI PRESENTATION AND THE ADI INFORMATION, INCLUDING WITHOUTLIMITATION ANY WARRANTIES OF ACCURACY OR COMPLETENESS. TYPOGRAPHICAL ERRORS ANDOTHER INACCURACIES OR MISTAKES ARE POSSIBLE. ADI DOES NOT WARRANT THAT THE ADIINFORMATION AND THE ADI PRESENTATION WILL MEET YOUR REQUIREMENTS, WILL BE ACCURATE, ORWILL BE UNINTERRUPTED OR ERROR FREE. ADI EXPRESSLY EXCLUDES AND DISCLAIMS ALL EXPRESSAND IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. ADI SHALL NOT BERESPONSIBLE FOR ANY DAMAGE OR LOSS OF ANY KIND ARISING OUT OF OR RELATED TO YOUR USEOF THE ADI INFORMATION AND THE ADI PRESENTATION, INCLUDING WITHOUT LIMITATION DATA LOSSOR CORRUPTION, COMPUTER VIRUSES, ERRORS, OMISSIONS, INTERRUPTIONS, DEFECTS OR OTHERFAILURES, REGARDLESS OF WHETHER SUCH LIABILITY IS BASED IN TORT, CONTRACT OR OTHERWISE.USE OF ANY THIRD-PARTY SOFTWARE REFERENCED WILL BE GOVERNED BY THE APPLICABLELICENSE AGREEMENT, IF ANY, WITH SUCH THIRD PARTY.©2013 Analog Devices, Inc. All rights reserved.2
  • Todays AgendaPCB Layout OverviewSchematicCritical Component Location and Signal RoutingPower Supply BypassingParasitics, Vias and PlacementGround PlaneLayout ReviewSummary3
  • OverviewWhat is high speed? The frequency above which a PCB can significantly degrade circuitperformance. 50MHz and above can be considered high speed.PCB layout is one of the final steps in the design process and oftennot given the attention it deserves. High Speed circuit performanceis heavily dependant on board layout.Today we will address Practical layout guidelines that: Improve the layout process Help ensure expected circuit performance Reduce design time Lower design cost4
  • Schematics
  • SchematicsA good layout starts with good Schematics!Basic Function of Schematics Represent actual circuit connections Generate NetList for layout.Can it be made more effective? Can it represent functionality more clearly? Others can understand circuit Can it show signal path? Aid layout Aid troubleshooting, debug Represent functionalityCan it be made more attractive? Can increase perceived valueMore effective schematics decrease time to market6
  • Schematics7 A perfectly good schematic. What are these? What is this? Too much unnecessary text Text orientation Alignment Lines cross. Is it necessary? Contradicting text No systematic approach Components are scattered No indication of functionality Difficult to read A good layout starts with agood Schematic!
  • Schematics – Example. Is this better?8 Functionality evident at first site. Recognizable signal path. Components grouped by function. Auxiliary functions separated. No clutter No crossed lines No excessive text All additional hidden informationis carried to layout automatically. Occupies less paper space, yetsymbol sizes are larger. Color can add to overallappearance. Separators can aid in recognizingfunctional blocks. Is this Better?
  • Schematics – A circuit with more complexity9
  • Component Placementand Signal Routing
  • Component Placement and Signal RoutingJust as in real estate location is everything!Input/output and power connections on a board aretypically definedComponent placement and Signal routing requiredeliberate thought and planning11
  • Component Placement and Signal RoutingUse of Plane LayersPlane LayerPrepregCopper Signal TraceSolder MaskSignal CurrentReturn Currentfollows the path ofleast inductance12
  • Component Placement and Signal RoutingPlane layer cutoutsPlane LayerPrepregCopper Signal TraceSolder MaskSignal CurrentReturn CurrentNot so good.Minimize Voids inplane layers13
  • Component Placement and Signal RoutingSignal RoutingPlacement not optimized – Minimize crossingsConnectorDigital ADCRFPowerConditioningAnalogTempSensorConnectorADCDriverPlacement optimized – Idealized14
  • Component Placement and Signal RoutingReturn Path RoutingClockCircuitryAnalogCircuitryResistorDigitalCircuitrySensitive AnalogCircuitry Disrupted byDigital Supply NoiseNot so goodIDVoltage DropA better waySensitive AnalogCircuitry Safe fromDigital Supply Noise Use GND and PWR planes toreduce return path R and L. Use separate AGND and DGNDplanes to minimize digitalcoupling into AGND plane. Compartmentalize functions Group components associatedwith functions. Place functions to coincide withsignal path. Route functions first with inputand output along signal path. Route connections betweenfunctions next.Voltage DropMore VoltageDropANALOGCIRCUITSDIGITALCIRCUITSVD VA+ +IDIAIA + IDVINGNDREF15
  • Component Placement and Signal RoutingExample Two Inputs. Carbon copies toensure balance. Gain and feedback. Carboncopies to ensure symmetry. Outputs. Carbon copies toensure symmetry. Level shifting tapped into signalpath. Carbon copies to ensuresymmetry. Auxiliary function. Critical Signal path as short aspossible. Critical signal paths are carboncopies to maintain balance.16
  • Component Placement and Signal RoutingPackaging and Pinout choicesPackaging plays a large role in high-speed applicationsSmaller packages Improved high frequency response Compact layout Lower package parasiticsLow Distortion Pinout (dedicated feedback) Compact layout Streamline signal flow Lower distortion12348765FBINPINNVOUT+-Low Distortion12348765VOUT+-StandardINPINN17
  • PCB18
  • Bottom Silk Carries assembly and/orcomponent ID information. Informative only. Does not affectperformance. Not essential. Information contains text, lines,shapes. Information can become useless ifnot placed carefully. Min. line width = 5 mils (0.127 mm) Text height-to-line width ratioshould be > 12 to retain readability. Avoid placing text over vias, holes,landing pads. Maintain a minimum distancebetween landing pads. Quality varies betweenmanufacturers, ranging from sharpto smudged edges.Bottom Mask Protects copper from environmentaleffects. Minimizes solder bridging. Canprevent bridging if designed withcare. Affects PCB performancesomewhat. Not required. Essential to maintainPCB longevity. Greatly increasesPCB assembly yield. Normally green. Other popularcolors are black, blue red, white.Bottom Copper Can be a signal layer or a planelayer. Normally a 1.4 mils (0.04 mm) thickcopper plate. Can be thicker. Etched to form signal traces andlanding pads. Minimum trace width is 4 mils (0.1mm). Minimum space requirementbetween two objects is 4 mils (0.1mm). Forms a capacitor with othernearby copper plates. Has inductance.PrePreg Separates two copper layers. Is a woven glass epoxy basematerial with glue. Has relative permittivity betweenabout 4.7 and 2.2. Weave density determines highfrequency performance. Comes in a range of thickness. A1080 laminate is 3.2 mils (0.08 mm)thick. Material determines maximumsoldering temperature.Core Two copper foils already attachedto a woven glass material. Same as Prepreg but alreadyglued. Same characteristics as PrePreg. Can provide “built-in” or “inter-planar” capacitance if one or bothcopper foils are used as GND orPWR planes.Another PrePreg and Core Can act as a spacer to ensurespecified finished PCB thickness If made thick, it minimizesinterplanar capacitance.One more PrePreg Can form controlled impedancelines when combined with coppertraces above and GND planebelow. Impedance depends on trace widthabove and thickness andpermittivity of PrePreg. Impedance accuracy depends onthe weave density.Top Copper Usually a signal layer. Normally a 1.4 mils (0.04 mm) thickcopper plate. Can be thicker. Etched to form signal traces andlanding pads. Minimum trace width is 4 mils (0.1mm). Minimum space requirementbetween two objects is 4 mils (0.1mm). Forms a capacitor with othernearby copper plates. Traces have inductance.Top Mask Same as bottom mask Protects copper from environmentaleffects. Minimizes solder bridging. Canprevent bridging if designed withcare. Affects PCB performancesomewhat. Not required. Essential to maintainPCB longevity. Greatly increasesPCB assembly yield. Normally green. Other popularcolors are black, blue red, white.Top Silk Same as bottom silk Carries assembly and/orcomponent ID information. Informative only. Does not affectperformance. Not essential. Information contains text, lines,shapes. Information can become useless ifnot placed carefully. Min. line width = 5 mils (0.127 mm) Text height-to-line width ratioshould be > 12 to retain readability. Avoid placing text over vias, holes,landing pads. Maintain a minimum distancebetween landing pads. Quality varies betweenmanufacturers, ranging from sharpto smudged edges.PCBA typical 62 mils (1.6mm) 6 layer PCB stackup19
  • PCBPCB Material selection examplesIsola – FR4 types Common general purpose material. High temperature versions for leadfree solder exist High permittivity 4.7-4.2. Generates high parasitic capacitances Specified to 1 GHz Controlled impedance trace consistency OK but not great.Rogers – PTFE types Good high frequency, high temperature material Low permittivity. 2.2 and up. Can reduce parasitic capacitances .Expensive Good impedance consistency. Specified to 10 GHzNumerous other manufacturers. Some with performancespecifications similar to above.20
  • PCBComponent Landing pad design Landing pad size Traditionally oversized by ≈ 30% from component pad. Can fit soldering iron on it Can allow visual inspection of solder joint Can accommodate component with larger placement errors. Increases parasitic capacitance – lowers effective useful frequency Increases chances for solder bridging Requires more board space Minimum oversizing: 0-5% from component pad. Retains mechanical strength Contact area between component and PCBremains the same Reduces parasitic capacitance – retainshigher useful frequency Reduces required board space Pad shape Traditionally rectangular with sharp corners Rounded corners allow tighter pad-to-tracespacing. Reduces board size.21This vs. ThisThisOr This
  • Signal Routing
  • Signal RoutingUse GND and PWR Planes Connect pads to planes using “Via-in-pad” method to minimize parasiticsPlace components of a functional block as close as possible 0.5 mm component-to-component spacing is sufficient for manual placementMinimize vias in signal traces. The less the better. Keep traces within a functional block on the same layer.Use interplanar capacitance for bypassingKeep plane layers as contiguous as possible Avoid unnecessary vias perforating plane layers. Avoid cutouts in plane layersKeep traces as straight as possible Minimize bends and turns23
  • Examples A perfectly good high frequency board BUT: Excessive number of unnecessary vias Plane layer compromised with a largecutout Unnecessarily long signal traces Landing pads are too large No internal plane layers Same circuit with added provisions foran auxiliary function A better alternative? More components yet smaller board size Vias are minimized Several internal plane layers “Properly” sized Landing pads24
  • Examples - Performance vs PCB 6 layer PCB No bypass caps No GND plane on top No plane cut outs No “stitching” vias
  • Performance vs. Component Location26
  • AD8099 Harmonic Distortion Vs. FrequencyCSP and SOIC Packages27HARMONICDISTORTION(dBc)0.1–120–100–110–80–90–60–70–501 10 5004511-0-085SOLID LINES – SECOND HARMONICSDOTTED LINES – THIRD HARMONICSG = +5VOUT = 2V p-pVS = ±5VRL = 100ΩFREQUENCY (MHz)SOICCSPImprovement10dB at 1MHz 14dBat 10MHz00:09:52
  • High Speed PCB Boards Small signal BW: New: 1.41 GHz Existing: 976 MHz This is nearly a 50%improvement28
  • Large signal (10 dm) BW:5V suply:New: 1.07 GHzExisting: 948 MHz10V supply:New: 1.25 GHzExisting: 891 MHz29
  • Pin4 - VNPin8 - VPVOUT2R51VOUT1R13IN1+R723IN1-R1R3RS1R11R15R9756R14IN2+R8IN2-R6R2R16RS2R12R4R10C3 C2C1VPVNGNDC4 C530
  • Crosstalk and CouplingCapacitive Crosstalk or Coupling This results from traces running on top of each other, which forms a parasiticcapacitor Solutions run traces orthogonal, to minimize trace coupling and lower areaprofileInductive Crosstalk Inductive crosstalk exists due to the magnetic field interaction between longtraces parallel traces There are two types of inductive crosstalk; forward and backward Backward is the noise observed nearest the driver on the victim trace Forward is the noise observed farthest from the driver on the driven lineMinimize crosstalk by Increasing trace separation (improving isolation) Using guard traces Using differential signals31
  • Power Supply Bypassing
  • Power Supply BypassingBypassing is essential to high speed circuit performance33
  • Power Supply BypassingBypassing is essential to high speed circuit performanceCapacitors right at power supply pins34
  • Power Supply BypassingBypassing is essential to high speed circuit performanceCapacitors right at power supply pins Capacitors provide low impedance AC return Provide local charge storage for fast rising/falling edges35
  • Power Supply BypassingBypassing is essential to high speed circuit performanceCapacitors right at power supply pins Capacitors provide low impedance AC return Provide local charge storage for fastrising/falling edgesKeep trace lengths shortEQUIVALENT DECOUPLED POWERLINE CIRCUIT RESONATES AT:f =12π LC√IC+VSC1L10.1µF1nHf = 16MHz36
  • Power Supply BypassingBypassing is essential to high speed circuit performanceCapacitors right at power supply pins Capacitors provide low impedance AC return Provide local charge storage for fast rising/falling edgesKeep trace lengths short37
  • Power Supply BypassingBypassing is essential to high speed circuit performanceCapacitors right at power supply pins Capacitors provide low impedance AC return Provide local charge storage for fast rising/falling edgesKeep trace lengths shortClose to load return Helps minimize transientcurrents in the ground plane38
  • Optimized Load and Bypass CapacitorPlacement and Ground ReturnTantalumTantalumCCRLAD80XXRTRGRF0039
  • Power Supply BypassingBoard Capacitance404 layer stack up Component/signal sideGround planePower planeCircuit sidedK = relative dielectric constantA = area in cm2d = spacing between plates in cmAkA11.3dC=
  • Power Supply BypassingPower Plane Capacitance*Courtesy of Lee Ritchey*41
  • Power Supply Bypassing Capacitor ModelESR (Equivalent Series Resistance) RsCapacitance XC = 1/2πfCESL (Equivalent SeriesInductance) XL=2πfLEffective ImpedanceAt Series resonance XL=XC Z = R2)(2 XCXLRsZ −+=*Courtesy of Lee Ritchey*42
  • Capacitor Choices0603 0612*Courtesy of Lee Ritchey*43
  • Multiple Parallel Capacitors1 x 330µF T520, 1 x 1.0µF 0603, 2 x 0.1µF 0603, and 6 x 0.01µF 0603*Courtesy of Lee Ritchey*2 x (1 x 330µF T520, 1 x 1.0µF 0603, 2 x 0.1µF 0603, and 6 x 0.01µF 0603)1µF330µF0.1µF0.01µF45
  • Parasitics46
  • Parasitics47PCB parasitcs take theform of hiddencapacitors, inductorsand resistors in the PCBParasitics degrade anddistort performance
  • Trace/Pad Capacitance and Inductance48113kXYC pFZ=K = relative dielectric constantX = Copper Length (mm)Y = Copper Width (mm)Z = Distance to nearest Plane (mm)Example1: SOIC landing padX = 0.51 mm Y = 1.27mmZ = 0.16mm: C = 0.17 pF; L=0.08 nHZ = 0.13mm: C = 0.21 pF; L=0.08 nH20 2 0 5 2235X Y ZL X nHY Z X. . ln . +   = + +    +    Example2: 3x3mm LFCSP landing padX = 0.3 mm Y = 0.6 mmZ = 0.16mm: C = 0.05 pF; L=0.05 nHZ = 0.13mm: C = 0.05 pF; L=0.05 nHFR4 PCB with 1 oz Cu on top, 50Ωcontrolled impedance for 10 mils and 0.2mmwide tracesK= 4.7, Z=0.16mm and 0.13mmMinimize Capacitance1) Increase board thickness2) Reduce trace/pad area3) Remove ground planeMinimize Inductance1) Use Ground plane2) Keep length short (halving the lengthreduces inductance by 44%)3) Doubling width only reducesinductance by 11%
  • Trace/Pad Capacitance and Inductance49113kXYC pFZ=K = relative dielectric constantX = Copper Length (mm)Y = Copper Width (mm)Z = Distance to nearest Plane (mm)20 2 0 5 2235X Y ZL X nHY Z X. . ln . +   = + +    +    Z An internal or Bottom Plane Layer Forms an Interplanar capacitance with aPower Plane layer (not shown) under it. Spacer Large distance to eliminate interaction withControlled Impedance Layer above it. Controlled Impedance Plane Layer Traces on the top signal layer, the spacerbetween and this plane forms transmissionlines with a characteristic impedance. Top (Signal) layer Has signal traces and component landingpads. Traces are transmission lines withcharacteristic impedance Top Solder mask Has effect on characteristic impedance
  • Via Parasitics50+= 14ln2dhhLL = inductance of the via, nHH = length of via, cmD = diameter of via, cmH= 0.157 cm thick board,D= 0.041 cm Via Inductance Via Capacitance+= 1041.0)157.0(4ln)157.0(2LL = 1.2nh12155.0DDTDC r−=εD2 = diameter of clearance hole in theground plane, cmD1 = diameter of pad surrounding via, cmT = thickness of printed circuit board, cm= relative electric permeability of circuitboard materialC = parasitic via capacitance, pFT = 0.157cm,D1=0.071cmD2 = 0.127C = 0.51pfrεnH
  • Via Placement*0603and 040251*Courtesy of Lee Ritchey
  • Capacitor Parasitic ModelC = CapacitorRP = insulation resistanceRS = equivalent series resistance (ESR) inductance of the leadsand platesRDA = dielectric absorptionCDA = dielectric absorption52LrRPCRDA CDARS
  • Resistor Parasitic ModelR = ResistorCP = Parallel capacitanceL= equivalent series inductance (ESL)53CPRL
  • Low Frequency Op Amp Schematic54
  • High Speed Op Amp Schematic55
  • High Frequency Op Amp Schematic56Stray Capacitance
  • Stray Capacitance Simulation Schematic57
  • Frequency Response with 1.5pF StrayCapacitance1.5dB peaking58
  • Stray InductanceStray Inductance59
  • Parasitic Inductance Simulation Schematic24.5mm x .25mm” =29nH60
  • Pulse Response With and Without GroundPlane0.6dB overshoot61
  • Ground and Power Planes
  • Ground and Power Planes ProvideA common reference pointShieldingLowers noiseReduces parasiticsHeat sinkPower distributionHigh value capacitance63
  • Ground Plane Recommendations There is no single grounding method which is guaranteed to work 100% ofthe time! At least one layer on each PC board MUST be dedicated to ground plane! Provide as much ground plane as possible especially under traces thatoperate at high frequency Use thickest metal as feasible (reduces resistance and provides improvedthermal transfer) Use multiple vias to connect same ground planes together Do initial layout with dedicated plane for analog and digital ground planes,split only if required Follow recommendations on mixed signal device data sheet. Keep bypass capacitors and load returns close to reduce distortion Provide jumper options for joining analog and digital ground planestogether64
  • Tweet it out! @ADI_News #ADIDC13What we covered High speed PCB design requires deliberate thought and attention to detail! Load the schematic with as much information as possible Where you put components on the board is just as important as to whereyou put entire circuits Take the lead when laying out your board, don’t leave anything to chance Use multiple capacitors for power supply bypassing Parasitics must be considered and dealt with Ground and Power planes play a key role in reducing noise and parasitics New packaging and pinouts allow for improved performance and morecompact layouts There are many options for signal distribution, make sure you choose theright one for your application Check the layout very carefully65
  • Tweet it out! @ADI_News #ADIDC13Electromagnetic compatibility (EMC)There are two aspects of EMC: It describes the ability of electronic systems to operate without interfering withother systems It also describes the ability of such systems to operate as intended within aspecified electromagnetic environmentPrimary specifications are IEC-60050 and IEC1000Extensive reviews in tutorial MT-095 and Analog Dialog 30-4 onAnalog Devices website (www.analog.com)Inability to meet these requirements will compromise yourequipmentInability to meet these requirements will severely limit the ability tosell the equipment to customers66