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Data Converters for Solving Hard Problems
 

Data Converters for Solving Hard Problems

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Data conversion for data acquisition is a two-part process that involves sampling and then converting signals into digital venues. These processes inherently remove part of the complete analog signal ...

Data conversion for data acquisition is a two-part process that involves sampling and then converting signals into digital venues. These processes inherently remove part of the complete analog signal in exchange for the power and robustness of digital signal handling. This becomes especially difficult when trying to capture signals at the limits of the resolution and speed of our systems. In this session, learn how to design a data conversion system that minimizes the signal loss to match the signal handling requirements … even on the hard ones.

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    Data Converters for Solving Hard Problems Data Converters for Solving Hard Problems Presentation Transcript

    • Data Converters for Solving HardProblemsAdvanced Techniques of Higher Performance Signal Processing
    • Legal Disclaimer Notice of proprietary information, Disclaimers and Exclusions Of WarrantiesThe ADI Presentation is the property of ADI. All copyright, trademark, and other intellectual property andproprietary rights in the ADI Presentation and in the software, text, graphics, design elements, audio and all othermaterials originated or used by ADI herein (the "ADI Information") are reserved to ADI and its licensors. The ADIInformation may not be reproduced, published, adapted, modified, displayed, distributed or sold in any manner, inany form or media, without the prior written permission of ADI.THE ADI INFORMATION AND THE ADI PRESENTATION ARE PROVIDED "AS IS". WHILE ADI INTENDS THE ADIINFORMATION AND THE ADI PRESENTATION TO BE ACCURATE, NO WARRANTIES OF ANY KIND ARE MADEWITH RESPECT TO THE ADI PRESENTATION AND THE ADI INFORMATION, INCLUDING WITHOUT LIMITATIONANY WARRANTIES OF ACCURACY OR COMPLETENESS. TYPOGRAPHICAL ERRORS AND OTHERINACCURACIES OR MISTAKES ARE POSSIBLE. ADI DOES NOT WARRANT THAT THE ADI INFORMATION ANDTHE ADI PRESENTATION WILL MEET YOUR REQUIREMENTS, WILL BE ACCURATE, OR WILL BEUNINTERRUPTED OR ERROR FREE. ADI EXPRESSLY EXCLUDES AND DISCLAIMS ALL EXPRESS AND IMPLIEDWARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT OFANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. ADI SHALL NOT BE RESPONSIBLE FOR ANY DAMAGEOR LOSS OF ANY KIND ARISING OUT OF OR RELATED TO YOUR USE OF THE ADI INFORMATION AND THE ADIPRESENTATION, INCLUDING WITHOUT LIMITATION DATA LOSS OR CORRUPTION, COMPUTER VIRUSES,ERRORS, OMISSIONS, INTERRUPTIONS, DEFECTS OR OTHER FAILURES, REGARDLESS OF WHETHER SUCHLIABILITY IS BASED IN TORT, CONTRACT OR OTHERWISE. USE OF ANY THIRD-PARTY SOFTWAREREFERENCED WILL BE GOVERNED BY THE APPLICABLE LICENSE AGREEMENT, IF ANY, WITH SUCH THIRDPARTY.©2013 Analog Devices, Inc. All rights reserved.2
    • Today’s AgendaData converters in the signal chainBasics of data conversionDynamic signal processingDriving ADCsInput structuresDACs for high speed and high resolution3
    • Analog to Electronic Signal Processing4SENSOR(INPUT)DIGITALPROCESSORAMP CONVERTERACTUATOR(OUTPUT)AMP CONVERTER
    • Analog to Electronic Signal Processing5SENSOR(INPUT)DIGITALPROCESSORAMP ADCACTUATOR(OUTPUT)AMP DAC
    • Analog and Digital DomainsWhy Convert to Digital?6Analog signals are continuous and provide the entire signalDigital signals capture only a portion of the signalWhy digitize? Improved signal analysis potential More robust storage More accurate transmission Why not digitize? Cost Complexity Processing time available. Development objective of sampled data systems is to minimizeeffect of the sampling process
    • Basic ADC with External Reference7VDDVSSGROUND(MAY BE INTERNALLYCONNECTED TO VSS)ANALOGINPUTVREFDIGITALOUTPUTSAMPLINGCLOCKCONTROL SIGNALS(EOC, DATA READY, ETC.)ADCVDIO
    • Sampled Data System: Sampling andQuantization8LPFORBPFN-BITADCDSPN-BITDACLPFORBPFfafs fstAMPLITUDEQUANTIZATION DISCRETETIME SAMPLINGfa1fsts=
    • Unipolar Binary Code, 4-Bit Converter9+15+14+13+12+11+10+9+8+7+6+5+4+3+2+10BASE 10NUMBERSCALE +10 V FS BINARY11111110110111001011101010011000011101100101010000110010000100009.3758.7508.1257.5006.8756.2505.6255.0004.3753.7503.1252.5001.8751.2500.6250.000+FS – 1 LSB = 15/16 FS+7/8 FS+13/16 FS+3/4 FS+11/16 FS+5/16 FS+9/16 FS+1/2 FS+7/16 FS+3/8 FS+5/16 FS+1/4 FS+3/16 FS+1/8 FS1 LSB = +1/16 FS0+15+14+13+12+11+10+9+8+7+6+5+4+3+2+10BASE 10NUMBERSCALE +10 V FS BINARY11111110110111001011101010011000011101100101010000110010000100009.3758.7508.1257.5006.8756.2505.6255.0004.3753.7503.1252.5001.8751.2500.6250.000+FS – 1 LSB = 15/16 FS+7/8 FS+13/16 FS+3/4 FS+11/16 FS+5/16 FS+9/16 FS+1/2 FS+7/16 FS+3/8 FS+5/16 FS+1/4 FS+3/16 FS+1/8 FS1 LSB = +1/16 FS0
    • Bipolar Codes, 4-bit Converter10+4.375+3.750+3.125+2.500+1.875+1.250+0.6250.000–0.625–1.250–1.875–2.500–3.125–3.750–4.375–5.0001 1 1 11 1 1 01 1 0 11 1 0 01 0 1 11 0 1 01 0 0 11 0 0 00 1 1 10 1 1 00 1 0 10 1 0 00 0 1 10 0 1 00 0 0 10 0 0 00 1 1 10 1 1 00 1 0 10 1 0 00 0 1 10 0 1 00 0 0 1*0 0 0 01 1 1 01 1 0 11 1 0 01 0 1 11 0 1 01 0 0 11 0 0 0+FS – 1LSB = +7/8 FS+3/4 FS+5/8 FS+1/2 FS+3/8 FS+1/4 FS+1/8 FS0– 1/8 FS– 1/4 FS– 3/8 FS–1/2 FS–5/8 FS–3/4 FS– FS + 1LSB = –7/8 FS– FS±5V FSSCALE0 1 1 10 1 1 00 1 0 10 1 0 00 0 1 10 0 1 00 0 0 10 0 0 01 1 1 11 1 1 01 1 0 11 1 0 01 0 1 11 0 1 01 0 0 11 0 0 00 1 1 10 1 1 00 1 0 10 1 0 00 0 1 10 0 1 00 0 0 1*1 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1OFFSETBINARYTWOSCOMP.ONESCOMP.SIGNMAG.0+ 0 0 0 00– 1 1 1 10 0 0 01 0 0 0ONESCOMP.SIGNMAG.CODES NOT NORMALLY USEDIN COMPUTATIONS (SEE TEXT)+7+6+5+4+3+2+10–1–2–3–4–5–6–7–8BASE 10NUMBER*
    • The Size of a Least Significant Bit (LSB)11VOLTAGE(10V FS)2.5 V625 mV156 mV39.1 mV9.77 mV (10 mV)2.44 mV610 mV153 mV38 mV9.54 mV (10 mV)2.38 mV596 nV*ppm FS250,00062,50015,6253,9069772446115410.240.06% FS256.251.560.390.0980.0240.00610.00150.00040.00010.0000240.000006dB FS-12-24-36-48-60-72-84-96-108-120-132-144RESOLUTIONN2-bit4-bit6-bit8-bit10-bit12-bit14-bit16-bit18-bit20-bit22-bit24-bit2N416642561,0244,09616,38465,536262,1441,048,5764,194,30416,777,216*600nV is the Johnson Noise in a 10kHz BW of a 2.2kW Resistor @ 25°C
    • Practical Resolution Needs for Data ConvertersInstrumentation measurements Sensor resolution/accuracy of 0.5% = 1/200 8 bits equivalent to 1/256 -- digitizing will lose information 10x sensor resolution = 1/2000 -- 12 bits is 1/4096 Allows discrimination of small changes Can also be driven by display requirementsDynamic signal measurements Audio systems need better than 0.1% distortion at 5% of full scale Equivalent to 1/20,000 -- 16 bits is 1/65,53612
    • Transfer Functions for Ideal 3-Bit DAC and ADC13DIGITAL INPUTANALOGOUTPUTFS000 001 010 011 100 101 110 111 ANALOG INPUTDIGITALOUTPUTFS000001010011100101110111QUANTIZATIONUNCERTAINTYQUANTIZATIONUNCERTAINTYDAC ADC
    • Primary Errors in Data Converters(DC Parametrics)Instrumentation and measurement Described in LSBs (least-significant-bit), % of FS, ppm of FS Offset error – the input level needed to change the first code Gain/full-scale error – the input level need to change the last code Nonlinearity – deviation of codes from the line from zero to FS Differential nonlinearity – code-to-code deviation from 1 LSB Transition noise – ADC uncertainty in code center point14
    • Primary Errors in Data Converters(AC Parametrics)15 Dynamic systems SINAD (Signal-to-Noise-and-Distortion Ratio):The ratio of the rms signal amplitude to the mean value of the root-sum-squares (RSS) of all other spectral components, includingharmonics, but excluding DC. ENOB (Effective Number of Bits): SNR (Signal-to-Noise Ratio), or Signal-to-Noise Ratio withoutHarmonics:The ratio of the rms signal amplitude to the mean value of the root-sum-squares (RSS) of all other spectral components, excluding the first5 harmonics and DC SFDR (Spurious-Free-Dynamic-Range) Signal dynamic range in thebandwidth of interest containing no frequency noise spursENOB =SINAD – 1.76dB6.02dB
    • Quantifying Data ConverterDynamic Performance16 Harmonic Distortion Worst Harmonic Total Harmonic Distortion (THD) Total Harmonic Distortion Plus Noise (THD + N) Signal-to-Noise-and-Distortion Ratio (SINAD, or S/N +D) Effective Number of Bits (ENOB) Signal-to-Noise Ratio (SNR) Analog Bandwidth (Full-Power, Small-Signal) Spurious Free Dynamic Range (SFDR) Two-Tone Intermodulation Distortion Multi-tone Intermodulation Distortion Noise Power Ratio (NPR) Adjacent Channel Leakage Ratio (ACLR) Noise Figure Settling Time, Overvoltage Recovery Time
    • The Comparator: A 1-Bit ADC17DIFFERENTIALANALOG INPUTLOGICOUTPUTLATCHENABLEDIFFERENTIAL ANALOG INPUTCOMPARATOROUTPUT"0""1"0VHYSTERESIS+–
    • Quantization and Quantization Noise180010100111001011101111/8 2/8 3/8 4/8 5/8 6/8 7/8 FSNORMALIZED ANALOG INPUTDIGITALOUTPUTQuantization noise error: RMS value is LSB/3.464Quantizationerror function
    • Combined Effects of Code Transition Noiseand DNL19ADC INPUT ADC INPUT ADC INPUTCODE TRANSITION NOISE DNL TRANSITION NOISEAND DNLADCOUTPUTCODE
    • Ideal ADC Sampling3 Different Frequencies, Sampled the Same20
    • Ideal ADC SamplingOnce Sampled, Information Is Lost21
    • Nyquists Criteria A signal with a maximum bandwidth of fa must be sampled at a rate fs > 2faor information about the signal will be lost because of aliasing. Aliasing occurs whenever fs < 2fa A signal which has frequency components between fa and fb must besampled at a rate fs > 2 (fb – fa) in order to prevent alias components fromoverlapping the signal frequencies. The concept of aliasing is widely used in communications applicationssuch as direct IF-to-digital conversion.22
    • Analog Signal fa Sampled @ fs Has Images(Aliases) At |±Kfs ±fa|, K = 1, 2 ...230.5fs0.5fsfsfs1.5fs1.5fs2fs2fsZONE 1 ZONE 2 ZONE 3 ZONE 4fa I I II IIIIfa
    • Oversampling Relaxes Requirementson Baseband Antialiasing Filter24BADRfsfa fs– faKfs – fafafs2KfsKfs2STOPBAND ATTENUATION = DRTRANSITION BAND: fa to fs – faCORNER FREQUENCY: faSTOPBAND ATTENUATION = DRTRANSITION BAND: fa to Kfs – faCORNER FREQUENCY: fa
    • Advantages of Differential Analog InputInterfaces for Data ConvertersDifferential inputs give twice the signal swing vs. single-ended(especially important for low voltage single-supply operation)Differential inputs help suppress even order distortion productsMany IF/RF components such as SAW filters and mixers aredifferentialDifferential inputs suppress common-mode ADC switching noiseincluding LO feed-through from mixer and filter stagesDifferential ADC designs allow better internal component matchingand tracking than single-ended. Less need for trimmingHelps minimize the effects of noise on the ground.If you drive them single-ended, you will have degradation indistortion and noise performanceHowever, many signal sources are single-ended, so the differentialamplifier is useful as a single-ended to differential converter2.25
    • ADA4941 Driving AD7690 18-Bit PulSAR® ADCin +5V Application2.26 After filter, noise = 13 µV rms due to amp Signal = 8V p-p differential SNR = 107 dB+5V+2.1V+1.75V9.53kW10.0kW8.45kW0.1µF0.1µF11.3kW4.02kW806WADR444+5VVREF = +4.096V0.1µFREF+5VVDDIN+IN–++––CFVIN = 10V+2.1V +/– 2V+2.1V – /+ 2VADA4941-141.2W41.2W3.9nF3.9nFAD7690, 400kSPSAD7691, 250kSPS18-BITPulSARADCsLPF CUTOFF = 1MHzVCM = +2.1VRR0.1µFVREF = +4.096VINPUT RANGE =8.192V p-p DIFF.10.2nV/HzSNR = 100dBFOR AD7690
    • ADA4937-1 Driving AD6645in +5V DC-Coupled Application2.27AD6645 SPECS:INPUT BW = 270MHz1 LSB = 134µVSNR = 75dB5nV/Hz 1.57270106 = 103µV rmsOUTPUT NOISE =OUTPUT SNR = 20 log10310–60.778= 77.6dB+–AD664514-BIT ADCAIN–AIN+VIN±1.1V65.5W200W200W200W226W24.9W24.9W+2.4VVOCMADA4937-10.1µF0.1µF0.1µF+1.2V + / – 0.275V+2.4V – / + 0.55V+2.4V + / – 0.55V2.2V p-pDIFFERENTIALINPUT SPAN+5VFROM 50WSOURCEfs =80/105MSPSVREF5nV/Hz+5VC
    • Buffered and Unbuffered DifferentialADC Inputs Structures2.28BUFFERED INPUTSUNBUFFEREDINPUTS5VINB+-AVINACPCPS1S2S3S4S6CH5pFCH5pFS7ZIN(A) (B)(C)GNDAVDDVINBR1 R1R2 R2INPUTBUFFERSHAVINAINPUTBUFFERSHAVREFVINAVINB
    • Input Impedance Model for Buffered andUnbuffered Input ADCs2.29R CADCZINBUFFERED INPUT R and C are constant over frequency Typically:R: 1 kW – 2 kWC: 1.5 pF – 3 pFUNBUFFERED INPUT R and C vary with both frequency and mode(track/hold) Use Track mode R and C at the input frequencyof interest
    • 2.30Unbuffered CMOS ADC (AD9236 12-Bit, 80 MSPS)Series Input Impedance in Track Mode and Hold ModeREAL Z, HOLDREAL Z, TRACKIMAG Z, TRACKIMAG Z, HOLDANALOG INPUT FREQUENCY (MHz)SERIESREALIMPEDANCE(OHMS)SERIESIMAGINARYIMPEDANCE(pF)200180160140120100806040200201816141210864200 100 200 300 400 500 600 700 800 900 1000RSZINCS
    • Basic Principles of Resonant Matching2.31(2 f )2 CSRSZINCSRPZINCPLS/2LS/2LPLS =1(2 f )2 CPLP =1SERIES RESONANT @ f (70MHz) PARALLEL RESONANT @ f (70MHz)ZIN = RS + j0 @ f ZIN = RP + j0 @ fADC ADCMake XLS = XCS Make XLP = XCPf|ZIN|RP|ZIN|RSf4kW @ 70MHzFor AD923669W @ 70MHzFor AD9236(69W)(4.3pF)(4kW) (4.3pF)(1.2µH) (1.2µH)
    • Before and After AddingMatching Analog Antialiasing Filter Network2.32 SFDR Improved by 13.4 dB, SNR improved by 10.7 dB Note: Measured at maximum gain of 35 dB (gain code 255, high gain mode) using76.8 MHz sampling clockSAMPLING RATE = 76.8MSPSINPUT = 70MHzNOISE FLOOR = –84.3dBFSTHD = –63.9dBcSFDR = 68.0dBcSNR = 42.1dBFSSAMPLING RATE = 76.8MSPSINPUT = 70MHzNOISE FLOOR = –84.3dBFSTHD = –63.9dBcSFDR = 68.0dBcSNR = 42.1dBFSWITHOUT NETWORKSAMPLING RATE = 76.8MSPSINPUT = 70MHzNOISE FLOOR = –95dBFSTHD = –76.8dBcSFDR = 81.4dBcSNR = 52.8dBFSWITH NETWORK
    • Effective Aperture Delay TimeMeasured with Respect to ADC Input33SAMPLINGCLOCKANALOG INPUTSINEWAVEZERO CROSSING+FS–FS0V+te–tete
    • Effects of Aperture Jitterand Sampling Clock Jitter34ANALOGINPUTTRACKHOLDDdvdtv dvdttRMS= APERTURE JITTERvRMSNOMINALHELDOUTPUT= t= SLOPE = APERTURE JITTER ERRORDDD
    • Theoretical SNR and ENOB Due to Jittervs. Full-Scale Sinewave Analog Input Frequency35SNR(dB)ENOB10080604020161412108641 3 10 30 100tj = 1nstj = 100pstj = 10pstj = 1pstj = 0.1ps12018FULL-SCALE SINEWAVE ANALOG INPUT FREQUENCY (MHz)SNR = 20log1012ftjtj = 50fs
    • Oscillator Requirementsvs. Resolution and Analog Input Frequencytj(ps)
    • Clock and Timing IC Jitter37SignaltoNoiseRatio(SNR)indBFrequency of Fullscale Analog Input to ADC in MHz45.050.055.060.065.070.075.080.085.090.0100 100050 fs100 fs200 fs400 fs800 fsAIN = 200 MHz300MHz400MHz500MHz
    • 4.38SNR Plot for the AD9445 Evaluation Boardwith Proper Decoupling
    • 4.39AD9445 Pinout Diagram
    • 4.40SNR Plot for an AD9445 Evaluation Board withCaps Removed from the Analog Supply
    • 4.41SNR Plot for an AD9445 Evaluation Board withCaps Removed from the Digital Supply
    • ADIsimADC42
    • ADIsimADC43
    • VisualAnalog™44
    • SPI Controller45
    • High Accuracy SourcesResolution to 1 ppm One microvolt out of 1 voltEverything matters External amplifiers – low offset, drift, noise Voltage reference – 1 ppm drift Layout and designApplications MRI – magnetic resonance imaging Precise gradient in magnetic field Test equipment46
    • High Accuracy 18-Bit ±10 V Source47
    • ADC ReferencesInput level compared to reference ADC accuracy is relative to that referenceInternal reference Simplicity and lower cost Reference tuned to ADC performance Specifications all-inclusiveExternal reference Can be chosen for higher absolute accuracy Allows common reference in multiple-ADC system Common reference for sensor driver and ADCPower supply as reference Lowest cost in most cases Noise is biggest issue Tolerance and drift may degrade accuracy48
    • Voltage Reference Comparison49
    • ADC References50
    • Analog to Electronic Signal Processing51SENSOR(INPUT)DIGITALPROCESSORAMP ADCACTUATOR(OUTPUT)AMP DAC
    • DAC Signal Construction52tSAMPLEDSIGNALtRECONSTRUCTEDSIGNAL1fcIDEAL TRANSITION TRANSITION WITHDOUBLET GLITCHTRANSITION WITHUNIPOLAR (SKEW) GLITCHt t t
    • DAC sin x/x Roll Off(Amplitude Normalized)530.5fc fc 1.5fc 2fc 2.5fc 3fcA =sin ffc ffc1fAt–3.92dBRECONSTRUCTEDSIGNAL01fcIMAGESIMAGESIMAGESFS – FOUT FS + FOUT 2FS – FOUT 2FS + FOUT
    • LPF Required to Reject Image Frequency54
    • Analog Filter Requirements for fo = 10 MHZ:fc = 30 MSPS, and fc = 60 MSPS55fCLOCK = 30MSPSdBIMAGE10 20 30 40 50 60 70 80foANALOG LPF10 20 30 40 50 60 70 80IMAGEANALOGLPFFREQUENCY (MHz)IMAGEIMAGEIMAGEIMAGEfofCLOCK = 60MSPSdBAB
    • DAC Images (continued)56As the DAC output (FOUT) approaches Nyquist frequency, the images come closertogether, making it extremely difficult to filter the image from the signal.0 50 100 150 200 2500101102X X XFREQUENCYPOWERIn the above example, FOUT = 0.45 3 Fs
    • Interpolation Maximum Output Frequency of Standard DAC is FCLOCK  2 (Nyquist Rate). In an Interpolating D/A Converter, Digital Interpolation Filters and a PLL Clock Multiplier AreUsed to Multiply the Input Data Rate to the DAC by a Factor of x Times the Clock Rate. Produces an Image at x Times FSIGNAL, Smoothing the Sine Function and Simplifying theFilter Requirements and Digital Interface.57fSIGNAL fCLOCK = 2 x fSIGNAL fSIGNAL fCLOCK = 8 x fSIGNAL
    • AD9775 TxDAC® 14-Bit CMOS DAC Core58CLOCK14-BITLATCH51-BITLATCH31CURRENTSWITCHES15CURRENT5 BINARYCURRENTSWITCHESBITS 1-5DECODE5-TO-31BITS 6-9DECODE4-TO-155 51515431 31514CURRENTOUTPUTFS =2mA-20mASWITCHESI = 512 LSBI = 32 LSBI = 1 LSB5NOTE: Differential Outputs Not Shown
    • Oversampling Interpolating TxDAC®Simplified Block Diagram59foK•fcfcLATCH LATCH DACLPFDIGITALINTERPOLATIONFILTERPLLN N N NTYPICAL APPLICATION: fc = 160MSPSfo = 50MHzK = 2Image Frequency = 320– 50 = 270MHz
    • AD9772: 2X Interpolation vs.Nyquist DAC60Nyquist DAC AD9772 DAC1st IMAGE1st NEW IMAGEIMAGES FILTERED BYDIGITAL 2XINTERPOLATION
    • Tweet it out! @ADI_News #ADIDC13What We CoveredData converters in the signal chainBasics of data conversionDynamic signal processingDriving ADCsInput structuresDACs for high speed and high resolution61
    • Tweet it out! @ADI_News #ADIDC13Design Resources Covered in This SessionDesign tools & resources:Ask technical questions and exchange ideas online in ourEngineerZone® Support Community Choose a technology area from the homepage: ez.analog.com Access the Design Conference community here: www.analog.com/DC13community62Name Description URLADIsimADC Shows dynamic performance of ADCs in realapplicationsVoltage ReferenceSelection WizardVisual AnalogSPI Controller
    • Tweet it out! @ADI_News #ADIDC13Visit the 16-Bit 250 kSPS 8-Channel, Isolated DataAcquisition System in the Exhibition Room Circuits from the Lab® CN0254 isa cost effective, highly integrated16-bit, 250 kSPS, 8-channel dataacquisition system that candigitize ±10 V industrial levelsignals. The circuit also provides2500 V rms isolation between themeasurement circuit and the hostcontroller, and the entire circuit ispowered from a single isolatedPWM controlled 5 V supply.63This demo board is available for purchase:www.analog.com/DC13-hardware
    • Tweet it out! @ADI_News #ADIDC1316-Bit 250 kSPS 8-Channel Isolated DataAcquisition System—CN025464
    • The Data Conversion Handbook65The Data Conversion Handbook, edited by Walt Kester (Newnes,2005), is written for design engineers who routinely use dataconverters and related circuitry. Comprising Data ConverterHistory, Fundamentals of Sampled Data Systems, DataConverter Architectures, Data Converter Process Technology,Testing Data Converters, Interfacing to Data Converters, DataConverter Support Circuits, Data Converter Applications, andHardware Design Techniques, it may be the ultimate expressionof product "augmentation" as it relates to data converters. Thelast chapter discusses practical issues, including common pitfallsand solutions related to the non-ideal properties of passivecomponents.The Data Conversion Handbook can be purchased from yourfavorite bookseller.Individual chapters--or a zip file containing all chapters--of the original Basic LinearDesign seminar notes can be downloaded by selecting the appropriate links belowhttp://www.analog.com/library/analogDialogue/archives/39-06/data_conversion_handbook.html
    • Linear Circuit Design Handbook66Linear Circuit Design Handbook, edited by Hank Zumbahlen(Newnes, 2008), bridges the gap between circuit componenttheory and practical circuit design. Effective analog circuit designrequires a strong understanding of core linear devices and howthey affect analog circuit design. This book provides completecoverage of important analog devices and how to use them indesigning linear circuits, and serves as a useful learning tool andreference for design engineers involved in analog and mixed-signal design. It features complete coverage of analog circuitcomponents for the practicing engineer; market-validated designinformation for all major types of linear circuits; practical adviceon how to read op amp data sheets and how to choose off-the-shelf op amps; printed circuit board design issues; and over 1000figures, including working circuit diagrams. Analog Dialoguereaders can get a 20% discount when they order this bookdirectly from Newnes. Enter discount code 92222.Individual chapters--or a zip file containing all chapters--of the original Basic LinearDesign seminar notes can be downloaded by selecting the appropriate links belowhttp://www.analog.com/library/analogDialogue/archives/43-09/linear_circuit_design_handbook.html