Clock Fundamentals

The World Leader in High-Performance Signal Processing SolutionsClock Fundamentals Paul Kern Staff Applications Engineer January 2012

What is a clock and what arethe common frequencies? Unlike a data waveform, a clock signal is a square wave whose frequency is usually constant. Common frequencies include:  1 pps (pulse per second) used by GPS  8 kHz (commonly used in wired communcations) and is commonly referred to as a BITS clock  19.44 MHz is a common reference clock in synchronous optical (SONET) networks.  122.88 MHz is commonly used in wireless communications  125 and 156.25 MHz are common Ethernet reference clocks.2

An Introduction toPhase-locked Loops (PLLs) What is a phase-locked loop? It is a control loop with an voltage-controlled oscillator (VCO) whose frequency is constantly adjusted so that the output frequency tracks the input frequency. The earliest examples of PLLs date back to the 1920s. R Phase / REF Divider Frequency Charge Loop P (Post) VCO OUT Detector Pump Filter Divider (PFD) N (Feedback) Divider3

Three types of clocking chips Analog PLLs  Simple architecture  Very high performance and low noise Digital PLLs  Excellent jitter cleaning  Extremely flexible  Capable of very low loop bandwidths Direct Digital Synthesis  Extremely flexible frequency generation  Very fast frequency sweeping and hopping  Very popular in military and instrumentation applications4

Analog PLL Block Diagram Simplified PLL Block Diagram REF R INPUT Phase / (Fin) Divider Frequency Charge Loop P (Post) OUTPUT VCO FREQUENCY Detector Pump Filter Divider (Fout) (PFD) N (Feedback) Divider In this diagram, Fout = Fin / R * N / P For Example: 19.44 MHz to 156.25 MHz:  R divider=81, N=3125, P divider = 125 August 2006 ADI Confidential Information

AD9553 Detailed Block Diagram LOCKED FILTER TEST SEL REFB REFERENCE SWITCHOVER CLOCK MUX 1 0 AD9553 UP/2 CONTROL HOLD DN/2 FDBK/2 XO LOCK REF DET DET DET 2 DETECT SEL A B XO P2 OUT2 CLOCK DET DET A MUX BW 10 CTRL REFA 0 x2 1 3350-4050 P2 0 RA FREF MHz 1 0 UP 5 or 6 P 2 5 1 14 F CHARGE LOOP P0 P1 PUMP FILTER VCO OUT1 REF D DIFF DN /5A x2A RA 3 10 HOLD P0 P1 OUTPUT DET DET B MODE FDBK N CONTROL x2 1 REFB/REFA 0 RB 20 3 0 5 1 14 1 0 N /5B x2B RB 3 3 3 OUTPUT MODE/ RA, x2A, /5A REGISTER BANK DET DET XO SERIAL PORT RB, x2B, /5B XO RXO, DCXO CTRL SPI CTRL XTAL x2 R XO N, P0, P1, P2 1 4 DCXO TUNING REF SEL A3:0 CTRL CONTROL 14 0 PRECONFIGURED XTAL TEST DIVIDER SETTINGS 6 RB REF DIFF Y5:06

Digital PLL Detailed Block Diagram(AD9548 Shown) OUT_RSET AD9548 POST OUT0P DIV OUT0N REFA POST OUT1P DIFFERENTIAL DIV OUT1N REFAA OR SINGLE-ENDED REFB POST OUT2P REFBB DIV OUT2N REFC DIGITAL PLL CORE POST OUT3P REFCC DIV OUT3N ÷S REFD REFDD CLKINP PROG. DIGITAL TW CLAMP CLKINN TDC/PFD LOOP AND DDS/DAC 4 OR 8 HISTORY CLOCK ÷R FILTER DISTRIBUTION EXTERNAL ANALOG PHASE HOLDOVER FILTER CONTROLLER LOGIC INPUT REF MONITOR LOW NOISE CLOCK MULTIPLIER M0 TO M7 IRQ AND STATUS CONTROL AMP IRQ LOGIC LOGIC SYSCLK PORT DIGITAL SYSCLKN SYSCLKP INTERFACE 9 2 8 0 -7

AD9558 Digital PLL Block Diagram XO or XTAL XO frequencies /M0 - /M3b are 10MHz-180MHz 10-bit integer SYNC RESET PINCONTROL M0 – M7 IRQ XTAL 10MHz-50MHz dividers Sy stem PLL (PLL3 ) Out0 /M0 Out0 b SPI/I²C ROM Multi-Function IO Pins O ut0,1,2,3,4: 360 kHz to 1.25GH z; SPI / Register RF x2 Frame Sync Mode Only /2 I²C Serial Port & (Control and Status Divider 1 Space /3 to /11 Out1 EEPROM FSM Read back) /M1 Out1 b Out5: 2KH z to1.25GH z Max PFD 1.25 GHz Out2 Out2 b /N3 /CP RF Divider 2 /M2 Out3 LF2kHz to 1.25GHz /3 to /11 Out3b REFA_P /2 REFA_N /M3 Out4 Out4 b REFA_P Freerun /2 x2 /M3b REFA_N TW Frame Sync Pulse x2 Out5 REFA_P /2 R Divider (20-bit) Tuning Out5b Digital DP FD REFA_N Word 30-bit NCO Frac1/ Loop Clamp & REFA_P /2 /N1 REFA_N Mod1 Filter History Integer divider 17-bit 24b / 24b /N2 Output PLL (PLL2) REF Monitoring Integer Resolution Digital PLL (PLL1) Automatic PFD/CP LF Switching VCO2 2 kHz or 8 kHz Frame Sync Signal 3.45 to 4.05 AD9558 GHz. PLL 2 LF cap STATUS8

Generating Clocks using DDS Fsysclock(fc) DAC out Filter out Limiter Reconstruction Clock out DDS Filter Ideal Time Domain 0 Response t t t Ideal Frequency Domain Response f f f fc 2fc 1 1 3 5 7 Odd harmonic series "Real World" Frequency Response f fc f f 2fc 1 3 5 7 The DDS chip can synchronize to a user’s reference. An on-chip clock multiplier can generate the fast clock needed to clock the NCO/DAC. A frequency tuning word may be written to set the output clock rate. External filtering removes unwanted images. A squaring function then converts sine wave to square wave.9

Common Uses for PLLs Frequency translation Jitter Cleanup Redundant clocking Holdover Clock Distrbution10

Frequency Translation Example: REF R INPUT Phase / (Fin) Divider Frequency Charge Loop P (Post) OUTPUT VCO FREQUENCY Detector Pump Filter Divider (Fout) (PFD) N (Feedback) Divider 19.44 MHz (SONET) to 156.25 MHz (10 Gb/s Ethernet):  R divider=81, N=3125, P divider = 12  Phase detector frequency: 120 kHz  VCO frequency: 1875 MHz11

Jitter Clean-up Backplane has lots of noise Clean signal from sources Clock received by main clock board line card is contaminated Clock received from back plane is Digital PLL w/ a used to establish phase and Programmable frequency of the output Digital loop Filter capable of <1 Hz BW HOW?12

Reference Input Switchover and Holdover :Holdover:An ADI clock featuring holdover provides output signals even when the reference inputdisappears. This feature allows designers to build systems that benefit from greater uptime,while alleviating fears of intermittent or unreliable reference signals crashing the system.Switchover:An ADI clock featuring switchover capability has multiple reference input ports. If one of thereferences fails, the clock device will use one of the alternate references instead. Animportant aspect of all the switchover functions provided in ADI clock devices is that no runtpulses and no extra long pulses result from this change. Downstream PLLs will not lose lockas a result, of or during, switchover - even when no predefined relationship exists betweenthe phases of the various reference input signals.Holdover and Switchover can be initiated either as directed by a controller/processor in thesystem, or by using the on-chip monitoring function which will automatically perform aswitchover and/or holdover when the active reference input goes quiet.

Switchover, Synchronization, and Holdover NOTE But what happens when the to output is synchronized primary reference disappears? primary reference The output slowly transitions until it is phase with the back-up reference

Clock Distribution Example RMS Jitter addedExample: AD9512 to signal at A 225 fs RMS Divide by 1-32 LVPECL Buffer 225 fs RMS LVPECL Divide by 1-32 Buffer 225 fs RMS LVPECL Divide by 1-32 BufferA 1:5 Fanout Buffer 350 fs RMS LVPECL to Divide by 1-32 LVDS 1-3 ps RMS LVPECL to Divide by 1-32 Delay 1-10ns CMOS15

14-Output Clock Generator What’s Inside  Two reference clock inputs, A/B  Automatic or manual reference switching and holdover  Integer-N frequency synthesizer  Voltage-Controlled Oscillator (VCO)  Programmable dividers  With output-to-output phase offset  Adjustable delay lines  LVPECL, LVDS/CMOS logic  Up to 14 clock output drivers  5 versions: -0,1,2,3,4  On-chip VCO frequency ranges from 1.45 GHz to 2.95 GHzAll critical timing functions integrated in a single IC atjitter levels less than 500 fs rms16

The World Leader in High-Performance Signal Processing Solutions Applications forPhase-locked Loops (PLLs)

Application – Wireless Transceiver Card ADC Clock to A-D Converters ADC ADC User’sTRX Cards Reference Clock TRX ADC Clock Distribution IC DDC or Critical Clock Functions on Transceiver Card: ASIC Clock to • clean-up jitter on user’s input reference Digital Chips • up-convert user reference frequency to highest DUC or frequency needed, usually driven by DAC clock FPGA requirements • generate multiple frequencies for RX & TX DAC • provide low jitter clocks for converters Clock to D-A Converters • generate mix of LVPECL, LVDS, CMOS clocks DAC • adjust phase or delay between clock channels • offer isolation between clock channels18

Application – Line Card Optical Transceiver Backplane CDR Digital XCVR SERDES Switch Limiting Engine Digital PIN TIA & EQ AMP Cross Line Card Point Signal Laser LDD Conditioner Clock Power Generation/ Sequencing Distribution Switch Card New ADI clock products suchLine Card as the AD9557 and AD9548 are tailored for network applications. Switch Card Specific AD9548 example on next pageBackplane19

SyncE / IEEE1588 Hybrid(with Hooks for Pure IEEE1588) Timing Card 2Line Card n Line Card Tx Timing Card GPS AD9557 BITS AD9548 AD9547 1 PPS Backplane Backplane MAC/PHY SPI / I2C SyncE Clock Recovering Clock/Frequency Control TCXO / OCXO Recovered clocks + IEEE1588 Time Stamp from Line cards Rx Frequency 1 PPS XO AD9553/7 Synchronization (Optional) CPU / FPGA / DSP Time Stamps IEEE1588 Time of Day Time of Day Offset Adjustment Protocol / Algorithm

ADI’s Complete Clock Portfolio Analog and Digital PLLs  Used for frequency multiplication/translation  Redundant Clocking and Holdover Synthesizers  Used for clock generation Clock Distribution  Used for sending the identical clock to multiple chips  Also used for logic level translation (i.e., LVPECL to LVDS)  May include frequency dividers (/2, /4, etc.)  May include skew adjustment21

What Makes Us Special? DDS (Direct Digital Synthesis) for synthesizers  Uses a DAC for synthesizing output frequencies Digital PLLs  Dynamically reconfigurable loop BWs from 100 kHz to 10 Hz.  Allows easy implementation of holdover and reference monitors LC Tank Oscillators  Much lower noise than ring oscillators The “Phase Noise Experts” (Experience with ADC/DACs)  Experience measuring jitter to < 100 fs. We’re “Process Agnostic”  We have CMOS/BiCMOS/Bipolar processes available to us.  Allows us to use the best process for the job.22

Questions from audience23

Upcoming FUNDAMENTAL webcasts Printed Circuit Board Layout  February 8th at 12pm (EST) Frequency Synthesis: Part 1, PLL  March 7th at 12pm (EST) Frequency Synthesis: Part 2, DDS  April 11th at 12pm (EDT) www.analog.com/webcast

Thank you Paul KernClock & Signal Synthesis Team Greensboro, NC

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Clock Fundamentals

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