compressed form in the tester memory and transferred to the chip wherethey are decompressed and applied to the coresstand-alone BISTBut it has a low fault detection probability due to RPR Faultsrandom-pattern-resistanthybrid BISTSuitable for manufacuring test only (more cost effective)Hybrid BIST involves storing some data on the tester to help detect RPR faultsThe simplestapproach is to perform ATPG for RPR faults not detectedby pseudorandom BIST to obtain a set of deterministic testpatterns that “top up” the fault coverage to the desiredlevel, and then store those patterns directly on the tester.test data compression.
The amount of compression depends on n how skewed the frequency of occurrence is for thedifferent codewordss. If all of the codewords occur with equal frequency,then no compression can be achievedtest vectors in a test set tend to have a lot of correlationsThe don’t care bits (X’s) provide flexibility to allow a blockto be encoded with more than one possible codeword. The shortest possibleskewed
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 22, NO. 6, JUNE 2003
Test vector compression in Digital Testing
Prof.Dr. : Ihab Talkhan
Eng. Amr Abd El latief Abd El Al
Eng. Mohammad Ahmed Hamed
Benefits of data Compression
Why does compression works (on testing vector)
Test vector compression schemes Categories
Data compression techniques
Hufman Coding method
• Test Levels: System Testing, Chip Testing
• Increasing integration density results in:
• more scan cells
• more faults.
• external testing: involves storing all test vectors and test
response on an external tester.
• Tester Challenges:
Overcoming approaches :
But it has a low fault detection probability due to
use a combination of BIST and test vectors
test data compression. (Described Here)
it reduces the amount of data stored on the tester,
it can reduces the test time for a given test data bandwidth
Test vectors are highly compressible because typically
only 1% to 5% of their bits are specified (care)bits. The
rest are don’t-cares.
because faults are structurally related in the circuit test
cubes also tend to be highly correlated
• simple form of data compression
• runs of data means line of data
• Good method for data that contains many such runs
Careful ordering of the test cubes maximizes the number of 0s in the
difference vectors, thereby improving the effectiveness of run-length
1 -partitions the original data into n-bit symbols.
2 - Uses a dictionary to store each unique symbol.
3 - encoding each n-bits using a b-bit code word
corresponds to the symbol’s index in the dictionary
initialization : put all symbols on a list sorted according to their frequency count
repeat until the list has only one symbol left:
from the list pick two symbols with the lowest frequency counts
form a Huffman sub-tree that has these two symbols as a child nodes
and create a parent node
Assign the sum of the children's freuency counts to the parent and insert it into the list such that
order is maintained
Delete the children from the list
Assign a code word for each leaf based on the path from the root
The technique is based on a linear decompressor which consists of wires,XOR gates and flip-flops.
It has two types
a) Static reseeding
Compute a seed for each cube, the seed is loaded in the LFSR and it produces the test vectors, so we
store only the seed.
it has two disadvantages
- It must be as large as the test vector length.
- The circuit is idle during the vector generation
b) Dynamic reseeding
Solves the problem of static reseeding, it uses a network that expands the output to fill n output scan
chains while creating the result
Broadcast scan method
Uses the fact that many bits are don't care, it can be either independent or
-------------- 1) Apply ATPG TO Both circuits.
2) NOw we have a set of patterns to detect CUT-2 and part of CUT-1 Faults.
3) Apply the don't care bits to detect CUT-1 Faults
4) NOw we have a `minimized set` with appropriate fault coverage/
Dependent Broadcast scan method
To allow the compression of the test vectors and to avoid the problem of equal cells in the scan chain,
we apply Illinois scan based compression technique.
In this technique instead of applying the test output of the ATPG to the scan chain, we partition it to
few partitions, we then either apply it as (broadcast - in parallel) and take the output of all stages, or
apply it serially(the output of stage i is the input of stage i+1) and so on, based on the partitioning
mechanism this technique is divided into
1) Static reconfiguration (uses a multiplexer to get the set of scan chains)
2) Dynamic reconfiguration (The configuration change every slice which is more flexible)
Illionis scan uses two modes of operations:
- Broadcast : Broadcasts one tester channel to multiple chains
- Scan : applies them in serial
The configuration can be done using a multiplexer to choose which channels the tester channel will
The geometric method uses a loseless compression technique.
It depends on four main shapes: point - line - traingle - rectangle
The algorithm goes like this
1) Start with a random test vector as a start point
2) Sort all of the other vectors depending on their correlation with the first vector.
3) Use shape covering algorithm to choose the largest shape that cover a group of zeros or
4) Choose the optimal result of covering shapes
5) Encode the results
Comparison of different techniques
While most techniques discussed have good performance on commercial use
there are few drawbacks
1) Linear decompression has the simplest structure (only XOR Gates and
registers) for cases of multiple scan chains we need to compress/decompress
each chain independently which takes more time and not parallelizable.
2) Broadcast scan is also simple to implement, but it has a redundancy issue
(i.e. many scan chains may have the same bit value at the same location)
3) Geometric method is less efficient and only experimentally tested, and
require more computation than other methods
 Survey of Test Vector Compression Techniques,Nur A. Touba
[ 2]An Efficient Test Vector Compression Scheme Using Selective Huffman Coding
3] Using a Single Input to Support Multiple Scan Chains,Kuen-Jong Lee Jih-Jeen Chen,Cheng-Hua
 LFSR-Based Test-Data Compression with Self-Stoppable Seeds, M. Koutsoupia E. Kalligeros X.
Kavousianos D. Nikolos
 An Efficient Test Vector Compression Technique Based on Geometric Shapes , Saif al Zahir, Aiman
El-Maleh, and Esam Khan
 Reconfiguration Technique for Reducing Test Time and Test
Data Volume in Illinois Scan Architecture Based Designs, Amit R. Pandey† and Janak H. Patel