14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 1VHDL(or beyond LAB #1 experiments)‫בנושא‬ ‫העשרה‬ ‫הרצאת‬Version 1.3 -...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 5Concepts CoveredLanguage background, Design FlowArchitecture, EntityIn...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 9Topics can all be found in this & other books14/04/2013 VHDL - Amos Za...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 13A very simple Package - exampleCollection of declarations (including:...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 17wait statementsHere is a list of all possible wait statement typeswai...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 21MultiplyingstructuraldescriptionCH 08 14/04/2013 VHDL - Amos Zaslavsk...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 25A conditional generate example (in gen loop)beginadder_gen: for i in ...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 29Use the package-- architecture with no component declarationslibrary ...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 33Direct-Moore MachineOUT = PSNS = g(IN,PS)INPSgPSINclockoutputsNSinput...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 37Simple behavioral ROM codinguse work.pkg_rom.all ;entity rom6 isport ...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 41A record of records - uP instruction23 bit8 bitExponent MantissaSfloa...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 45A simple Dual Port RAMdata_inwrite_addressramsignal typemem_array8204...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 49Playing a little with descriptionsbeginprocess ( clk )beginif rising_...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 53Using the Package & Functionuse work.utils.all ;entity comp isport ( ...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 57Real & ComplexPackagesCH 11 14/04/2013 VHDL - Amos Zaslavsky © Copyri...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 61simple examplefor readingstimulus fromtext fileCH 12 14/04/2013 VHDL ...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 65Writing resultsto a text fileCH 12 14/04/2013 VHDL - Amos Zaslavsky ©...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 69Simple example of manipulating binary filesprocess-- declaring a non-...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 73VHDL-2008 is here (alive and kicking..)The Original VHDL-1987 standar...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 77We will not go into all the modifications..For More information ( or ...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 81Topics that will be Mentioned hereMore convenient combinatorial descr...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 85Comments-- this comment ends with <CR> <LF>y <= a and b and c ; -- ri...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 89More convenientmixed bit & vectorLogical operationsCH 02 14/04/2013 V...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 93What had to be done in older versions-- no reduced operations on old ...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 97boolean, integer, real & time arrays-- decoder 3->8 using numeric rel...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 101Problems with old = relations’1‘’H‘false’X‘’Z‘false’U‘’U‘trueReturn ...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 105Other Matched relationsAre all created by operations on the previous...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 109More Powerful vector data typesThe new Powerful data types– Unsigned...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 113Example of floating point divider-- example of a floating point divi...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 117The ?? condition Operator-- Introducing the condition operator "??"l...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 121Where can this implicitly implied ?? be usedAfter an if clause (as i...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 125An new elegant matching case? statementcase? din is -- using the ?= ...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 129Complete sensitivity list in comb system-- complete sensitivity list...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 133The to_string(_) functionHere is an exampleprocess ( din ) -- din is...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 137wiring of signals constants & expressionsin VHDL-87 only clean signa...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 141New coding stylelibrary ieee ;use ieee.std_logic_1164.all ;use ieee....
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 145Monitoring (Accessing)signals through hierarchiesusing external name...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 149Force & Release assignmentsOverride all normal resolved values assig...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 153Force & Release assignments of portsVHDL-2008 allows us to force the...
14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 157More advanced topicsIP (Intellectual Property) protection– Pragma ba...
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Enrichment lecture EE Technion (parts A&B) also including the subject of VHDL-2008 (April 2013)

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Enrichment lecture EE Technion (parts A&B) also including the subject of VHDL-2008 (April 2013)

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Enrichment lecture EE Technion (parts A&B) also including the subject of VHDL-2008 (April 2013)

  1. 1. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 1VHDL(or beyond LAB #1 experiments)‫בנושא‬ ‫העשרה‬ ‫הרצאת‬Version 1.3 - April 2013Amos Zaslavsky14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 2Presentation OutlineSECTION 1: Known (~5 min)SECTION 2: Un-Known (~40 min)SECTION 3: New (~40 min)SECTION 4: Questions (~5 min)2:30-2:352:35-3:153:15-3:553:55-4:0014/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 3Known:Topics covered by LAB ExperimentsSECTION 114/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 4Lab #1 ExperimentsVHDL Basics
  2. 2. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 5Concepts CoveredLanguage background, Design FlowArchitecture, EntityInternal data types, Operators, assignments,std_logic, std_logic_vector & vector mathProcessSignal, Variables and their proper usageIf statements, case statements, loopsSimulation Tool: Modelsim and running simulations with scriptsSynthesis Tool: Quartus, Project, Device & Pin assignments, RTL viewerCombinatorial hardware descriptionsSynchronous hardware descriptionsDecomposition of Design to RTL block descriptionSync design rulesVHDL to => graphics (symbol generation & graphic wiring)Lot’s of material14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 6Concepts CoveredVHDL Structural descriptions: Hierarchy & wiringUsing generic parametersGraphic wiring to => structural VHDLSimulation using Test BenchesSome basic Generators for Test BenchesState Machines (mealy,Moore) and their codingTiming of sync systems & increasing fmax performanceAutomatic State assignmentsCoding example of PS/2 host systemCompiling (preparing) Gate-Level LibrariesGate-Level simulationHardware debug (Signal TAP) and in system memory editorA bigger VHDL design task using PS2A/D mixed projectLot’s of material14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 7Un-Known:Some more topics on VHDLSECTION 214/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 8‫מטרה‬‫כיוונים‬ ‫כמה‬ ‫על‬ ‫ההצבעה‬‫חשובים‬(‫השפה‬ ‫יכולות‬ ‫כל‬ ‫על‬ ‫לעבור‬ ‫ומבלי‬ ‫בחומר‬ ‫להעמיק‬ ‫)מבלי‬Presentation goals
  3. 3. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 9Topics can all be found in this & other books14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 10Topics that will be Mentioned here...PackageWait & assert statementsStructural descriptions– Components with generals ports– Multiplying structural description (generate)– conditional generate– architectures with out component declarations– Direct InstantiationsForcing State Assignments through code in direct machinesSimulation Only !CH 01CH 06CH 08CH 09All other topics are relevantfor simulation & Synthesis14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 11Topics that will be Mentioned hereComposite data types– Trying to describe a ROM– Attributes of arrays– Records– a DPRAM exampleSubprograms: functions & proceduresUsing files– Simple example of reading a stimulus text file– Simple example of writing a results text file– Simple examples of operations on non-text filesCH 10CH 11CH 1214/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 12PackagesCH 02
  4. 4. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 13A very simple Package - exampleCollection of declarations (including: constants, data types,functions & procedures - shown later)can be visible from many placesA simple examplepackage math isconstant pi : real := 3.14159 ;constant e : real := 2.71828 ;end math ;CH 02 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 14insert use statement before each primary unituse work.math.all ;entity area isport ( r : in real ; -- radiusa : out real ) ; -- areaend area ;architecture arc_area of area isbegina <= pi * r * r ;end arc_area ;use work.math.all ;entity perim isport ( r : in real ; -- radiusp : out real ) ; -- perimeterend perim ;architecture arc_perim of perim isbeginp <= 2.0 * pi * r ;end arc_perim ;Primary unitSecondary unitPrimary unitSecondary unitCH 0214/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 15Wait & AssertstatementsCH 06Simulation Only !14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 16testing time-out of handshake (test bench)processbeginrequest <= 0 ; wait for 2 ms ;request <= 1 ;wait until acknowledge = 1 for 10 ms ;assert ( acknowledge = 1 )report " Time out " severity error ;wait ;end process ;acknowledge(case I)10 msErrorrequestokacknowledge(case II)requestacknowledgeDeviceUnder TestTester2 msCH 06
  5. 5. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 17wait statementsHere is a list of all possible wait statement typeswaitwait on ( )wait until ( )wait for ( )wait on ( ) until ( )wait on ( ) for ( )wait until ( ) for ( )wait on ( ) until ( ) for ( )Wait statements are generally not used for synthesis !Wait statements are powerful statements used forsimulation with test benches !we will have muchmore on this subjectin section 6CH 06 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 18Components withgeneral portsCH 0714/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 19components with general ports (vector)entity comp isport ( a , b : in bit_vector ;eq : out bit ) ;end comp ;architecture arc_comp of comp isbeginprocess ( a, b )beginif a = b theneq <= 1 ;elseeq <= 0 ;end if ;end process ;end arc_comp ;No widthspecifiedCH 07 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 20Port limitation determined with instantiationentity comp2 isport ( a1,a0,b1,b0 : in bit_vector(3 downto 0) ;eq : out bit ) ;end comp2 ;architecture arc_comp2 of comp2 iscomponent compport ( a , b : in bit_vector ;eq : out bit ) ;end component ;signal eq0 , eq1 : bit ;beginu0: comp port map (a0,b0,eq0) ;u1: comp port map (a1,b1,eq1) ;eq <= eq0 and eq1 ;end arc_comp2 ;equivalent with integers:integer range 0 to 15CH 07
  6. 6. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 21MultiplyingstructuraldescriptionCH 08 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 22Multiplying structure with generatearchitecture arc_adder4g2 of adder4g2 iscomponent faport ( a,b,ci : in bit ;s,co : out bit ) ;end component ;signal c : bit_vector (4 downto 0) ;beginc(0) <= ci ;adder_gen: for i in 0 to 3 generateu: fa port map (a(i),b(i),c(i),s(i),c(i+1)) ;end generate ;co <= c(4) ;end arc_adder4g2 ;CH 0814/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 23Results of structural multiplicationThe generated instantiationsu0: fa port map (a(0),b(0),c(0),s(0),c(1)) ;u1: fa port map (a(1),b(1),c(1),s(1),c(2)) ;u2: fa port map (a(2),b(2),c(2),s(2),c(3)) ;u3: fa port map (a(3),b(3),c(3),s(3),c(4)) ;The assignments of the boundariesc(0) <= ci ;co <= c(4) ;CH 08 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 24conditionalgenerateCH 08
  7. 7. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 25A conditional generate example (in gen loop)beginadder_gen: for i in 0 to 3 generatecarry_in: if i=0 generateui: fa port map ( a(i) , b(i) , ci , s(i) ,c(i+1)) ;end generate ;mid_section: if (0 < i) and (i < 3) generateum: fa port map ( a(i) , b(i) , c(i) , s(i) ,c(i+1)) ;end generate ;carry_out: if i=3 generateuo: fa port map ( a(i) , b(i) , c(i) , s(i) , co ) ;end generate ;end generate ;end arc_adder4g3 ;CH 08 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 26parameter dependant conditional generateentity syncbuff isgeneric ( sync : boolean := true ) ;port ( clk , din : in bit ; dout : out bit ) ;end syncbuff ;architecture arc_syncbuff of syncbuff iscomponent dffport ( clk , d : in bit ; q : out bit ) ;end component ;beginyes: if sync generateus : dff port map (clk,din,dout) ;end generate ;no: if not sync generatedout <= din ;end generate ;end arc_syncbuff ;Quartus generated symbolCH 0814/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 27architectures with outcomponent declarationsCH 08 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 28Collect all component declarations to package------------------------------------------- a package with component declarations-----------------------------------------package gates iscomponent nandgport ( in1,in2 : in bit ;out1 : buffer bit ) ;end component ;component norgport ( in1,in2 : in bit ;out1 : buffer bit ) ;end component ;..end gates ;gates1.vhdCH 08
  8. 8. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 29Use the package-- architecture with no component declarationslibrary my_lib1 ;use work.gates.all ;entity nocomp isport ( s,r : in bit ;q,q_bar : buffer bit ) ;end nocomp ;architecture arc_nocomp of nocomp issignal x1 , x2 : bit ;beginu1: nandg port map ( s , s , x1 ) ;u2: nandg port map ( r , r , x2 ) ;u3: nandg port map ( x1 , q_bar , q ) ;u4: nandg port map ( x2 , q , q_bar ) ;end arc_nocomp ;Make entity visibleMake component declarations visibleCH 08No component declaration needed14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 30VHDL93 &DirectInstantiationsCH 0814/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 31Direct instantiation (no component & config)-- direct instantiation (VHDL-93)library gates1, gates2 ;entity dirinst isport ( s,r : in bit ;q,q_bar : buffer bit ) ;end dirinst ;architecture arc_dirinst of dirinst issignal x1,x2 : bit ;beginu1: entity work.nandg(arc1_nandg) port map (s , s ,x1 ) ;u2: entity work.nandg(arc2_nandg) port map (r , r ,x2 ) ;u3: entity gates1.nandg(arc1_nandg) port map (x1, q_bar,q ) ;u4: entity gates2.nandg(arc2_nandg) port map (x2, q ,q_bar) ;end arc_dirinst ;Make lib visibledirect connection to entityno need for componentdeclarationconfiguration is done hereCH 08 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 32Forcing State Assignmentsthrough code in directmachinesCH 09
  9. 9. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 33Direct-Moore MachineOUT = PSNS = g(IN,PS)INPSgPSINclockoutputsNSinputs OUTFFscombinatorial systemCH 09 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 34Force state assignments to fit output requirements-- type state is(idle, grant1, grant2, grant3) ;subtype state is std_logic_vector ( 2 downto 0 ) ;-- direct-moore state assignmentsconstant idle : state := "000" ;constant grant1 : state := "100" ;constant grant2 : state := "010" ;constant grant3 : state := "001" ;signal present_state , next_state : state ;Avoid any assignments to outputs in the combinatorialprocessWrite direct assignments of outputs (3rd process)a1 <= present_stste(2) ;a2 <= present_stste(1) ;a3 <= present_stste(0) ;Implementing a Direct Moore machineandDirect assignmentsCH 0914/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 35Trying to describe aROMCH 10 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 36Initialization Package of ROM-- using named associations, slices and the others clausepackage pkg_rom istype mem_array is array (0 to 7) of bit_vector(3 downto 0) ;constant rom : mem_array := (0 => "1010" ,1 to 2 => "1100" ,3 | 5 => "0000" ,others => "1111" ) ;end pkg_rom ;CH 10
  10. 10. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 37Simple behavioral ROM codinguse work.pkg_rom.all ;entity rom6 isport ( address : in integer range 0 to 7 ;data : out bit_vector(3 downto 0) ) ;end rom6 ;architecture arc_rom6 of rom6 isbegindata <= rom(address) ;end arc_rom6 ;CH 10 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 38Attributes of arraysCH 1014/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 39attributes usage exampleInverting a sign of a vector that represents a signed number (in 2C)invert := 0 ;for i in 0 to 7 -- THIS LINE WILL BE CHANGED toif invert = 1 theny(i) <= not x(i) ; -- inverting bitselsey(i) <= x(i) ; -- passing bitsif x(i) = 1 theninvert := 1 ;end if ;end if ;end loop ;Possible replacements (a more general coding style)for i in xreverse_range loopfor i in xright to xleft loopfor i in 0 to (xlength - 1) loopx(7) x(6) x(5) x(4) x(3) x(2) x(1) x(0)y(7) y(6) y(5) y(4) y(3) y(2) y(1) y(0)2C sign inversionCH 10General descriptionalso popular withsubprograms14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 40RecordsCH 10
  11. 11. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 41A record of records - uP instruction23 bit8 bitExponent MantissaSfloat recordopcode : float_operation op1 : float op2 : floatinstruction recordfadd, fsub, fmul, fdivCH 10 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 42A record of records - uP instructiontype myloat isrecordsign : bit ;exponent : bit_vector( 7 downto 0) ;mantissa : bit_vector(22 downto 0) ;end record ;type float_operation is ( fadd , fsub , fmul , fdiv ) ;type instruction isrecordopcode : float_operation ;op1 : myfloat ;op2 : myfloat ;end record ;signal x : instruction ;CH 1014/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 43A record of recordsA separate assignments for each fieldx.opcode <= fdiv ;x.op1.sign <= 0 ; -- IEEE-754 -> +7.5x.op1.exponent <= "10000001" ;x.op1.mantissa <= "11100000000000000000000" ;x.op2.sign <= 0 ; -- IEEE-754 -> +197.625x.op2.exponent <= "10000110" ;x.op2.mantissa <= "10001011010000000000000" ;Assignment through aggregates (this is positional association, nameassociation also exists)x <= ( fadd ,( 0 , "10000001" , "11100000000000000000000" ) ,( 0 , "10000110" , "10001011010000000000000" ) ) ;CH 10 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 44DPRAM example(Behavioral Description)CH 10
  12. 12. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 45A simple Dual Port RAMdata_inwrite_addressramsignal typemem_array820488syncprocesssyncWriteOnlyregisterCombROMreaderdata_out8weclkenread_address8Comb read may not bepossible with somedevice memoryarchitecture resourcesCH 10 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 46A simple Dual Port RAM code (1 of 2)library ieee ;use ieee.std_logic_1164.all ;entity dpram isport ( clk : in std_logic ;write_address : in integer range 0 to 255 ;we : in std_logic ;data_in : in std_logic_vector(7 downto 0) ;read_address : in integer range 0 to 255 ;data_out : buffer std_logic_vector(7 downto 0) ) ;end dpram ;architecture arc_dpram of dpram istype mem_array is array (0 to 255) of std_logic_vector(7 downto 0) ;signal ram : mem_array ;beginCH 1014/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 47A simple Dual Port RAM code (2 of 2)beginprocess ( clk )beginif rising_edge (clk) thenif we = 1 thenram(write_address) <= to_X01(data_in) ;end if ;end if ;end process ;data_out <= ram(read_address) ;end arc_dpram ;CH 10 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 48Wy behavioral description of memory ?To show ways for writing behavioral code that will mostlikely make third party tools Instantiate memory LPMs anduse memory resources that are more efficientCode is more user friendly for humans (more readable,and easier to change) and also portable to other vendors.Don’t have to prepare a separate mif or hex file (load inVHDL code)Reduce LPM RTFM (read the f... manual) activityFlexibility: make non standard versions of memory (RAMwith: direct outputs, sync clear,Backspace delete, CAM,prevent certin data writes, make memory shiftable..)Only for standard memory descriptionsFor humansFor small memoriesCH 10
  13. 13. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 49Playing a little with descriptionsbeginprocess ( clk )beginif rising_edge (clk) thenif we = 1 and data_in /= “0000” thenram(write_address) <= to_X01(data_in) ;end if ;end if ;end process ;data_direct3 <= ram(3) ;end arc_dpram ;CH 10make directdata syncdo not allow0000 data inNO standard LPMS !14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 50Subprograms:functions &ProceduresCH 1114/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 51Sub-programsFunction– Parameters are only of mode (direction) in– Returns a single value– The returned value is an expression sig_or_var [<= | :=] fun(param..)Procedure– Parameters can be of mode (direction): in out and inout– Multiple values can be returned through parameters values– Usage is done by writing the procedure as a statement proc(param..)Mostly used for:– Conversions between data types– Performing calculations that are not built into the language– Overloading existing operations so they can be preformed on newdata types (e.g "and" operation on std_logic) & resolution fuction– Specified in any declarative section (before begin) and in packageCH 11 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 52Using package body for file specificationpackage utils isfunction bool2bit( b : boolean ) return bit ;end utils ;package body utils isfunction bool2bit( b : boolean ) return bit isbeginif b thenreturn 1 ;elsereturn 0 ;end if ;end bool2bit ;end utils ;bodyCH 11
  14. 14. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 53Using the Package & Functionuse work.utils.all ;entity comp isport ( a , b : in bit_vector ( 7 downto 0 ) ;equal : out bit ) ;end comp ;architecture arc_comp of comp isbeginequal <= bool2bit ( a = b ) ;end arc_comp ;CH 11 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 54External function in package declarationpackage string_utils is----------------------------- function declarations -----------------------------function ucase_str( s : string ) return string ;...end string_utils ;external function declarationCH 1114/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 55Internal function in a package bodypackage body string_utils is-------------------------------- internal package funcion --------------------------------function ucase_chr( c : character ) return character isbegincase c iswhen a to z =>return characterval(characterpos(c) - 32) ;when others =>return c ;end case ;end ucase_chr ;...a function specifications with no declaration in package declarationinternal function specificationCH 11 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 56External functions in a package body---------------------------------- external package functions ----------------------------------function ucase_str( s : string ) return string isvariable ucase : string( sleft to sright) ;beginfor i in sleft to sright loopucase(i) := ucase_chr(s(i)) ;end loop ;return ucase ;end ucase_str ;...end string_utils ;This function uses the ucase_chr function specified in the upper part of package bodyfunction specificationgeneralwidthCH 11
  15. 15. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 57Real & ComplexPackagesCH 11 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 58Random signals, Sinus , more ..CH 11library ieee ;use ieee.math_real.all;use ieee.math_complex.all;..sinout <= sin( w * t ) ;..UNIFORM(seed1,seed2,real_stim);int_stim := integer(trunc(real_stim* 4096.0));External packages canenhance the randomcapabilities14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 59Using files(mainly for test benches &Memory Initializations)CH 12 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 60Text files (for test benches & initializations)Basic text files supportuse std.textio.all ;– read, write, readline, writeline supportMore text file supportuse std.textio.all ;library ieee ;use ieee.std_logic_1164.all ;use ieee.std_logic_textio.all ;Gives more support for handling text files:– Read and writes std_logic, Read and writes Hexadecimal andOctalBinary file support tooCH 12TEXT filesTEXT files
  16. 16. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 61simple examplefor readingstimulus fromtext fileCH 12 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 62Simple example of reading stimulus form filetest vectorsC:PROJINFILE3.TVFile readerentry #0bit_vector8stim100 ns 1010101050 ns 11111111100 ns 0011001150 ns 11110000...relative timeentry #1CH 1214/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 63Simple example of reading stimulus form fileuse std.textio.all ;entity filegen3 isport( stim : out bit_vector(7 downto 0) ) ;end filegen3 ;architecture arc_filegen3 of filegen3 issignal done : boolean := false ;beginprocess-- file infile : text is in " c:vhdinfile3.tv" ; -- vhdl-87file infile : text open read_mode is "c:vhdinfile3.tv" ;variable l : line ;variable t : time ;variable entry1 : bit_vector(7 downto 0) ;variable good : boolean ;beginCH 12 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 64Simple example of reading stimulus form filewhile not endfile(infile) loopreadline(infile,l) ;read(l , t , good) ;next when not good ;read(l , entry1 , good) ;next when not good ;stim <= entry1 ;wait for t ; -- t is incremental delay timeend loop ;done <= true ;file_close (infile) ; -- not usable with VHDL-87assert false report "End of test vectors"severity note ;wait ;end process ;end arc_filegen3 ;CH 12
  17. 17. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 65Writing resultsto a text fileCH 12 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 66example of dumping results to a filetest vectorsC:PROJDUMP.TXTFile writerTime out1 out2100 ns 67 01010000200 ns 33 00001111..std_logic_vector8out1clkout2integerCH 1214/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 67example of dumping results to a fileprocess-- file dumpfile : text is out "c:vhddump.txt" ; -- 87 syntaxfile dumpfile : text open write_mode is "c:vhddump.txt" ; -- 93variable l : line ;constant header : string(1 to 30):= "Time out1 out2 " ;beginwrite ( l , header ) ; -- haederwriteline ( dumpfile , l ) ;loopwait until rising_edge(clk); -- dump resultswrite ( l , now , left , 10 ) ;write ( l , out1, left , 10 ) ;write ( l , out2, left , 10 ) ;writeline( dumpfile , l ) ;end loop ;end process ;CH 12 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 68Operations onnon-text filesCH 12
  18. 18. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 69Simple example of manipulating binary filesprocess-- declaring a non-text filetype byte_file is file of character ;-- VHDL 93 coding stylefile source : byte_file open read_mode is "c:aba.bin" ;file target : byte_file open write_mode is "c:ima.bin" ;variable b : character ;beginwhile not endfile(source) loop -- copy aba to new imaread ( source , b ) ;write ( target , b ) ;end loop ;file_close ( source ) ;file_close ( target ) ;aba.bin ima.bincopyVHDL87 files can be closed only by quitting simulationread & write are actually built in commandsdeclaring a non text fileCH 12 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 70Simple example of manipulating binary files-- opening pipi again (external filename can be changed)file_open ( source , "c:aba.bin" , read_mode ) ;-- opening existing kaka for appendingfile_open ( target , "c:ima.bin" , append_mode ) ;while not endfile(source) loop -- copy aba to ima againread ( source , b ) ;write ( target , b ) ;end loop ;-- unlocking filesfile_close ( source ) ;file_close ( target ) ;wait ;end process ; aba.bin ima.bincopy aba.bin + aba.bin ima.binima.binDOS equivalent:duplicatecontents ofaba.binCH 1214/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 71New:VHDL-2008 revisionSECTION 314/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 72Introduction
  19. 19. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 73VHDL-2008 is here (alive and kicking..)The Original VHDL-1987 standard was very powerful !Previous updated revisions were minor– VHDL-1993 (files, direct instantiation, extended naming of identifiers,some minor coding style change, shared variables .. )– VHDL-2002 (protected shared variables, improved buffer mode,bigger real .. )Because the basic version was very powerful and modifications were veryminor, many tool vendors ignored modifications or upgraded their toolsvery slowly (why bother ..)Many people consider only Verilog 2001 to be a matching competitor toVHDL (this tie situation continues from 2001 until 2005)SystemVerilog (2005) is a superset of Verilog that improves itsverification capabilities. Some are beyond VHDLs verification capabilities.VHDL-2008 is a Major Revision with many improvementVendors are adding support quickly !CH 01A Short HistoryLesson14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 74Improvements in VHDL-2008 are in areas:Making VHDL language stronger(many more features.. )Making VHDL language easier to use(less cumbersome.. )Enhancements in the area of Verification(adding powerful features to existingcapabilities + More coming soon.. )CH 0114/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 75The final goal (‫בתנור‬ ‫מתבשל‬ ‫)מה‬Why update VHDL ? Instead, why not adopt SystemVerilog as verificationLanguage ?VHDL already includes many system-level modeling features such as: records,access types (pointers), Protected types & shared variables, PSL and many manyother advanced features that can be enhanced with relatively little effort, and newfeatures can be added in a way that integrates cleanly with existing features.Organizations using VHDL already have significant experience using thelanguage and a pool of people familiar with the language.Using SystemVerilog wold force users to learn a language that is different or haveto manage multilingual environments (causing lower productivity)Final Goal: VHDL = Verification & Hardware Description LanguageThe next enhancements are mostly Verification focused:– Object Oriented Classes– Verification Data structures– More powerful Randomization (enhancing existing capabilities)– Functional Coverage– & Incorporating good things from SystemVerilog, SystemC, Vera & ECH 01 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 76‫מטרה‬‫כיוונים‬ ‫על‬ ‫ההצבעה‬(‫התוספות‬ ‫כל‬ ‫על‬ ‫לעבור‬ ‫ומבלי‬ ‫בחומר‬ ‫להעמיק‬ ‫)מבלי‬Presentation goals
  20. 20. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 77We will not go into all the modifications..For More information ( or use the new LRM :-( )14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 78VHDL-2008 not supported in first edition... ‫שאזלה‬ ‫ראשונה‬ ‫מהדורה‬VHDL-2008 ‫ב‬ ‫תומכת‬ ‫לא‬14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 79Topics can also be found in 2nd edition14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 80Topics that will be Mentioned hereMore reserved wordsMore convenient CommentsMore powerful & convenient constant string assignmentsMore convenient mixed bit & vector Logical operationsUnary reduction operationsMore built in arraysnumeric_std_unsigned from IEEE replaces std_logic_unsigned fromSynopsysBetter relationsNew maximum(_), & minimum(_) functionsNew Fixed point and float vectorsThe Context design unitThe condition operatorMore convenient Case operationsconditional assignments & selected assignments in processSimulation/Verification
  21. 21. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 81Topics that will be Mentioned hereMore convenient combinatorial descriptionsMore convenient sync descriptionsNew to_string(_) functionsexpressions written to ports when instantiation of componentsRevision of Modes (port directions)More convenient & powerful generate statementsForcing signals through hierarchies using external namesForcing signals through hierarchies using external namesForcing ports: Driving value & Effective valueEmbedded PSLIP (Intellectual Property) protectionVHDL Procedural Interface (VHPI)Simulation/VerificationdirectedSimulation/VerificationdirectedSimulation/VerificationonlySimulation/Verificationonly14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 82More reservedwordsCH 0214/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 83More reserved names VHDL-93/2002/2008group impure inertial literal posponedpure reject rol ror sharedsla sll sra srl unaffectedxnorprotectedassume assume_guarantee context coverdefault fairness force parameterproperty release restrict restrict_guaranteesequence strong vmode vpropvunitVHDL-93VHDL-2002VHDL-2008PSL wordsCH 02 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 84More convenientCommentsCH 02
  22. 22. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 85Comments-- this comment ends with <CR> <LF>y <= a and b and c ; -- right part of this line is a comment-- this-- is-- a-- long-- comment/* this is a delimitercomment in VHDL-2008 */CH 02 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 86More powerful &convenient constantstring assignmentsCH 0214/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 87Old & New bit-string literalsy <= b"11110110" ; -- binaryy <= x"F6" ; -- hexy <= "1111" & "011" & 0 ; -- default vector is biny <= x"f" & o"3" & 0 ; -- octal & lowercase tooy <= 246 ; -- errory <= d"246" ; -- ERROR d is not a legal prefixy <= d"246" ; -- OK in VHDL-2008 !ok on olderversionsCH 02 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 88Specifying width in new bit-string literalsPadding with leading zeros on the left13d"246" => "0000011110110"13o"366" => "0_000_011_110_110"13x"f6" => "0_0000_1111_0110"10o"0366" => "0_011_110_110"10x"0f6" => "00_1111_0110”Signed values (Unsigned is the default)12ux"f6" => "0000_1111_0110" (unsigned extension)12x"f6" => "0000_1111_0110" (unsigned extension)12sx"f6" => "1111_1111_0110" (signed extension)assigning std_logic_vector with meta-characters12o"01X" => "000_111_XXX"CH 02
  23. 23. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 89More convenientmixed bit & vectorLogical operationsCH 02 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 90Mixed vector & bit operations-- a polarity changer ?entity op_bv1 isport ( x : out bit_vector(7 downto 0) ;a : in bit_vector(7 downto 0) ;b : in bit ) ;end op_bv1 ;architecture arc_op_bv1 of op_bv1 isbeginx <= a xor b ;end arc_op_bv1 ;x7x6x5x4x3x2x1x0a7a6a5a4a3a2a1a0bNot legal on older VersionsOK onVHDL-2008CH 0214/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 91Solution on older versions-- a polarity changerentity op_bv1 isport ( x : out bit_vector(7 downto 0) ;a : in bit_vector(7 downto 0) ;b : in bit ) ;end op_bv1 ;architecture arc_op_bv1 of op_bv1 issignal b_bv : bit_vector ( 7 downto 0 ) ;beginb_bv <= ( others => b ) ;x <= a xor b_bv ;end arc_op_bv1 ;x7x6x5x4x3x2x1x0a7a6a5a4a3a2a1a0bCH 02Annoying14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 92Unary reductionoperationsCH 02
  24. 24. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 93What had to be done in older versions-- no reduced operations on old VHDLentity reduced_vec isport ( din : in bit_vector(7 downto 0) ;parity : out bit ) ;end reduced_vec ;architecture arc_reduced_vec of reduced_vec isbeginparity <= din(7) xor din(6)xor din(5) xor din(4)xor din(3) xor din(2)xor din(1) xor din(0);end arc_reduced_vec ;CH 02 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 94Unary reduction operations in VHDL-2008-- reduced operations on a vector (VHDL-2008)entity reduced_vec isport ( din : in bit_vector(7 downto 0) ;parity : out bit ) ;end reduced_vec ;architecture arc_reduced_vec of reduced_vec isbeginparity <= xor din ;end arc_reduced_vec ;CH 0214/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 95More built in arraysCH 02 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 96boolean, integer, real & time arrays-- decoder 3->8 using numeric relationsentity dec3t8 isport ( din : in integer range 0 to 7 ;enable : in boolean ;d : out boolean_vector(7 downto 0) ) ;end dec3t8 ;architecture arc_dec3t8 of dec3t8 isbegin-- positional associationd <= ( ( din=7 ) and enable ,( din=6 ) and enable ,( din=5 ) and enable ,( din=4 ) and enable ,( din=3 ) and enable ,( din=2 ) and enable ,( din=1 ) and enable ,( din=0 ) and enable ) ;end arc_dec3t8 ;in old VHDL only bit_vector(or std_logic_vector) andstringsboolean_vector,integer_vector, real_vector,time_vectorCH 02
  25. 25. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 97boolean, integer, real & time arrays-- decoder 3->8 using numeric relationsentity dec3t8 isport ( din : in integer range 0 to 7 ;enable : in boolean ;d : out boolean_vector(7 downto 0) ) ;end dec3t8 ;architecture arc_dec3t8 of dec3t8 isbegin-- named associationd <= ( 7 => ( din=7 ) and enable ,6 => ( din=6 ) and enable ,5 => ( din=5 ) and enable ,4 => ( din=4 ) and enable ,3 => ( din=3 ) and enable ,2 => ( din=2 ) and enable ,1 => ( din=1 ) and enable ,0 => ( din=0 ) and enable ) ;end arc_dec3t8 ;in old VHDL only bit_vector(or std_logic_vector) andstringsboolean_vector,integer_vector, real_vector,time_vectorCH 02 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 98std_logic_unsigned fromSynopsys is replaced bynumeric_std_unsigned fromIEEECH 0214/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 99New: numeric_std_unsignedThe most popular 3 declarations (math operations on vectors)-- Using the classic package of Synopsys in old VHDLlibrary ieee ;use ieee.std_logic_1164.all ;use ieee.std_logic_unsigned.all ;Replaced by:-- Same thing with new package of IEEE in VHDL-2008library ieee ;use ieee.std_logic_1164.all ;use ieee.numeric_std_unsigned.all ; -- a new package !More operations (divisions,power)CH 02 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 100Better relationsCH 02
  26. 26. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 101Problems with old = relations’1‘’H‘false’X‘’Z‘false’U‘’U‘trueReturn BooleanNot behaving like real hardwareCH 02 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 102New (matched) ?= relationAny compare to ‘-’(don’t care) is ‘1’Any compare to‘U’ is ‘U’Strong ‘0’ & ‘1’equal weak ‘L’ & ‘H’‘W’ ‘X’ & ‘Z’ issame as ‘X’Behaving like real hardwareVectors are and-ed together, with any ‘X’ producing ‘X’ result and any ‘0’ producing ‘0’ resultCH 0214/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 103Problems with old relations - (<)Return BooleanU < X < 0 < 1 < Z < W < L < H < -No Meaningful hardware behaviorCH 02order is according toenumerated declaration14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 104New (matched) ?< relationAny compare to ‘-’(don’t care) is errorAny compare to‘U’ is ‘U’Strong ‘0’ & ‘1’equal weak ‘L’ & ‘H’‘W’ ‘X’ & ‘Z’ issame as ‘X’Behaving like real hardwareCH 02
  27. 27. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 105Other Matched relationsAre all created by operations on the previous relations?/= is an inverted ?=?>= is inverted ?<?<= is ?< or-ed with ?=Example of usage:library ieee ;use ieee.std_logic_1164.all ;use ieee.numeric_std_unsigned.all ; -- present for math meaningentity good_compare2 isport ( a : in std_logic_vector(3 downto 0) ;b : in std_logic_vector(2 downto 0) ;a_gte_b : out std_logic ) ;end good_compare2 ;architecture arc_good_compare2 of good_compare2 isbegina_gte_b <= ( a ?>= b ) ; -- matching directional compareend arc_good_compare2 ;CH 02 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 106New maximum(_), &minimum(_) functionsCH 0214/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 107minimum(_) & maximum(_) functionsCan be used with the following data types: character, bit, integer, real,time, string, boolean_vector, bit_vector, integer_vector, real_vector,time_vector, std_logic_vector and many more types .. (any data typesthat relations can be operated on)Usage:maximum( object1 , object2 ) -- max between 2maximum ( array_type ) -- returns max array elementExample of usage:constant w1 : integer := 3 ;constant w2 : integer := 2 ;signal y : std_logic_vector(maximum(w1,w2) downto 0) ;CH 02 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 108New Fixed point andFloating point vectorsCH 02
  28. 28. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 109More Powerful vector data typesThe new Powerful data types– Unsigned fixed - ufixed– Signed fixed - sfixed– Floating Point - floatThey are all vectoric data types !Useful for:– Large dynamic range (including fractions)– Complex Arithmetic and DSP applicationsfixed types consume less hardware resources but have lower dynamicrange, float has more dynamic range but hardware is more complexSupport for synthesis already exist structurally: full support very soon– For example, Altera has already the flowing floating point macrofunctions:ALTFP_ABS, ALTFP_ADD_SUB, ALTFP_COMPARE, ALTFP_CONVERT,ALTFP_DIV, ALTFP_EXP, ALTFP_INV, ALTFP_INV_SQRT, ALTFP_LOG,ALTFP_MULT, ALTFP_SQRT, and more coming soon... & fixed = integersCH 02 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 110ufixed & sfixed declarations & assignmentsCode example of an adderlibrary ieee ;use ieee.fixed_pkg.all ;entity fixed_vec isport ( a,b : in ufixed(3 downto -4) ; -- width 8y : out ufixed(4 downto -4) ) ; -- width 9end fixed_vec ;architecture arc_fixed_vec of fixed_vec isbeginy <= a + b ; -- both sides are width 9end arc_fixed_vec ;Operands are 8 bit wide & Result is 9 bits (Full Precision math with noautomatic modulo-truncation)1 1 1 1 . 0 0 0 01 1 1 1 . 0 0 0 01 1 1 1 0 . 0 0 0 0c c c cExampleCH 0214/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 111with old vector (integer) mathHandling the truncated bit-- Handling truncation bitlibrary ieee ;use ieee.std_logic_1164.all ;use ieee.std_logic_unsigned.all ;entity vec3_math isport ( a,b : in std_logic_vector(3 downto 0) ;y : out std_logic_vector(4 downto 0) ) ;end vec3_math ;architecture arc_vec3_math of vec3_math isbeginy <= (0 & a) + (0 & b) ;end arc_vec3_math ;CH 02Annoying14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 112Beyond fixed - floatFloat Fixed– more (dynamic range + hardware) less (dynamic range + hardware)– constant relative accuracy constant absolute accuracyand What’s wrong with existing real ?– Fixed range of 64 bit not suitable for all applications– No easy and direct access to bits of numberPackage float_pkg enables usage of– Standard 32 bit & 64 bit numbers (IEEE-754)– Standard 128 bit numbers– Any width (compliant with IEEE-854)3 Parts (mandatory)sign.exponent.fractionExamples in next foils..CH 02
  29. 29. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 113Example of floating point divider-- example of a floating point dividerlibrary ieee ;use ieee.float_pkg.all ;entity fdiv isport ( a,b : in float32 ;y : out float32 ) ;end fdiv ;architecture arc_fdiv of fdiv isbeginy <= a / b ;end arc_fdiv ;CH 02Standard vs Non Standardfloating points declarationsstandard 64 & 128 bitsignal a,b : float64 ;signal a,b : float128 ;-- non standard 16 bitsignal a,b : float(5 downto -10) ;-- non standard 7 bits (minimum)signal a,b : float(3 downto -3) ;Synthesis supported toobut still not optimal withwww.vhdl.org/fphdl14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 114The Contextdesign unitCH 0214/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 115The context design unitMakes including a group of libraries and packages easier using a singlename referenceExample of declaration (and then declaration to library proj_lib):context easy islibrary ieee ;use ieee.std_logic_1164.all ;use ieee.std_logic_unsigned.all ;library proj_lib ;use proj_lib.proj_pack.all ;use std.textio.all ;use ieee.std_logic_textio.all ;end context ;Example of usage:library proj_lib ;context proj_lib.easy ;entity . . . is. . .CH 02 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 116The conditionoperatorCH 03
  30. 30. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 117The ?? condition Operator-- Introducing the condition operator "??"library ieee ;use ieee.std_logic_1164.all ;entity condition isport ( din : in std_logic ;dout : out boolean ) ;end condition ;architecture arc_condition of condition isbegindout <= ?? din ; -- convert std_logic to booleanend arc_condition ;‘1’ or ‘H’ is converted to trueother values (’0’,’L’,’X’,’Z’,’U’,’W’’-’) are converted to falseCH 03 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 118Old style (not convenient)entity condition1 isport( cs0,cs1,pol : in bit ;din : in bit_vector(3 downto 0) ;dout : out bit_vector(3 downto 0) ) ;end condition1 ;architecture arc_condition1 of condition1 isbeginprocess (din,cs0,cs1,pol)beginif cs1 = 1 and cs0 = 0 and pol = 1 thendout <= din ;elsif cs1 = 1 and cs0 = 0 and pol = 0 thendout <= not din ;elsedout <= ( others => 0 ) ;end if ;end process ;end arc_condition1 ;CH 03boolean14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 119Old style (using the ?? operator)-- using the ?? operatorarchitecture arc_condition2 of condition2 isbeginprocess (din,cs0,cs1,pol)beginif ?? ( cs1 and not cs0 and pol ) thendout <= din ;elsif ?? ( cs1 and not cs0 and not pol ) thendout <= not din ;elsedout <= ( others => 0 ) ;end if ;end process ;end arc_condition2 ;CH 03Not boolean14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 120Old style (?? implicitly implied)-- the ?? operator implicitly impliedarchitecture arc_condition3 of condition3 isbeginprocess (din,cs0,cs1,pol)beginif cs1 and not cs0 and pol thendout <= din ;elsif cs1 and not cs0 and not pol thendout <= not din ;elsedout <= ( others => 0 ) ;end if ;end process ;end arc_condition3 ;CH 03OK too
  31. 31. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 121Where can this implicitly implied ?? be usedAfter an if clause (as in previous example) in an if statementAfter an elsif clause in an if statementAfter an until clause in a wait statementAfter an assert statementAfter a while clause in a while loop statementAfter a when clause in a next statementAfter a when clause in an exit statementAfter an if clause (as in previous example) in an if generate statementAfter an elsif clause in an if generate statementIn a boolean expression in a PSL declarationIn a boolean expression in a PSL statementCH 03 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 122More convenientCase operationsCH 0314/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 123Priority encoder example (‫)תזכורת‬din(3) din(2) din(1) din(0)4 to 2Priority EncoderhighprioritylowpriorityDirect inputsEncoded outputsdout(1) dout(0)gsGroup selectCH 03 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 124The old case statementcase to_x01(din) iswhen "1000" | "1001" | "1010" | "1011"| "1100" | "1101" | "1110" | "1111" =>dout <= "11" ; gs <= 1 ;when "0100" | "0101" | "0110" | "0111" =>dout <= "10" ; gs <= 1 ;when "0010" | "0011" =>dout <= "01" ; gs <= 1 ;when "0001" =>dout <= "00" ; gs <= 1 ;when "0000" =>dout <= "00" ; gs <= 0 ;when others =>dout <= "XX" ; gs <= X ; report "unknown din" ;end case ;CH 03
  32. 32. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 125An new elegant matching case? statementcase? din is -- using the ?= (built in matching) operatorwhen "1---" =>dout <= "11" ; gs <= 1 ;when "01--" =>dout <= "10" ; gs <= 1 ;when "001-" =>dout <= "01" ; gs <= 1 ;when "0001" =>dout <= "00" ; gs <= 1 ;when "0000" =>dout <= "00" ; gs <= 0 ;when others =>dout <= "XX" ; gs <= X ; report "unknown din" ;end case ;- in code istreated as ΦH is treated as 1L is treated as 0no need for to_xo1()CH 03 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 126conditionalassignments &selectedassignmentsin processCH 0314/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 127Complex assignments in process (2 of 2)process (din,sel,ena)beginif sel = "00" then-- conditional assignment in processdout <= din(0) when ena = 1 else 0 ;elsif sel = "01" then-- conditional assignment in processdout <= din(1) when ena = 1 else 0 ;elsif sel = "10" then-- selected assignment in processwith ena selectdout <= din(2) when 0 ,0 when others ;else -- sel="11"-- selected assignment in processwith ena selectdout <= din(1) when 0 ,0 when others ;end if ;end process ;end arc_mixedmux ;CH 03 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 128More convenientcombinatorialdescriptionsCH 04
  33. 33. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 129Complete sensitivity list in comb system-- complete sensitivity list for VHDL-2008architecture arc_comrule2 of comrule2 isbeginprocess ( all ) -- very elegant solution !beginy <= a or b or c ;end process ;end arc_comrule2 ;-- good for latches too !CH 04 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 130More convenientsync descriptionsCH 0514/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 131using rising_edge(_) with bit too, no dilemma-- using the rising_edge(_) function with bit tooentity dff7 isport ( clk : in bit ;d : in bit ;q : out bit ) ;end dff7 ;architecture arc_dff7 of dff7 isbeginprocess ( clk )beginif rising_edge(clk)then -- no more dilemma !q <= d ;end if ;end process ;end arc_dff7 ;CH 05 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 132New to_string(_)functionsCH 06
  34. 34. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 133The to_string(_) functionHere is an exampleprocess ( din ) -- din is std_logic_vector(11 downto 0)beginassert falsereport " [time=" & to_string(now) & "]" &" [din=" & to_string(din) & "]"severity note ;end process ;resultsNote: [time=100 ns] [din=101011001111]Note: [time=200 ns] [din=00001111HLXZ]All other old built in data types are supported tooData types ufixed, sfixed and float are supported tooCH 06useful inverification14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 134to_string(_) function with more parametersShown: units to use with timeShown: width of the right side of decimal point with realprocess ( din ) -- din is now realbeginassert falsereport " [time=" & to_string(now,ps) & "]" &" [din=" & to_string(din,10) & "]"severity note ;end process ;resultsNote: [time=100000 ps] [din=1.0000000000]Note: [time=200000 ps] [din=6.5000000000]With type real you can also use other format strings like in printf of C:E%, e%, f%, g%CH 0614/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 135to_hstyring(_) & to_hstyring(_) functionsSpecial functions to be used on vector types:to_hstring( vector_type )to_ostring( vector_type )Example with binary hex & octal presentation shown:process ( din ) -- din is std_logic_vector(11 downto 0)beginassert falsereport " [bin=" & to_string(din) & "]" &" [hex=" & to_hstring(din) & "]" &" [oct=" & to_ostring(din) & "]"severity note ;end process ;results on “101011001111” and “00001111HLXZ”Note: [bin=101011001111] [hex=ACF] [oct=5317]Note: [bin=00001111HLXZ] [hex=0FX] [oct=03XX]CH 06 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 136expressions writtento ports wheninstantiation ofcomponentsCH 07
  35. 35. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 137wiring of signals constants & expressionsin VHDL-87 only clean signals are possibleu1: or_gate port map ( s , q , x1 ) ;In VHDL-93 wiring of constants is possible toou1: and_gate8port map(output => y ,input(3 downto 0) => x(3 downto 0) ,input(7 downto 4) => 1&1&1&1’ ) ;in VHDL-2008 expressions are possible toou1: or_gate port map ( not s , q , x1 ) ;CH 07 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 138Revision of Modes(port directions)CH 0714/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 139New - Modes (port directions)in– The default mode– In signal can not be written (LHS) internally– In signal can only be read (RHS) internallyout– Out signal can be externally bussed– Out signal can be read back (RHS) internally !– Out signal can be written (LHS) internallyinout– inout signal can be externally bussed– inout signal can be read back (RHS) internally– No internal restrictions (read write)Will be used as normal output (not I/O) BUSWill be used as I/O BUS (synthesis tools prefer this mode) People will probably stop using bufferCH 07Usuallyused forI/Onew14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 140Old coding stylelibrary ieee ;use ieee.std_logic_1164.all ;use ieee.std_logic_unsigned.all ;entity count16 isport ( clk : in std_logic ;count : out std_logic_vector(3 downto 0) ) ;end count16 ;architecture arc_count16 of count16 issignal cnt : std_logic_vector(3 downto 0) ;beginprocess (clk)beginif rising_edge(clk) thencnt <= cnt + 1 ;end if ;end process ;count <= cnt ;end arc_count16 ;CH 07
  36. 36. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 141New coding stylelibrary ieee ;use ieee.std_logic_1164.all ;use ieee.std_logic_unsigned.all ;entity count16 isport ( clk : in std_logic ;count : out std_logic_vector(3 downto 0) ) ;end count16 ;architecture arc_count16 of count16 is-- signal cnt : std_logic_vector(3 downto 0) ;beginprocess (clk)beginif rising_edge(clk) thencount <= count + 1 ; -- now you can read mode outend if ;end process ;-- count <= cnt ;end arc_count16 ;CH 07 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 142More convenient &powerful generatestatementsCH 0814/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 143-- same thing in new stylelabel: if condition generate-- first alternative...else generate-- second alternative...end generate ;More powerful if-generate statements-- old coding stylelabel1: if conditiongenerate-- first alternative...end generate ;label2: if not conditiongenerate-- second alternative...end generate ;CH 08No elseclause14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 144Full If-generate & case-generate syntax-- syntax similar to-- regular if clauselabel: if condition1generate-- first alternative...elsif condition2 generate-- second alternative......else generate-- last defaultalternative...end generate ;-- syntax similar to-- regular case clauseslabel: casetested_expressiongeneratewhen choice1 =>-- first alternative...when choice2 =>-- second alternative...when others =>-- last defaultalternative...end generate ;CH 08
  37. 37. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 145Monitoring (Accessing)signals through hierarchiesusing external namesCH 08Probing14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 146Accessing external namesAccess data objects (signals,constants & shared variables) directly andnot through portsFull syntax:<< object_class_type pathname : subtype_indicator >>object_class_type can be: signal, constant or shared variable. pathnamecan be: absolute, relative or start from package. subtype_indicators roleis the same as its role in alias declarations (can also be unconstrained)Example #1 (Absolute path)ext_sig <= <<signal .tb.top_u.bot_u.int_sig : bit>> ;Example #2 (relative path - used in an assert statement):assert << signal u_top.u_mid.u_bottom.count :std_logic_vector(3 downto 0) >> /= "1111"report "count is not legal" ;CH 08useful inverification14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 147Accessing external names (using alias)Special path characters are: ^ - go up from current hierarchy ,@ - start absolute hierarchy from packageExample #3 (pakage with hierarchy & start from package)alias data_width is << constant @work.cpu_pack.alu_pack.width : natural >> ;signal data_bus : std_logic_vector( data_width -1 downto 0) ;Example #4 using the alias command to make a compact namealias count is <<signal .eut.u_top.cnt : std_logic_vector>> ;assert count(3 downto 0) = "1001"report "got: "& to_string(count) & "/= 1001 expected" ;Results of Example #4 (when count is not 1001)Error: got: 0000 /= 1001 expectedCH 08 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 148Forcing signalsthroughhierarchies usingexternal namesCH 08
  38. 38. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 149Force & Release assignmentsOverride all normal resolved values assigned to a signal (similar to scriptforce command)– Initialize signals quickly bypassing complex initialization sequences– Inject erroneous values into design to ensure that detection & response areappropriateA powerful verification feature !Force Syntax:signal_name <= force expression ;signal_name can be a regular signal name but also can also be (and usuallyis) an external name or aliasRelease syntax:signal_name <= release ;Stop forcing & design takes back controlCH 08very useful inverification14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 150Force & Release assignment exampleprocessuse work.control_pkg.all ;alias clk is << signal eut.clk : std_logic >> ;alias present_state is<< signal eut.sm.present_state :std_logic_vector(3 downto 0) >>;begin. . .-- force a bad (corrupt) state to state machinewait until falling_edge(clk) ;current_state <= force "1111" ; -- bad (corrupt) statewait until falling_edge(clk) ;current_state <= release ;-- monitor recovery activity .... . .end process ;CH 08very useful inverification14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 151Forcing ports:Driving value &Effective valueCH 08 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 152Force & Release assignments of portsDriving value– The value presented externally by the entity– Determined by internal sources within the entityEffective value– The value seen internally by an entity– Determined by whatever is externally connected to portDriving value 0Effective value XDriving value 1VHDL-2008 allows us to forcethe driving and effective valuesof a port independently !CH 08
  39. 39. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 153Force & Release assignments of portsVHDL-2008 allows us to force the driving and effective values of a portindependently !Forcing driving value (can be done to any port of mode out or inout orbuffer but can not be done to port of mode in)bus_io <= force out "ZZZZZZZZ" ;Forcing effective value (can be done to port of any mode)bus_io <= force in "XXXXXXXX" ;Releasing previous portsbus_io <= release out ;bus_io <= release in ;Default forcing assignment of port signals of mode in is force in (forcingeffective value)Default forcing assignment of port signals of mode inout,out,buffer is forceout (forcing driving value)Driving value "ZZZZZZZZ"Effective value "XXXXXXX"bus_ioCH 08 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 154Embedded PSL14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 155General Information on PSLPSL = Property Specification LanguageOrigin: Sugar (IBM) => IEEE std 1850Allows specification of temporal properties of a model– Enables Static Verification (using formal proof tools)– Enables Dynamic Verification (using simulation checkers)For full information refer to:– "Practical Introduction to PSL",Cindy Eisner & Dana Fisman– "Using PSL/Sugar for Formaland Dynamic Verification",multiple authors14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 156Moreadvancedfeatures
  40. 40. 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 157More advanced topicsIP (Intellectual Property) protection– Pragma based approach– Allows IP authors to mark specific areas of VHDL code for encryption– using standard cipher algorithms (symmetric & asymmetric ciphers such as:DES,AES,blowfish,twofish,serpent, cast,RSA,elgama, and others)– using standard encoding methods (such as: uudecode, base64 & others)– Using standard hash functions (sha1,md5,md2,ripemod-160)– Support is embedded in standard simulation & Synthesis toolsVHDL Procedural Interface (VHPI)– application-programming interface (API) to VHDL tools– Tools can gain access about VHDL model during analysis, elaboration orexecution of model– Can help development of add-in tools such as: Linters, Code coverageanalyzer tools, Timing and Power analyzers– Can help usage of external simulation models14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 158Open Source VHDL Verification Methodology14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 159How to get more capabilities ?Learn more existing capabilities of VHDL (there are Lot’s of books)Learn the New capabilities of the New VHDL-2008 (some books availableand LRM-standard is accessible through the Technion web)There are many helpful packages & Libraries that can help you improveyour capabilities (Synthesis, Simulation-Verification, randomization...)Learn PSL and use it through VHDLUse the float and complex package (randomization, sin(_), cos(_) ..)Read about the many IP (Intellectual Property) Cores available and usethemVHDL can be used with many tools (Synthesis, Simulation, Codecoverage, Lint tools and may more..)Many VHDL tools can and also work with other languages such as(SystemVerilog, E,Vera, System C - and others... )Learn to use microprocessors embedded to FPGAsCH 03 14/04/2013 VHDL - Amos Zaslavsky © Copyright Page: 160Coffee Break

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