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Altera’s Role In Accelerating the Internet of Things
Altera’s Role In Accelerating the Internet of Things
Altera’s Role In Accelerating the Internet of Things
Altera’s Role In Accelerating the Internet of Things
Altera’s Role In Accelerating the Internet of Things
Altera’s Role In Accelerating the Internet of Things
Altera’s Role In Accelerating the Internet of Things
Altera’s Role In Accelerating the Internet of Things
Altera’s Role In Accelerating the Internet of Things
Altera’s Role In Accelerating the Internet of Things
Altera’s Role In Accelerating the Internet of Things
Altera’s Role In Accelerating the Internet of Things
Altera’s Role In Accelerating the Internet of Things
Altera’s Role In Accelerating the Internet of Things
Altera’s Role In Accelerating the Internet of Things
Altera’s Role In Accelerating the Internet of Things
Altera’s Role In Accelerating the Internet of Things
Altera’s Role In Accelerating the Internet of Things
Altera’s Role In Accelerating the Internet of Things
Altera’s Role In Accelerating the Internet of Things
Altera’s Role In Accelerating the Internet of Things
Altera’s Role In Accelerating the Internet of Things
Altera’s Role In Accelerating the Internet of Things
Altera’s Role In Accelerating the Internet of Things
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Altera’s Role In Accelerating the Internet of Things

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  • Key column is the far right in each benchmark (performance metric per watt)- 10X to 30X better than MPU/GPY solutions- OpenCL makes these gains a possibility for sw engineers who don’t know how to code in HDL
  • Key column is the far right in each benchmark (performance metric per watt)- 10X to 30X better than MPU/GPY solutions- OpenCL makes these gains a possibility for sw engineers who don’t know how to code in HDL
  • historically, the huge population of sw programmers don’t access the performance per watt advantages of FPGAs b/c they only know how to program in C-code. Some of these programmers have made the leap to nVidia GPU’s because nVidia provided “CUDA”, which is a C-code capability for use on their GPUs. Meanwhile, HW engineers (probably outnumbered by SW engineers by about 10 sw to 1 hw) live in a hardware description language (HDL) world and they are the ones using FPGAs and getting great results (performance/power).- OpenCL is the key that unlocks the door for SW programmers, who need greater performance/watt, to gain access to the benefits of FPGA devices. This will allow Altera to access growth at the expense of MCU/MPU in a variety of applications both as a CPU offload (i.e., in conjunction with a processor) or fully displacing a CPU/MCU (SoC FPGA).Transition to next slide (may not be applicable due to changes in order of slides): Let’s look at Altera SoC FPGA and see why we are seeing some significant design win traction<click>
  • Transcript

    • 1. Altera’s Role In Accelerating the Internet of Things Chris Balough Senior Director, SoC Products
    • 2. Key Points 2 FPGAs are used throughout the communications infrastructure for flexibility, adaptability and faster time-to-market Altera’s new SoC devices combine FPGA and ARM, making the network more IoT-ready: intelligently flexible and adaptable Explosive growth of IoT devices driving substantial new requirements for the communications and datacenter infrastructure Altera’s newest FPGAs and SoCs will help enable infrastructure advancements to be IoT-ready FPGAs are widening the technology gap vs. ASICs and ASSPs
    • 3. Altera Overview 3  Headquartered in Silicon Valley, California; founded in 1983  Industry’s first reprogrammable logic semiconductors  $1.73 billion in 2013 sales  3,000 employees in more than 20 countries  Leading supplier of FPGAs, CPLDs and SoCs
    • 4. Advanced Chip Development: Difficult ROI 4 65nm 40nm 28nm 20nm $35 $52 $88 $156$175 $260 $440 $780 Revenue Requirement ($M) (to maintain R&D costs at 20% of Revenue)  Stay on lagging node  less competitive for design wins  Move to advanced node  higher ROI hurdle“A Difficult Choice” Total Development Costs ($M)   Development Cost Source: IBS FPGAAdvantage: Aggregating Demand From Many Markets Allows Ongoing Investment in New Process Nodes
    • 5. 5 FPGAs: Growing Gap vs. ASIC/ASSP 180 nm 130 nm 90 nm 45 nm 180 nm 130 nm 90 nm 65 nm 45 nm 28 nm 20 nm Primary FPGA Process Node Primary ASIC Process Node Source: Altera; data applies to new design starts. 40 nm 40 nm 32 nm 32 nm 28 nm 22 nm 65 nm 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 TECHNOLOGY GAP
    • 6. Generation 10 – A Complete Portfolio of SoCs and FPGAs 6 Intel 14 nm Tri-gateTSMC 20 nm High EndMid RangeHigh Volume To be announced.
    • 7. SoC Roadmap: Getting “Smarter” with ARM Cores 7 Features&Performance 1st Generation 28 nm TSMC 1.05 GHz Dual ARM Cortex™-A9 MPCore™ 2nd Generation 20 nm TSMC 3rd Generation 14 nm Intel Tri-Gate Quad ARM Cortex™-A53 ARMv8 Processor 1.5 GHz Dual ARM Cortex™-A9 MPCore™ More Coming
    • 8. Stratix 10 SoC: Altera’s Most Advanced Product Ever 8 QUAD 64-BIT PROCESSOR ADVANCED TOOLS 1GHZ FPGA LOGIC 10 TFLOPS DSP + + + + ALTERA® SDK FOR OPENCL™
    • 9. Altera In Communications: Infrastructure Enablement Altera #1 FPGA In OTN; Data Center; Wireless Backhaul, Baseband, Radio 9 = FPGA Application
    • 10. Wireless Example: Escape Microwave Modem  Single-chip modem  Altera Cyclone V FPGA: flexibility, adaptability, fast time-to-market 10
    • 11. Wireline Example: 100G Multi-Service Platform Card  Leading communications equipment vendor using Altera FPGA to deliver highly integrated Multi-Service Platform  FPGA allows flexibility, adaptability, and time-to-market 11 PCB Broadcom BCM88650 Switching Solution Altera Stratix V FPGA  DMA engines  Search Engine  Acceleration  Load balance  Policies, Stats Micron RLDRAM3 Search Engine Interlaken Intel PCIe x8 Intel PCIe x8 Intel PCIe x8 Intel PCIe x8 Micron RLDRAM3 Search Engine
    • 12. Communications Infrastructure Before IoT 12 Client Devices Data Centers Comms Infrastructure
    • 13. Impact of IoT: Large Number of New Devices 13 Client Devices Data Centers Comms Infrastructure
    • 14. Impact of IoT: Infrastructure Capacity Must Expand 14 Client Devices Comms Infrastructure Data Centers
    • 15. Altera SoCs, FPGAs Accelerating the Internet of Things 15 SoC and FPGA-Enabled Network Infrastructure SoC and FPGA-Enabled Accelerated Computing SoC and FPGA-Enabled IoT Gateways +
    • 16. 16 Spotlight: FPGAs in the DataCenter
    • 17. IBM Netezza 1000 Data Warehouse Appliance 17 Source: IBM Netezza 1000 Datasheet and “Teradata and IBM PureData System for Analytics Compared” White Paper from IBM.com “IBM Netezza 1000 uses Field Programmable Gate Arrays (or FPGAs) which have been programmed specifically to handle large volumes of data very efficiently. These FPGAs … removes I/O bottlenecks … creating a significant turbocharger effect on system performance.” “The visibility engine maintains … compliance at streaming speeds. All this work, … is achieved in an energy efficient FPGA measuring just one square inch. “
    • 18. FPGAs can greatly enhance CPU-based data center processing by accelerating algorithms and minimizing bottlenecks FPGAs Increase Efficiency in the Data Center  Massively parallel architecture Has 10X-100X the number of computational units Enables pipelined designs that perform multiple / different instructions in a single clock cycle Better localized memory avoids bottlenecks  Programmability that enables application-specific accelerators 18 10X+ increase in performance per watt ~1M Logic Elements 2,660 20-kbit Memory Blocks ~2000 DSP Blocks 840 Programmable I/O Blocks Stratix V Architecture Diversity of applications make ASSPs and ASICs impractical
    • 19. Performance Per Watt Benchmarks 19 Platform Power (W) Performance (MT/sec) Performance / Power (MT/sec/W) Intel Xeon (w3690) 130 2070 15.92 nVidia Tesla (C2075) 215 3240 15.07 Altera FPGA Accelerator 25 3602 144.08 Search – Unstructured Data Analytics (Document Filtering / Bloom Filter) Source: Altera benchmarks; MT/sec = Million terms per second ~10X or more improvement in performance per watt
    • 20. Performance Per Watt Benchmarks 20 Platform Power (W) Performance (MSIM/sec) Performance / Power (MSIM/sec/W) Intel Xeon (w3690) 130 32 0.25 nVidia Tesla (C2075) 215 63 0.29 Altera FPGA Accelerator 25 170 7.40 Financial Modeling – (Option pricing, Monte Carlo Simulation/Heston model) Source: Altera benchmarks; MSIM/sec = Million simulations per second ~10X or more improvement in performance per watt
    • 21. OpenCL Making FPGAs “Programmer-friendly”  Open, royalty-free standard for parallel programming  Altera is first and only FPGA supplier with proven OpenCL capability  Development and evaluation at… 4 of the top 6 largest server suppliers 3 of the top 5 largest investment banks 21 HDL code HW Engineers C-based code SW Developers CPU GPU Ease of Implementation Best Performance per Watt FPGA
    • 22. Stratix 10 Impact On Data Centers 22  Faster data processing 2X searches, 2X transactions, 2X video operations  Lower energy cost >10X performance per watt improvement vs. alternatives More servers in a rack High speed, high-end FPGAs offer strategic differentiation in data center market PowerSoC PowerSoC PowerSoC PowerSoC
    • 23. Summary 23 FPGAs are used throughout the communications infrastructure for flexibility, adaptability and faster time-to-market Altera’s new SoC devices combine FPGA and ARM, making the network more IoT-ready: intelligently flexible and adaptable Explosive growth of IoT devices driving substantial new requirements for the communications and datacenter infrastructure Altera’s newest FPGAs and SoCs will help enable infrastructure advancements to be IoT-ready FPGAs are widening the technology gap vs. ASICs and ASSPs
    • 24. Thank YouThank You Chris Balough Senior Director, SoC Products

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