Voltagestorm

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Voltagestorm

  1. 1. VoltageStorm® Transistor-Level Rail Analysis User Guide Product Version 10.1 December 2010
  2. 2. © 2009–2010 Cadence Design Systems, Inc. All rights reserved. Cadence Design Systems, Inc. All rights reserved. Printed in the United States of America. Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134, USA Open SystemC, Open SystemC Initiative, OSCI, SystemC, and SystemC Initiative are trademarks or registered trademarks of Open SystemC Initiative, Inc. in the United States and other countries and are used with permission. Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. contained in this document are attributed to Cadence with the appropriate symbol. For queries regarding Cadence’s trademarks, contact the corporate legal department at the address shown above or call 800.862.4522. All other trademarks are the property of their respective holders. All other trademarks are the property of their respective holders. Restricted Permission: This publication is protected by copyright law and international treaties and contains trade secrets and proprietary information owned by Cadence. Unauthorized reproduction or distribution of this publication, or any portion of it, may result in civil and criminal penalties. Except as specified in this permission statement, this publication may not be copied, reproduced, modified, published, uploaded, posted, transmitted, or distributed in any way, without prior written permission from Cadence. Unless otherwise agreed to by Cadence in writing, this statement grants Cadence customers permission to print one (1) hard copy of this publication subject to the following conditions: 1. the publication may be used only in accordance with a written agreement between Cadence and its customer; 2. the publication may not be modified in any way; 3. any authorized copy of the publication or portion thereof must include all original copyright, trademark, and other proprietary notices and this permission statement; 4. the information contained in this document cannot be used in the development of like products or software, whether for internal or external use, and shall not be used for the benefit of any other party, whether or not for consideration Disclaimer: Information in this publication is subject to change without notice and does not represent a commitment on the part of Cadence. The information contained herein is the proprietary and confidential information of Cadence or its licensors, and is supplied subject to, and may be used only by Cadence’s customer in accordance with, a written agreement between Cadence and its customer. Except as may be explicitly set forth in such agreement, Cadence does not make, and expressly disclaims, any representations or warranties as to the completeness, accuracy or usefulness of the information contained in this document. Cadence does not warrant that use of such information will not infringe any third party rights, nor does Cadence assume any liability for damages or costs of any kind that may result from use of such information. Restricted Rights: Use, duplication, or disclosure by the Government is subject to restrictions as set forth in FAR52.227-14 and DFAR252.227-7013 et seq. or its successor.
  3. 3. VoltageStorm Transistor-Level Rail Analysis User Guide December 2010 3 Product Version 10.1 About This Manual. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 How This Manual Is Organized . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Conventions Used in This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Approaches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Transistor-Level Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Thunder, UltraSim, and Lightning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Static and Dynamic Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PGS Exploration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2 Issues in Power-Grid Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 IR Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Symptoms of IR Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Electromigration (EM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Wearout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Joule Heating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Fusing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Symptoms of Electromigration Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Advanced Processing Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Evaluating Electromigration Risk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Modeling Electromigration Risk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Why Are Power-Grid Failures More Common Today? . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Advances in Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Contents
  4. 4. VoltageStorm Transistor-Level Rail Analysis User Guide December 2010 4 Product Version 10.1 Design Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Hierarchical Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Conservative Design for Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Location and Design of I/O Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Isolation of Block Power Grids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Low-Power Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Errors in Connecting Global and Block Power Grids . . . . . . . . . . . . . . . . . . . . . . . . . 32 Power-Grid Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Power-Grid Analysis Methodologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Architecture of VoltageStorm Power-Grid Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Tap Currents in Decoupled Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Static and Dynamic Power-Grid Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Static Power-Grid Analysis Methodologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Basic Dynamic Power-Grid Analysis Methodologies . . . . . . . . . . . . . . . . . . . . . . . . . 47 Advanced Power-Grid Analysis Methodologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Correcting IR Drop and Electromigration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3 Preparing to Use VoltageStorm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Required Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Transistor Circuit File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Power-Grid Resistance Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Transistor Model Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Directory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Preparing to Run Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Setting Up the XTC Command File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Generating Basic Static Analysis Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Creating Model Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Creating the Circuit File for Static Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Adding Capacitance Data to the Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Creating the Circuit File for Dynamic Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Backannotating Net and Device Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Updating the Circuit File for Dynamic Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
  5. 5. VoltageStorm Transistor-Level Rail Analysis User Guide December 2010 5 Product Version 10.1 4 Using VoltageStorm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Circuit Netlist File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Power-Grid Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Tutorial Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Static Ipeak Power-Grid Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Performing Ipeak Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Viewing Analysis Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 VoltageStorm Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Applying Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Saving Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Recommended Analysis Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Recommendations for Using Lightning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Static Activity-Based Power-Grid Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Using Activity Data to Compute Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Performing Activity-Based Power-Grid Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Static Vector-Based Power-Grid Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Vectors Input to Thunder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Performing Vector-Based Netlist Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Performing Vector-Based Static Power-Grid Analysis . . . . . . . . . . . . . . . . . . . . . . . 117 Dynamic Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Vector Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Dynamic Analysis Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Performing Dynamic Netlist Analysis with Thunder . . . . . . . . . . . . . . . . . . . . . . . . . 125 Performing Dynamic Netlist Analysis with UltraSim . . . . . . . . . . . . . . . . . . . . . . . . . 127 Performing Dynamic Power-Grid Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Viewing Dynamic Analysis Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 PGS Exploration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 When to Use PGS Exploration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 How to Use PGS Exploration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Static PGS for Mixed-Signal Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
  6. 6. VoltageStorm Transistor-Level Rail Analysis User Guide December 2010 6 Product Version 10.1 Performing Static PGS for Mixed-Signal Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 A StormCenter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Starting StormCenter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Viewing a Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Zooming and Panning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Adding Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Editing Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Resizing Plot Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 B Preparing to Use VoltageStorm Using QRC . . . . . . . . . . . . . . . . . 167 Required Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Power-Grid Analysis Methodologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 PowerGrid Analysis Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Directory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Flows to prepare data for input to QRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 QRC Parasitic Extraction Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Transistor Model Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Creating Model Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Running Static and Dynamic Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
  7. 7. VoltageStorm Transistor-Level Rail Analysis User Guide December 2010 7 Product Version 10.1 About This Manual This manual describes how to use VoltageStorm Transistor-Level PGS, the Cadence tool that analyzes your chip’s power distribution network for IR voltage drop and metal electromigration failure. How This Manual Is Organized This manual covers the following topics: ■ Chapter 1, “Introduction,” describes the purpose, features, inputs, outputs, and design flow involved in using VoltageStorm Transistor-Level PGS. ■ Chapter 2, “Issues in Power-Grid Analysis,” explains the potential sources of power-grid design problems related to IR drop and electromigration, as well as methodologies to detect them. ■ Chapter 3, “Preparing to Use VoltageStorm,” describes how to generate the data required to run VoltageStorm Transistor-Level PGS. ■ Chapter 4, “Using VoltageStorm,” is a guide that steps through the basic procedures involved in using VoltageStorm Transistor-Level PGS to analyze your power distribution network. ■ Appendix A, “StormCenter,” describes StormCenterTM , Cadence’s interactive waveform viewer. ■ Appendix B, “Preparing to Use VoltageStorm Using QRC,” describes StormCenterTM, Cadence’s interactive waveform viewer. ■ Glossary defines the terms and concepts that you should understand to use VoltageStorm Transistor-Level PGS effectively. Conventions Used in This Manual This document uses the following syntactical conventions: ■ Commands and parameters used on the command line are given in Courier font: command_name
  8. 8. VoltageStorm Transistor-Level Rail Analysis User Guide About This Manual December 2010 8 Product Version 10.1 ■ Menu commands and the fields in dialog boxes in the graphical user interface are given in Helvetica italic font: File – Save An en dash (–) separates the menu name and the command name. ■ Variables for which you are to substitute a value are given in Courier italic font: filename, cellname, layer_name ■ File names are given in Courier font: library.lib ■ Angle brackets enclose optional parameters: <options> ■ Vertical bars (|) in commands indicate choices. ■ Square brackets indicate that you must select one of the choices: [a|b|c] ■ Square brackets followed by a plus sign mean that you can choose more than one of the choices, but you must select at least one: [a|b|c]+ ■ Use white space (tabs or spaces) to separate a command and its arguments.
  9. 9. VoltageStorm Transistor-Level Rail Analysis User Guide December 2010 9 Product Version 10.1 1 Introduction The VoltageStorm product includes two separate and distinct flows that perform power-grid analysis (PGS). The first flow, called VoltageStorm Professional Edition, analyzes and macromodels sub- blocks and cells at the top level of a design. It is designed to support efficient PGS analysis of embedded ASIC and system-on-a-chip (SoC) design styles. It has the ability to invoke PowerMeter to perform instance-based power calculation. This flow is described in the VoltageStorm Cell-Level Rail Analysis User Guide. This manual focuses on the second flow, called VoltageStorm Transistor-Level Rail Analysis, which performs PGS down to the transistor level. For brevity, the tool is called VoltageStorm in this manual. This chapter discusses the chip design problems addressed by VoltageStorm. It explains the potential sources of power-grid design problems related to IR drop and electromigration, as well as the methodologies to detect them. Features VoltageStorm is designed to help you verify that the power network on your chip does not suffer from IR drop or electromigration failure as you sign off your design. The occurrence of these types of failures experienced an upsurge as integrated circuits designs transitioned to 0.35-μm processes and continued to grow in 0.25-μm processes and below. An indication of these failures is the declining rate of first-time silicon success and the increasing number of design iterations required in manufacturing ASICs and other standard-cell designs. As a result, the application of tools such as VoltageStorm is becoming a signoff requirement in many design methodologies. Silicon foundries do not commonly discuss these failure mechanisms as reasons for chip failure, because IR drop failures may create an appearance of poor methodology on their part. Similarly, electromigration failures may create an appearance of poor process control on the part of the foundry. In reality, most failures are a consequence of today’s increasing chip design complexity. What was once taken for granted or visually checked is now much too
  10. 10. VoltageStorm Transistor-Level Rail Analysis User Guide Introduction December 2010 10 Product Version 10.1 complex, so power-grid verification tools are increasingly becoming an integral part of design flows for power-grid signoff (PGS). Foundries are endorsing power-grid signoff as a way to eliminate design surprises before designs reach the foundry. High-speed microprocessor designers were the first to adopt extended verification methodologies, and ASSP and high-end ASIC designers are adopting them today. Approaches VoltageStorm is designed to help you find weak spots in the implementation of your power grid at the block and full-chip stages of design. Weak spots are implementation characteristics that result in excessive IR drop, electromigration stress, or pin currents during the operation of the chip. VoltageStorm not only finds weak spots but helps you understand what implementation decisions created the weak spot. Finding weak spots can be divided into three approaches: ■ The first is finding weaknesses in your power grid that are likely to impact the proper functioning of your chip, regardless of the magnitude of the impact. This approach is quite common and best addressed by static analysis. It is strongly recommended that you apply static analysis before dynamic analysis, because static analysis can find problems quickly. Also, static analysis can find problems that even thorough dynamic analyses can miss because of insufficient vector coverage. ■ The second approach to finding weak spots is to predict a worst-case IR drop vector on the basis of the limited coverage of the vectors for analysis. Vector compression predicts this test vector on the basis of the vectors that you have. ■ The third approach to finding weak spots is to assess the precise voltage drop on the grid for a specific test vector. This approach is common in memory design or when the cost of changing a design is high, and you want to determine the exact magnitude of the IR drop. VoltageStorm supports all three approaches. Transistor-Level Analysis VoltageStorm Transistor-Level PGS performs a flat, transistor-level analysis of the power grid of true full-custom digital designs and IP blocks. If you are not using easily identifiable library elements, you may require transistor-level recognition. It is intended for those using an SoC design methodology or an ASIC methodology and who want accuracy down to the transistor level.
  11. 11. VoltageStorm Transistor-Level Rail Analysis User Guide Introduction December 2010 11 Product Version 10.1 Thunder, UltraSim, and Lightning VoltageStorm uses Thunder or UltraSim™, which are netlist analysis tools, and Lightning, which is a power-grid analysis tool, to perform these analyses. Thunder performs a transistor- level analysis of your design. It analyzes the entire transistor netlist by using the voltage sources, transistor model data, and vectors that you provide. A power grid in Thunder is modeled as a single node. Lightning performs a detailed analysis of that power-grid node when the node is represented by its actual resistor, inductor, and capacitor components. It only processes the devices connected directly to the power grid of interest. The power grid is modeled as a linear circuit with voltage sources representing the power pins and current sources representing the transistor taps on the grid. Power current flows from the voltage sources, through the grid, and out the current taps. Proper analysis requires all three components: the voltage sources, the resistor-inductor-capacitor grid, and the tap current sinks. If the design contains no tap current sink, the entire grid is at the voltage of the sources (assuming that they are at the same voltage). You must add voltage sources in Lightning. If the design contains no voltage sources, the power grid cannot be analyzed. Without a power grid, there is nothing to analyze. Thunder calculates current information for each device connected to the power grid (VDD or VSS) and passes these currents (plus device capacitances for dynamic power-grid signoff) to Lightning. The interface between the tools is based on the names of the devices (almost always transistors) connected to the power node. Thunder passes current and capacitance data to Lightning for each transistor. Lightning passes IR drop data to Thunder for each transistor. Itaputil either reports the characteristics of tap current files or extracts portions of the data and places them into a new tap current file. As an alternative to Thunder in the dynamic analysis, you can use Cadence’s UltraSim simulator. UltraSim is a fast, multi-purpose, single-engine, hierarchical simulator, designed for the verification of analog, mixed-signal, and digital circuits. UltraSim provides accurate, vector-based dynamic circuit simulation and high-performance hierarchical circuit simulation and rail analysis while greatly improving the performance and capacity of the dynamic analysis. The UltraSim dynamic analysis offers two flows: ■ It can use lumped capacitance for the signal nets for higher performance in the actual circuit simulation. ■ It can use distributed resistance and capacitance for signal nets for greater accuracy in signal timing. See “Performing Dynamic Netlist Analysis with UltraSim” on page 127 for detailed information about these two flows.
  12. 12. VoltageStorm Transistor-Level Rail Analysis User Guide Introduction December 2010 12 Product Version 10.1 Thunder differs from UltraSim in the following ways: ■ Thunder requires you to run Tablegen for MOS devices before using Thunder. UltraSim reads in the models directly without requiring you to use Tablegen. ■ Thunder requires the .simplexlib command in the circuit file to specify the table models. UltraSim requires the .lib command in the circuit file to specify the SPICE model file. ■ Thunder directly reads the capacitance database output by Ice when you use the .capdb command in the circuit file. It can also read the DSPF file output by Rain. In contrast, UltraSim reads the output of the capdbutil utility, which processes the Ice capacitance database, when you use the .usim_opt capfile command in the circuit file. Static and Dynamic Analysis VoltageStorm supports both static and dynamic analysis. For static analysis, you can use these methodologies: ■ Accura, an algorithm embedded in LibGen that performs activity-based static analysis ■ Maximum saturation currents ■ Net activity data ■ Vector-based netlist analysis These methodologies are described in detail in “Static Power-Grid Analysis Methodologies” on page 42. For dynamic analysis, you can use these methodologies: ■ Single-vector analysis ■ Vector compression These methodologies are described in detail in “Basic Dynamic Power-Grid Analysis Methodologies” on page 47. In addition to these, VoltageStorm offers advanced methodologies for both static and dynamic analysis. These are described in “Advanced Power-Grid Analysis Methodologies” on page 52.
  13. 13. VoltageStorm Transistor-Level Rail Analysis User Guide Introduction December 2010 13 Product Version 10.1 PGS Exploration PGS Exploration enables you to perform power-grid ECOs within VoltageStorm. Before PGS Exploration, engineering change orders (ECOs) that addressed power-grid problems identified by VoltageStorm required you to complete a lengthy and complex ECO loop, as shown in Figure 1-1 on page 13. Figure 1-1 ECO Loop Before PGS Exploration Because of the complexity and number of steps involved, performing and validating the effects of such an ECO was both time-consuming and resource-intensive. Since PGS Exploration enables you to perform power-grid ECOs within VoltageStorm, you can remove all power-grid problems from a design in a single ECO pass. Once the power grid is clean in VoltageStorm, you then create a single ECO list, called a change report, which guides the implementation of the layout modifications necessary to create the clean power- grid design, as shown in Figure 1-2 on page 14. ECO loop Edit the power-grid layout Re-extract the power grid Re-load power grid into VoltageStorm Transistor-Level PGS Perform power-grid solve Layout environment Fire & Ice VoltageStorm Transistor- Level PGS
  14. 14. VoltageStorm Transistor-Level Rail Analysis User Guide Introduction December 2010 14 Product Version 10.1 Figure 1-2 ECO Loop Using PGS Exploration PGS Exploration enables you to quickly experiment with power-grid changes, then use VoltageStorm’s static power-grid analysis to show the effects of these modifications on the performance of the power grid. Because all this ECO functionality is available within VoltageStorm, you do not need to re-extract and re-load the power-grid network with each ECO, so the turnaround time is extremely fast. Note: Because PGS Exploration is based on modifications to the resistive network of the power grid, use it only with static power-grid analysis. Using PGS Exploration with dynamic power-grid analysis is not recommended. Design Flow A detailed view of the design flow involved in using Thunder in VoltageStorm is shown in Figure 1-3 on page 15. The design flow involved in using UltraSim in VoltageStorm is shown in Figure 1-4 on page 16. See Appendix B, “Preparing to Use VoltageStorm Using QRC” for a flow using QRC rather than Fire & Ice. The QRC interface provides the ability to model small geometries (90nm, 65 nm ...) accurately. Change power grid in VoltageStorm Perform power-grid solve ECO loop Back to layout to implement changes Create ECO change report All within VoltageStorm
  15. 15. VoltageStorm Transistor-Level Rail Analysis User Guide Introduction December 2010 15 Product Version 10.1 Figure 1-3 VoltageStorm Static and Dynamic Design Flow with Thunder Resistanc GDSII Hierarchical Calibre Connectivity XTC Annotat SPICEStripe Capacitan DistR MergeNet RC Power- IceFire Lightning or Thunde Tap current data (*.ptiavg, Transistor Pass/fail Voltage source Rain Interconnect Tablege Activit Model Comma VCD file Vector Circuit
  16. 16. VoltageStorm Transistor-Level Rail Analysis User Guide Introduction December 2010 16 Product Version 10.1 Figure 1-4 VoltageStorm Dynamic Design Flow with UltraSim Resistanc GDSII Hierarchical Calibre Connectivity XTC Annotat SPICEStripe Capacitan DistR MergeNet RC Power- IceFire Lightning or capdbut Circuit UltraSi Tap current data (*.ptiavg, Transistor Pass/fail Voltage source
  17. 17. VoltageStorm Transistor-Level Rail Analysis User Guide Introduction December 2010 17 Product Version 10.1 Inputs The input to VoltageStorm is a GDSII file output by a place-and-route tool. Outputs As output, VoltageStorm produces plots of power-grid IR drop, resistor current flow, and electromigration analysis. In addition, it can produce these outputs: ■ Filtered plots, which are plots of your design with filters applied to data values. The filters determine the subset of data that you view and how each subset should be colored to make the plot meaningful. These plots can be stored in GIF format. ■ Text reports, which contain the subset of the data in which you are interested. The specific data reported is controlled by the filters just described. Although text reports are easy to pass to other tools, they can be very large if you do not filter carefully. ■ Sorted text reports, which can rank your data in worst-case order. You can print this data or access it interactively to take you to the worst errors on your chip. ■ GDSII overlays of filtered data, which enable you to overlay the results of your analysis filtering directly on top of the design in the layout editor. ■ Saved states of your power grid, which you can reload at a later time. This option makes it more efficient to perform data filtering because you do not need to perform the solve again. ■ Movies, which are a unique feature of dynamic analysis in VoltageStorm. Plots of individual time steps are created in the same form as in static analysis but can be placed together to form an animated sequence of your power grid’s behavior.
  18. 18. VoltageStorm Transistor-Level Rail Analysis User Guide Introduction December 2010 18 Product Version 10.1
  19. 19. VoltageStorm Transistor-Level Rail Analysis User Guide December 2010 19 Product Version 10.1 2 Issues in Power-Grid Analysis This chapter discusses the chip design problems addressed by VoltageStorm. It explains the potential sources of power-grid design problems related to IR drop and electromigration, as well as the methodologies to detect them. IR Drop IR drop is a reduction in voltage that occurs on both power and ground networks in integrated circuits. Integrated-circuit design usually assumes an ideal power supply that can instantly deliver any amount of current to maintain the specified voltage throughout the chip. In reality, however, narrower metal line widths cause an increase in the resistance and therefore in the amount of voltage drop in the chip. The amount of voltage drop depends on the effective resistance from the pad to the gates. Figure 2-1 on page 19 illustrates the concept of IR drop. Figure 2-1 Typical Power-Grid Structure This figure shows a power supply connected to the chip pads. The power distribution system (generally a grid) is illustrated by the R11-R14 resistors for VDD and R21-R24 resistors for VSS. G1-G4 are the connections between logic gates on the power distribution system. Typically, when you perform transistor-level simulation, these voltages (V1- V4) are assumed to be equal. In other words, all R11-R14 and R21-R24 resistances would be 0.0 ohms, so all G1-G4 gates would have ideal power supply voltages, VDD and VSS. + - Vpower VSS VDD Pad Pad R11 R21 R22 R12 R23 R13 R24 R14 G1 G2 G3 I3I2I1 I4 G4 V1 V2 V3 V4
  20. 20. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 20 Product Version 10.1 In reality, the power-grid resistances of a chip are non-zero. For example, gate G4 never has an ideal VDD voltage at its power pin when it is active; it has a lower voltage. The current flowing from the power supply to G4 must flow through the power distribution network. A current, I, flowing through an effective resistance, R, introduces a voltage drop, V = IR. (The term “IR drop” is derived from IR.) IR drop or ground bounce on the VSS power-grid distribution network is an increase in the VSS voltage at gates G1-G4. Figure 2-1 also illustrates the complexity of power grids and IR drop. Assume that gate G4 has a VDD power-grid current of I4 amperes. No other gate has current. The I4 current flows from the power supply through the power grid to G4. The IR drop at gate G4 is then I4(R11+R12+R13+R14). In addition, because of the I4 current at gate G4, gate G2 does not have an ideal power supply. It has an IR drop of I4(R11+R12). Therefore, the current of each gate in a design causes some type of IR drop for all other gates in the design. If the gates along the metal line switch together, the IR drop can be large. Given simultaneous currents I1-I4 for the G1-G4 gates, respectively, in Figure 2-1 on page 19, the IR drop at gate G4 would be the following: I1(R11)+I2(R11+R12)+I3(R11+R12+R13)+I4(R11+R12+R13+R14) IR drop can be either a local or global phenomenon. ■ IR drop is a local phenomenon when a number of gates in close proximity switch at once, causing IR drop in that proximity. Local IR drop can also be caused by a higher resistance to a specific portion of the grid, such as R14 being much larger than expected. ■ IR drop is also a global phenomenon when activity in one region of a chip causes IR drop in other regions. In a well-meshed power grid with equally distributed current, the power grid typically has a set of equipotential IR drop surfaces that form concentric circles centered in the middle of the chip, which has the largest IR drop. Large gate currents throughout the chip increase the magnitude of these equipotential IR drop surfaces. The IR drop formulations illustrate why it is important for the gates in a design to switch at different times. If they all switched at once, the local or global IR drop on a chip would be extremely large. For some portions of a design, however, it is important for the gates to switch together. The clock and the latches that it drives must switch together in a synchronous digital system, so some amount of IR drop is inevitable in a chip. Figure 2-1 on page 19 also illustrates the difference between average and peak IR drop. If all four gates switched at once, the IR drop at gate G4 is that shown by the calculation given earlier in this section. If this peak current occurred over one fourth of the clock cycle, the average IR drop at gate G4 over the entire clock cycle would be one quarter of that value. The peak IR drop at any location in a chip can therefore be much larger than the IR drop averaged over a clock cycle. As the size of a block increases, the ratio of the peak IR drop to the average decreases towards 1.0, because the probability of many gates switching at once decreases significantly. The primary causes of simultaneously switching IR drop (noise) is the switching
  21. 21. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 21 Product Version 10.1 of the clock, a bus, or signal pads. These problems are due to many large gates switching synchronously in one area. You can easily recognize these situations and verify them. Symptoms of IR Drop Because the number of failures resulting from IR drop has become significant only recently, many designers do not look at power distribution as a potential source of chip failure. The symptoms of IR drop problems can frequently resemble timing or even signal integrity problems. Symptoms of IR drop problems include the following: ■ Non-functional chips. If the global IR drop is too high when a chip operates, logic gates malfunction. The failure resembles a logical functional failure or manufacturing problem, although logic simulation indicates that the design is correct. One way of diagnosing this symptom is to increase the power supply voltage and see if the chip works. ■ Intermittent or data-dependent functional failures. Local IR drop problems are sensitized, or forced to occur, by specific operations in close proximity, such as all bits of a bus switching at once. In normal operation, the specific sensitization might not occur. However, a specific data input activates the problem. The symptom appears as a logic functional failure of that portion of the chip. ■ Timing failure. When the global IR drop is high, but not high enough to cause complete logic failure, the symptom is a timing failure of the chip. In this case, the IR drop slows down the speed of the gate operation. Experiments have shown that a 5 percent IR drop on a gate can slow down its speed by up to 15 percent. The reduction in speed is due to two mechanisms, as shown in Figure 2-2 on page 22. First, the IR drop on the power input of gate G1 slows the charging speed of the output of that gate. Explained simply, the output voltage of gate G1 rises only up to VDD minus the IR drop. In turn, this drop reduces the logical high input voltage to gate G2, reducing its switching speed as well.
  22. 22. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 22 Product Version 10.1 Figure 2-2 Impact of IR Drop on Gate Speed ■ Intermittent or data-dependent timing failures. Like intermittent functional failures, specific data inputs can cause IR drop that appears to be a timing failure. An intermittent timing failure of this type is also symptomatic of a signal net cross-coupling capacitance problem. One way of diagnosing this symptom is to decrease the clock frequency and see if the chip works. Electromigration (EM) Electromigration is used as a general term to describe failure mechanisms in the metal wires of a computer chip caused by the movement of metal atoms in a wire because of high current stress. As electrons move through a metal wire, they collide with the atoms in that wire. These collisions cause wires to become heated, and If enough electrons collide with a metal atom over a period of time, the metal atom may move in the direction of the electron flow, causing two problems. ■ First, if enough atoms are moved, the wire effectively breaks and becomes an open circuit. ■ Second, if enough atoms move to the same location, a short to an adjacent metal wire can be created. This phenomenon is commonly known as fusing. Either of these mechanisms changes the functionality of the chip. Two distinct physical phenomena cause electromigration: wearout and Joule heating. + - VDD VDD-IR drop Gate G1 Gate G2 VIH I
  23. 23. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 23 Product Version 10.1 Wearout Electromigration in a specific sense is a long-term wearout mechanism of chip interconnect wires. As metal atoms are moved and the wire becomes narrower (in the location from which the atoms are moving), the resistance of the wire increases. If atom movement continues, the wire eventually breaks. Because wearout can take a significant amount of time to be observed, failure due to wearout is measured as a statistical process and is characterized by a wire’s mean time to failure (MTTF). To reduce the impact of electromigration, chip interconnect wires on a given metal layer are built from several metal materials in a sandwich fashion. The extra metal layers in the wire, generally the top and the bottom layers in the sandwich structure, are more resistant to electromigration, so they help prevent total wire failure because of breaks. Electromigration failures are therefore defined as an unacceptable increase in the resistance of the wire rather than an outright break in the wire. Because electromigration is the result of long-term wearout, the risk to a wire is measured in terms of the long-term average current flowing through the wire. There remains some debate in the reliability community about the proper model for wires exposed to alternating current flow. One approach indicates that when the average current is 0 A, no electromigration occurs. Another approach says that the recovery from the reversed current is not full, so the average should be the peak in one direction minus a recovery factor times the reverse current. A recovery factor of 0.0 indicates no recovery, and a factor of 1.0 indicates full recovery. Joule Heating Joule heating refers to the excessive heating of a specific segment of a wire because of high alternating currents. Wires are heated as alternating current moves through them. This heating occurs regardless of the direction of the current. If the heating of the wire becomes significant, thermal expansion and temperature-induced electromigration occurs. Since the risk of Joule heating increases with temperature, and increasing frequency increases heating effects, electromigration due to Joule heating is associated with high-frequency wires. Because the root cause of Joule heating failure is different from electromigration, different measures are applied in verification.
  24. 24. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 24 Product Version 10.1 Fusing Fusing is a specific failure mechanism related to electromigration. It refers to the instant failure of a wire segment because of excessive instantaneous current. To address this failure mechanism, different measures are applied in verification. Some reliability researchers classify this failure mechanism as a subset of Joule heating. Symptoms of Electromigration Problems Because electromigration is a wearout phenomenon, its symptoms are primarily a change in either the timing or functionality of a chip over time. Wires that provide unique connectivity in the circuit cause total functional failure if they break because of electromigration. Wires that are inherently redundant, such as a meshed power grid, exhibit symptoms of high IR drop after electromigration failure results in disconnected sections of the power grid. If electromigration causes a short between wires on a chip, total functional failure occurs. Advanced Processing Techniques Using metals such as titanium nitride and copper in chips can also contribute to electromigration failure. Titanium Nitride To reduce the impact of electromigration, chip interconnect wires on a given metal layer are built from several metal materials in a sandwich fashion, as shown in Figure 2-3 on page 24. Figure 2-3 Multiple Materials Used to Build a Single Wire Generally the top and the bottom layers in the sandwich structure are constructed from titanium nitride (TiN), which is more resistant to electromigration. This structure helps to prevent total open circuit failures; however, because the resistivity of the TiN layer is greater Aluminum Titanium nitride
  25. 25. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 25 Product Version 10.1 than aluminum, electromigration failures are defined as an unacceptable increase in the resistance of the wire rather than an outright break in the wire. Copper Interconnect State-of-the-art process technologies use copper as chip interconnect material because copper offers not only lower resistivity but also higher resistance to electromigration wearout. However, copper interconnect structures are not as deep as aluminium structures, so the cross-section area is smaller and therefore the current densities are higher. As a result, electromigration-based failures still occur in copper structures. In contrast to aluminum-based processes, vias built with copper increase the likelihood of electromigration wearout and require more detailed verification. Evaluating Electromigration Risk Electromigration occurs in metal wires that conduct high current densities. Conducting electrons collide with diffusing metal atoms and impel the atoms in the direction of electron flow. This collision produces a mass flux opposite to that of the current. Divergences in this mass flux can result in damage to the conductor in the form of voids or hillocks. You can minimize this problem by limiting the current density in metal conductor lines, vias, and contacts. Electromigration resistance is primarily a function of processing parameters. Many of the variations observed in the lifetime behavior of conductors because of electromigration cannot be attributed to a specific cause. In addition, material contains significant lot-to-lot variations. To fully understand electromigration within the chip, you must be familiar with the specific properties of your own material and process. In some cases, complete data is not available. The following suggestions may help you in making an evaluation. The figures quoted here are from relevant literature over the past 25 years; you should consider them non-definitive values and not necessarily representative of your material or process. Cadence provides these figures only as background information. In recent evaluations of electromigration performance in the industry, it has become commonplace to observe that failures in lines connected to bond pads obey 1/j2 kinetics and that lines connected to vias and contacts usually obey 1/j kinetics. Therefore, these are the default values used in this simulation. If you have evidence that your process provides other kinetics, you can make suitable changes in the modeling. The following table shows the pre-exponential, A, and activation energy for line and via electromigration failure for wide and narrow lines for a variety of alloys. The values chosen are conservative and represent the latest data available from leading industrial laboratories.
  26. 26. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 26 Product Version 10.1 Al/Si figures are estimated from the expectation that lifetimes without Cu alloying are about 10 percent of those with Cu. No recent data on this assumption is available, and earlier data is questionable in view of recent advances in electromigration testing procedures. Note: These values are not independent. If you choose a different value for the activation energy, it is necessary to determine another value for A. Table 2-1 Pre-Exponential, A, and Activation Energy for Line and Via Electromigration Failure The units of A are the following: ■ Amp-hours per cm2 degree for n=1 ■ Amp2-hours per cm4 degrees for n=2 For vias, the current density is defined as the current density in the wire immediately contacting the via or the contact to silicon. This density is assumed to be for a line with a width equal to the via. Al and Al/Si are assumed to be equivalent, and all Al/Cu alloys are assumed to be created equal. 1. Anthony S. Oates, Proc. 34th Ann. IRPS, 164 (1996) Metal Configuration n A Ea Al/Si wide line 2 130 to 20,000 0.5 eV Al/Si narrow line or Al/Cu wide line, with or without barrier shunt layer 2 1,300 to 80,000 0.6 eV Al/Cu narrow line without barrier shunt layer 2 1,300 to 200,000 0.8 eV Al/Cu narrow line with barrier shunt layer 2 13,000 to 800,000 0.8 eV Al/Si via 1 .00001 0.8 eV Al/Si via 2 7.5 0.5 eV Al/Cu via without barrier 1 .0001 0.8 eV Al/Cu via without barrier 2 75 0.8 eV Al/Cu via with barrier 1 .0004 to .008 0.8 eV Al/Cu via with barrier 2 300 to 16,000 0.8 eV
  27. 27. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 27 Product Version 10.1 2. Carole D. Graas, Huy A. Le, Joe W. McPherson, and Robert H. Havemann, Proc 32nd Ann. IRPS (1994) 3. Keiichi Hashimoto, Kenshin Touchi, and Hiroshi Onoda, Proc. 32nd An. IRPS, 18 (1994) An additional source that you may wish to check is Bill Baerg, Rob Crandall, and Ken Wu, 32nd Ann. IRPS, 195 (1994). Refer to the VoltageStorm Transistor-Level Rail Analysis User Guide or the VoltageStorm Cell-Level Rail Analysis Users Guide for information on power-grid analysis. Refer to the ElectronStorm Manual for information on signal electromigration analysis. Modeling Electromigration Risk Electromigration risk analysis requires the use of failure models. The choice of failure model depends on the particular manufacturing process and design rules. The failure kinetics vary according to the metal line width. They must be determined from the test structures. Model parameters such as A_n, A_w, and n (the current density coefficient) are used to describe the predominant failure kinetics. On the basis of the calculated average current density, Cadence analysis tools use Black’s Equation to determine the mean time to failure (MTTF): ■ n is either 2 for nucleation-dominated failure or 1 for growth-dominated failure. ■ A is the technology and structure dependent pre-factor. ■ T is the temperature. ■ m is the temperature coefficient. ■ j is the average current density. ■ Ea is the activation energy for the electromigration mechanism. ■ k is Boltzmann’s constant. The MTTF is then used to calculate the probability of failure for a line segment: t50 AT m j n -------------exp Ea kT -------- ⎝ ⎠ ⎛ ⎞=
  28. 28. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 28 Product Version 10.1 ■ t is the expected lifetime of the design, which you can specify by using the Lifetime environment variable. ■ σis the lognormal standard deviation. It is process-dependent and must be determined by using test structures. It is a model parameter that you can specify layer by layer. After Cadence analysis tools calculate the failure probability for each wire segment, they use the following calculation to determine the failure probability for the full chip: This approach assumes a lognormal failure distribution, which is analogous to the weakest link in a chain. Cadence analysis tools report the overall probability of failure after they finish the analysis. They report the inverse of the failure probability for each wire segment as electromigration risk. You must specify several processing parameters for each layer to obtain good results from electromigration risk analysis. See “model” in the Lightning Manual for these parameters and their default values; these defaults assume Al/Cu metal layers. In addition, you should set the Default_Temp and Lifetime .simplexrc environment variables. Cadence analysis tools can include temperature effects on resistance. The model parameters for each layer now include fields for TC1, TC2, and TREF. The resistance of a resistor is calculated by using the following formula: Reffective=R*(1+TC1 * delta_t + TC2 * delta_t2 ) Pfi t( ) σ 2π ln t50 t⁄( ) -------------------------------------exp t50 t⁄( )ln 2σ ---------------------------- ⎝ ⎠ ⎜ ⎟ ⎛ ⎞ 2 –= pf n t,( ) 1 1 Pfi t( )–( ) i 1= n ∏–=
  29. 29. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 29 Product Version 10.1 where delta_t is defined as the default temperature minus TREF. Lifetime is defined as the probable time, in years, until failure because of electromigration. You use a lifetime calculation during electromigration risk analysis. Cadence analysis tools calculate the probability of the chip failing by the time specified by the Lifetime global environment variable. The probability of failure ranges between 0 and 1, although a probability of 1 indicates that assumptions were violated in the calculations. If the reported probability of failure is high, it means that there are components in the design with relatively short mean times to failure. Examine these components, and make modifications to lower the probability of failure. Why Are Power-Grid Failures More Common Today? A combination of factors causes the increase in IR drop and electromigration failures. In the past, designers of low-frequency circuits implementing 0.35-μm three-layer metal processes rarely encountered IR drop or electromigration issues. However, designs with frequencies above 100 MHz, 0.25-μm processes, or four or more layers of metal increase the risk of problems. Advances in Processing The first set of causes is related to advancements in processing. Most chip feature sizes are decreasing in accordance with Moore’s Law. Transistor sizes are decreasing, permitting a higher density of design. New, more powerful transistors require a lower-power supply voltage to avoid device failures. A lower supply voltage means lower noise margins (IR drops permitted) on power grids. On the other hand, the ability to design increasingly complex chips leads to increases in overall size and power dissipation. To design the larger chips, more metal layers are being used to implement longer signal and power routing. Narrower wires have higher resistance than previous technologies. These higher-resistance wires and the higher overall power currents naturally lead to increases in IR drop or power-grid noise. The conflicting design trend toward lower noise margins means that you must seek a balance between inherent power-grid noise and power supply noise margins to achieve a successful design. As your design increases in frequency or size, the design space in which you have to balance decreases in area. The natural response to balancing the technology trends is to be more conservative in power- grid design. But more conservative power-grid design means sacrificing chip area—a potentially high cost. Other trends in processing present additional problems. Via and contact resistances are not scaling in accordance with Moore’s Law. The trend is to remain the same or increase in
  30. 30. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 30 Product Version 10.1 resistance. Skin effects limit the effective width of power wires. The higher currents flowing through narrower power grids also increase the current density in power-grid wires, increasing the risk of electromigration. Design Tools A second set of causes of IR drop is the design tools that you use to create power grids on chips. Placement and routing tools today cannot assess the impact of design decisions on IR drop. As a result, these tools introduce the following problems: ■ The parallel nature of data, such as a 64-bit-wide bus, means that placement tools naturally place drivers of each bit of the bus near each other. Large drivers in a local area are a common cause of local IR drop problems. When all bits of the bus switch at once, a local brownout may result. ■ As mentioned earlier, clocks in chips must operate synchronously. Simultaneous clock switching introduces a large, instantaneous IR drop on your power grid. The clocks on some chips today consume up to 40 percent of the chip’s total power. More sophisticated manual clock design purposely skews various clock drivers to reduce IR drop noise as well as radio frequency interference. ■ In addition to clocks, a general trend in design tools is to minimize the delay of switching signals over the clock cycle to minimize the delay of timing-critical paths. As a result, most circuit activity in a design occurs just after the edge of the clock, creating a high instantaneous power demand just after the demand due to the clock itself. ■ Power routing causes problems such as the creation of a via cluster between two large power buses on different metal layers with a single via rather than with an array of 25 or more vias. A single via can be the source of serious IR drop problems and electromigration risk on a chip. For example, via array-filling procedures cannot determine if the via array is large enough for the buses involved. In addition, power-planning techniques in place-and-route tools are too primitive to prevent these problems. Hierarchical Design Hierarchical design is a common practice today, leading to the third common cause of IR drop and electromigration problems. In creating large designs, it is natural to design functional blocks separately and combine them in the final design. However, power grids of blocks are designed to route power only for the block. When blocks are assembled in the design, the union of their individual power grids creates the full-chip power grid. The flow of current through the resulting power grid is usually different from what you expect. You may observe
  31. 31. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 31 Product Version 10.1 power current flowing through blocks rather than in the guard bands around them. An effective power grid for the block also creates a low-resistance power bus for neighboring blocks. This increase in current through the block creates a potential for electromigration or IR drop problems. Avoiding this problem requires some knowledge of the floorplan and power routing of the chip to account for feedthrough currents in the block design. Conservative Design for Timing The fourth common cause of IR drop and electromigration problems is over-conservative design for timing. For example, suppose that a chip exhibits intermittent timing problems after first fabrication. Increasing the buffer size on the assumption that the problem was due to path delays results in the complete functional failure of the chip during second fabrication. The source of the failure, in reality, is IR drop rather than timing. Increasing buffer sizes worsens the problem rather than corrects it. Conservative design for timing must now be balanced with power-grid design. Location and Design of I/O Pads The location and design of I/O pads is the fifth source of IR drop and electromigration problems. Simultaneously switching output pads, which always have a large load, creates a strong demand for power current and causes IR drop. The placement of I/O pads and power pins is a difficult design challenge. I/O rings normally have independent power rings and pads to prevent I/O ring IR drops from affecting the internal chip power. Isolation of Block Power Grids Another common source of IR drop problems is the isolation of block power grids. It is common to isolate the power grids for sensitive blocks in a design, such as phase-lock loops and memories. However, power-grid problems can result from excessive isolation or insufficient isolation. ■ Excessive isolation occurs when the block’s power grid is so well isolated that the resistance from the power pad to the block is excessive, causing IR drop. ■ Insufficient isolation occurs when neighboring blocks create IR drop that seeps into a sensitive block. IR drop in sense amplifiers is a particular concern for memory designers. Low-Power Design The seventh source of IR drop problems is low-power design because of the difference between average and peak power consumption of blocks. The goal of the power grid of a
  32. 32. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 32 Product Version 10.1 block is to distribute the block power current among a number of connections to a global power grid. The global power grid then distributes that current among the power pins. If the current is not distributed well, large IR drops may occur. Many low-power design methodologies apply techniques to reduce the average power dissipation of a block. Techniques such as gated clocking isolate power demands to times of block activity. Power consumption of the block is normal when activated. By gating the clock, you reduce the average power, but the peak power remains as before, creating a potential source of problems. Low power consumption does not necessarily mean low IR drop. If you design the block power grid on the basis of average power consumption, undersized power buses will create IR drop problems. Errors in Connecting Global and Block Power Grids The last source of IR drop problems is errors in connecting global power grids to block power grids. It is common to design global and block power grids separately. In these cases, the global grid is designed to be simply attached to the block power grid at a large number of points after the block is finally placed. Either manual or automatic techniques are used to insert the vias in the design where the grids are to be connected. This attachment of grids is prone to error. Attachment points are often missed, resulting in large IR drops to portions of the chip. Because there is always at least one attachment point, the chips are free of design- rule errors. The problems are only discovered when power-grid analysis is applied. Power-Grid Analysis Power-grid analysis is designed to help identify weak spots in the power network. Weak spots are implementation characteristics that result in excessive IR drop, ground bounce, or electromigration stress of the power grid under operating conditions. A good power-grid analysis tool not only helps you find such weak spots but also helps you understand what you must change to improve the weak spots. You can use many different approaches to identify and correct weak spots in a power grid, including static, activity-based, and dynamic analyses. The value of each of these different approaches is discussed later in this manual. Power-Grid Analysis Methodologies VoltageStorm is referred to as an analysis tool here rather than as a simulator, because it performs more analysis than just simulation. This section describes the power-grid analysis methodologies available in VoltageStorm. They are presented here at a high level. Chapter 3, “Preparing to Use VoltageStorm,” explains the data preparation required for VoltageStorm. Chapter 4, “Using VoltageStorm,” examines these flows in detail.
  33. 33. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 33 Product Version 10.1 Architecture of VoltageStorm Power-Grid Analysis Power-grid analysis involves the extraction of power grid and netlist data from your chip layout, followed by analysis of the power grid and netlist. The architecture of the analysis portion of the system can take two forms: ■ Integration of netlist and power-grid simulation ■ Decoupled netlist and power-grid simulation Integrated Netlist-Power-Grid Simulation Figure 2-4 on page 33 shows the high-level flow for integrated analysis. Figure 2-4 Integrated Netlist-Power-Grid Simulation Flow While this flow has the advantage of simulating the netlist and the power-grid together so that there is a tight coupling between the simulations, integrated simulation has a high price in terms of capacity and solution performance. Simulating the transistor-level netlist alone can be overwhelming for most simulators. Simulating the power grid can also be overwhelming. Competing for the same resources limits the size of the design that you can consider. Capacity and performance limitations make this flow best suited to block analysis. Because many IR drop problems are due to block interactions at the full-chip level, this approach can leave you stranded when you need it most.
  34. 34. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 34 Product Version 10.1 Decoupled Netlist-Power-Grid Simulation Figure 2-5 on page 34 shows the high-level flow for decoupled analysis. Figure 2-5 Decoupled Netlist-Power-Grid Simulation Flow This flow has the advantage of maximizing the capacity of each component of the system, yielding a much higher capacity than integrated analysis. In addition, this flow has greater flexibility than integrated methods for computing or importing tap current information. On the other hand, this flow does not instantly evaluate the impact of IR drop on netlist simulation. Fortunately, this feedback is not required to solve the real problem in power-grid analysis—finding weak spots in the power grid. Therefore, VoltageStorm is designed in accordance with the flow shown in Figure 2-5 on page 34. Feedback is required if your objective is to perform an accurate simulation of the netlist in the presence of IR drop. This feedback is provided by VoltageStorm, but it is especially important in ClockStorm, the clock analysis tool. This feedback is not required for finding power-grid problems, because the objective of finding weak spots in the power grid is achieved in the first pass from netlist analysis to power-grid analysis. This first pass finds worst-case (conservative) IR drops. The feedback only serves to refine the accuracy of netlist analysis. The impact is small when the IR drop is small. The
  35. 35. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 35 Product Version 10.1 feedback from power-grid analysis to netlist analysis does not improve VoltageStorm’ ability to find power-grid problems. The timing at which dynamic problems arise may change slightly, but the problems are still present in the power grid. Tap Currents in Decoupled Analysis The interface between netlist analysis and power-grid analysis in Figure 2-5 on page 34 is implemented by using tap currents. In most cases, each tap current is a transistor current, but it could be from a variety of elements. This decoupled interface permits a wide variety of methodologies to be applied, depending on how tap currents are computed, represented, or imported from other sources. As you will learn in “Advanced Power-Grid Analysis Methodologies” on page 52, VoltageStorm can accept different tap current files computed from netlist analysis of different blocks and effectively merge the data into a full-chip power- grid analysis. What Are Tap Currents? Tap currents are currents arising from the connection of transistors to the power grid. Figure 2-6 on page 35 shows a typical netlist analysis view of transistors connected to a power grid. Figure 2-6 Transistor Simulation Model of Transistors on the Power Grid Netlist analysis treats the power grid—in this case, VDD—as an ideal wire, that is, a wire with no resistance. The netlist analysis tool analyzes the entire transistor netlist. It monitors the currents in the VDD wire originating from each individual transistor—M1, M2, and so forth. It then passes the monitored transistor currents to the power-grid analysis, as shown in Figure 2-7 on page 36. If the netlist has 1 million transistors connected to the VDD wire, data for 1 million transistors is passed to the power-grid analysis. M1 M2 VDD
  36. 36. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 36 Product Version 10.1 Figure 2-7 Modeling of Transistors on the Power Grid Power-grid analysis includes no information about any transistors other than those connected to the specific power grid being analyzed. In a typical digital design, one third of the total number of transistors is connected to VDD, one third is connected to VSS, and the rest are connected to internal nodes in logic gates. Because the primary elements in common between netlist analysis and power-grid analysis are the transistors connected to the power grid, those transistor names—for example, M1—are used as the identification for passing data from one tool to the other. Power-grid analysis models transistor currents as current sources attached to the power grid. The tap current data file provides the details for each current source. Tap current files can be static, where only a single current value is provided for each transistor, or dynamic, where a sequence of data points is provided for each transistor. These currents are used to perform either a simple steady-state analysis or a dynamic analysis of the power grid. How Does VoltageStorm Compute Tap Currents? Transistors have four terminals: drain (D), gate (G), source (S), and bulk (B). A typical p-type representation is shown in Figure 2-8 on page 37. M1 M2 VDD grid
  37. 37. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 37 Product Version 10.1 Figure 2-8 Transistor Currents on VDD The dominant current in a transistor is IDS, the current flowing into the drain through the transistor and out the source. In a p-type transistor, this current is typically negative. A number of other currents are present in transistor operation as well. In power-grid analysis, you are interested not only in IDS but also in the total currents flowing from and to the power grid: IS and IB. The total power current is the sum of these currents over all transistors: The negative sign in the equation is a sign convention on element currents. ■ IS is the sum of several currents in the transistor: IS = -IDS + ICSG + ISB. IS is normally positive but can be negative under certain operating conditions. ❑ ICSG is the current charging the transistor capacitance, CSG. ❑ ISB is the junction current (including capacitive) between the source and the bulk. ICSG might be significant in transient analysis, but ISB is negligible compared to IDS and ICSG. ■ IB is also the sum of several currents: IB = -ISB -IDB + ICBG. IB is several orders of magnitude less than the peak IS current. ❑ ICBG is the current charging the transistor capacitance, CBG. ❑ ISB and IDB are junction currents. IB contributes to the total power dissipation for chips over a million transistors in size, but it is not a primary cause of IR drop. In addition, the bulk current flows into either a well or the substrate of the chip and therefore usually introduces its load to the power grid in a location away from the transistor. For these reasons, VoltageStorm considers only IS in power-grid analysis, although it also computes IB during netlist simulation. + -B D G S VDD IB IDS IS IVDD VVDD IVDD IS IB+( )∑–= Transistors
  38. 38. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 38 Product Version 10.1 Validation of VoltageStorm Currents If you want to validate currents computed in Thunder, the netlist analysis tool used in VoltageStorm, you must remember that Thunder passes IS currents to power-grid analysis but also includes IB currents in IVDD reports. If you want the sum of the IS currents to match IVDD, you can modify the netlist to connect all transistor bulk nodes to a voltage source other than VDD, as illustrated in Figure 2-9 on page 38. In this case, a new power source called VDD2 is created, and a simple edit of the transistor cards in the netlist completes the modification. The resulting netlist is suitable for validating currents by using tools such as HSPICE. Figure 2-9 Removing Transistor Bulk Currents from VDD Static and Dynamic Power-Grid Analysis This section compares static and dynamic analysis in VoltageStorm and shows you how static analysis can find problems in the power grid. When used effectively and interpreted properly, static analysis in VoltageStorm can find even data-dependent power-grid problems. Static Analysis You perform static power-grid analysis when the analysis of a power grid is based on steady- state current modeling of the tap currents. It is easiest to view these currents as average current for each transistor obtained over a long simulation run. If you simulate your chip with thousands of test vectors and track the average current through each transistor connected to VDD, you obtain a long-term average behavior of the VDD distribution network in power-grid analysis. This method is an excellent qualitative analysis of the power grid for IR drop and the best way to perform electromigration analysis. The challenge in static power-grid analysis is obtaining sufficiently representative tap currents in minimal processing time. An important lesson learned through experience is that + - + - B D G S VVDD VDD VDD2 VVDD2 IS IB
  39. 39. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 39 Product Version 10.1 meaningful results are obtained in static analysis, even if the currents applied are not precise. The goal of static power-grid analysis is to find weak spots in the power distribution network, not necessarily to compute the exact IR drop to the nearest millivolt. The most common significant power-grid problems stand out in static analysis, even if the tap currents applied are rough guesses of actual average currents. Knowing the chip well reduces the probability of missing problems. But you do not need to know how the chip operates; in many cases, you may actually learn the behavior of the chip’s power grid from the power-grid analysis. To illustrate, consider a chip in which one row of cells is only connected on one end when it should be connected on both. The result is that the IR drop at one end of the row is much larger than in all other rows in the chip. Even if the total power distribution of the chip is unknown, a specific row standing out above the others is a strong indication of a weak spot. As another example, consider a set of drivers of a long bus, all powered from a specific location on the power grid. In this case, an IR drop failure may be data dependent. However, in static power-grid analysis, each driver is modeled by a larger current because of either the larger loading on the driver or the larger transistors in the driver. These larger currents in static analysis highlight the weak spot without requiring you to simulate the specific vector to activate all drivers at once. You can still find problems without performing a significant amount of simulation. VoltageStorm enables you to provide current scaling information to static analysis when you have it or when it is easily derived from the circuit. For example, memory cells have substantially lower activity levels than other circuitry. Mechanisms are therefore available to make sure these regions have very low average current values. These mechanisms are discussed in Chapter 4, “Using VoltageStorm.” Static analysis is the standard method used to perform electromigration analysis on power grids, because power grids generally have unidirectional current flow, and electromigration is a function of average current. Electromigration analysis prohibits the application of power-grid reduction in extraction. Reduction techniques mathematically remove the physical characteristics of wires. This physical data is an input requirement for electromigration analysis. Average currents assume equal amounts of rising and falling transitions on nets, so you can ignore currents due to Miller capacitances in transistors. These currents are considered, however, in dynamic analysis. The most significant advantage of static power-grid analysis is that the requirements for extraction and netlist analysis are much lower, so you can rapidly perform static power-grid analysis. As a result, many design methodologies today require a chip to pass static power- grid analysis before tapeout, a process called power-grid signoff (PGS). You can apply more extensive dynamic analysis while waiting for the chip to return if your schedule does not
  40. 40. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 40 Product Version 10.1 permit it before tapeout. Cadence recommends that you always begin with static analysis before proceeding to dynamic analysis. Dynamic Analysis Dynamic power-grid analysis uses simulation vectors to stimulate your chip to obtain a finer resolution of your chip’s behavior. While static analysis is quite effective in finding weak spots in the power grid, you may want to go to the next level of depth in analyzing your grid. Dynamic analysis helps differentiate between false warnings caused by the temporal variation of currents. If the weak spots identified in static analysis do not have an obvious power-grid implementation cause, dynamic analysis can help you understand your chip’s behavior better. A difference that static analysis cannot distinguish is shown in Figure 2-10 on page 40 and Figure 2-11 on page 41. Figure 2-10 Synchronized Transistor Currents Transistor current Time Clock cycle M1 M2 M3 M4 M5 M6 0
  41. 41. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 41 Product Version 10.1 Figure 2-11 Asynchronized Transistor Currents Each figure shows current waveforms for transistors M1-M6 over a clock cycle. Each transistor has the same current pulse. The difference between Figure 2-10 on page 40 and Figure 2-11 on page 41 is in the timing of the pulses. In Figure 2-10 on page 40, all pulses occur at once, and in Figure 2-11 on page 41, they are spread out over the clock cycle. Both sets of current waveforms yield the same average currents for all transistors. Depending on the specific characteristics of your chip design, the case shown in Figure 2-10 on page 40 could yield a false pass in static analysis but show excessive IR drop in dynamic analysis. You are likely to use dynamic analysis for one or more of four specific purposes: ■ To simulate a specific test vector ■ To identify which specific test vector activated an implementation weakness ■ To examine the time correlation of tap currents ■ To obtain a better estimate of the realistic magnitude of IR drop Time Clock cycle 0 Transistor current M1 M2 M3 M4 M5 M6
  42. 42. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 42 Product Version 10.1 The simulation of a specific test vector is common in memory design to test power-grid behavior under specific corner cases. It is also used when worst-case IR drop test vectors are known before analysis. Simulation to identify which specific test vector activates a weakness is useful when you cannot change your power grid, but you can change your power profile by changing the vectors using microcode. Examining time correlation of tap currents is a valuable check to avoid the static averaging issue just discussed. A better estimate of the magnitude of IR drop is used when the cost of fixing a weak spot is high and you want a more precise analysis before making the decision to fix the problem or not. Note: Cadence recommends that you always begin with static analysis before proceeding to dynamic analysis—it can be a fast path to finding problems. In addition, if you have little experience with power-grid analysis, static analysis is the better platform for learning the value that can be obtained from power-grid analysis. Dynamic power-grid analysis is a type of transient analysis. Transient analysis assumes the application of automatic time-step control. However, performing full-chip netlist and power- grid analysis requires many resources. Automatic time-step control tends to create time steps too small for practical use in power-grid analysis. It is used in netlist analysis, but not in power- grid analysis. You can manually control the step size used in power-grid analysis by setting parameters in the command files. Static Power-Grid Analysis Methodologies You can perform static power-grid analysis in a variety of ways. The way that you choose depends on the amount of information that you have about the operation of your design and the amount of time that you are willing to take. This section introduces the types of data that may be required in static analysis and surveys several basic methodologies. Advanced methodologies are discussed in “Advanced Power-Grid Analysis Methodologies” on page 52. Minimum Static Power-Grid Requirements Static power-grid analysis requires a minimum of three pieces of information: a netlist of your chip, transistor modeling information, and a power grid of your chip. It is assumed that you know the name of the power wires extracted from your chip. These are often labeled VDD and VSS, but if you use different names, substitute VDD and VSS for those names in the discussion here. Your chip netlist must be a transistor netlist. Chapter 3, “Preparing to Use VoltageStorm,” shows you how to obtain this netlist from Fire & Ice, a Cadence extraction product. See Appendix B, “Preparing to Use VoltageStorm Using QRC” for a flow using QRC rather than Fire & Ice. The QRC interface provides the ability to model small geometries (90nm, 65 nm ...) accurately. To create a complete input circuit netlist for VoltageStorm, combine the transistor netlist with voltage source definitions for at least VDD and VSS. If you do not identify
  43. 43. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 43 Product Version 10.1 the power supplies, the tap current data cannot be created. You must define additional voltage sources if your chip has additional power inputs. In addition to the voltage sources, you must include data for transistor modeling in the circuit netlist. You should also create voltage sources for the signal inputs to your chip in the circuit netlist. Do not define them as DC sources; it is best to define them as piecewise linear input sources with a single initial voltage. If you are going to apply vector-based simulation, the data in the vector file overrides the piecewise linear data. For static power-grid analysis, the power grid extracted from the chip must only contain resistances. In steady-state analysis, inductances and capacitances are treated as shorts and opens, respectively, so extraction time is reduced by extracting only resistances for the power grids being analyzed. If you intend to analyze both VDD and VSS, extract them individually; do not extract both into a single power-grid database. It is assumed that you know where the power pins are located on the power grid. Voltage sources are defined in the power-grid analysis tool at these locations. A different voltage source is defined for each pad and can include a series resistance and inductance. Different sources are used because each has different behavior resulting from the characteristics of the power grid in operation. As mentioned earlier, the passing of tap current data from netlist analysis to power-grid analysis uses transistor names as the identification. It is therefore critical that transistor names be consistent between the netlist and the power grid. If the netlist is extracted from the same extractor that extracts the power grid, the correlation should already be in place. For minimal power-grid analysis, neither net names nor transistor names need to match any schematic that you may have. Schematic net names are only required if you supply activity data or vectors. Accura Static Analysis Technology One of the challenges in static power-grid analysis is to obtain an estimate of the distribution of the power consumption in the chip. The Accura static analysis technology is a new approach based on transistor sizes and activity rates that uses circuit recognition, analysis techniques, and any additional information available to estimate the distribution of power consumption in the chip. The techniques applied in Accura are proprietary, but they use various forms of data to derive the distribution of power consumption of the chip. The input to Accura requires a default chip frequency and the following optional information: ■ Specific clock inputs and the clock frequency. This information is used to trace the clock domains in the design. Any portion of the design not assigned to a specific domain is assigned the default chip frequency. The gates on the clock distribution network are
  44. 44. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 44 Product Version 10.1 modeled as operating at the specified clock frequency. Accura derives an activity rate for logic not on the clock tree but in the clock domain. ■ Specific activity rates or frequencies of specific nets in the design. This information is used to set known activity rates of specific nets in the design. It is propagated forward and backward, considering the logic functionality to improve estimations of activity rates of nearby logic. ■ Power consumption of specific blocks in the design. When the actual power consumption of a specific block is known, this number is used to automatically scale the distribution of currents in the block so that the total estimate power consumption of the block is as specified. ■ Power consumption of the entire design. Once various portions of the design are processed to estimate their power distribution, this value is used to scale the currents in the design to the specified level. The information provided guides the Accura technology in estimating the power consumption of the gates in the design. Accura’s output is a distribution of currents for the transistors in the design. It is a good prediction of power distribution in the design; however, it should not be used for power consumption analysis. Static Power-Grid Analysis Using Maximum Saturation Currents This high-level flow is shown in Figure 2-5 on page 34. It is the fastest way to observe power- grid behavior. No capacitance or vectors are required, so the turnaround time is that of connectivity and resistance extraction. To use this flow, you should have an estimate of total power dissipation of the design in the form of average current. Additional information about block power consumption also improves the quality of the analysis. A simple command computes the peak saturation current, IDS, for each transistor connected to the power grid, where IS in Figure 2-8 on page 37 is -IDS. This current is placed in the tap current file. Of course, parameters to scale the VGS and VDS voltages are applied to compute the saturation current, as well as a variable to scale the resulting current. In addition, certain transistor configurations result in no IDS current because transistors with shorted source and drain or gates turned off have no current. As mentioned earlier, although saturation currents may seem to be an inaccurate method for deriving average currents, they have been quite successful in finding weaknesses in power grids. Scaling saturation currents by 0.01 for digital logic is a good approximation of averaging the transistor current. Because you can perform this scaling in either netlist analysis or power- grid analysis, there is no harm in generating the tap currents without scaling. In addition, power-grid analysis permits additional scaling by geometric region, so you can scale
  45. 45. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 45 Product Version 10.1 memories further in power-grid analysis. If you know the specific power dissipation of your blocks or chip, you can scale the currents accordingly. Static Power-Grid Analysis Using Net Activity Data The flow for static power-grid analysis using net activity data is illustrated in Figure 2-12 on page 45. Use this flow when the gate-level simulator reports relative gate activities that you want to use in static analysis. The clock is defined as having an activity ratio of 1.0. This data is used in conjunction with net capacitance, VDD voltage, and chip frequency (F) to derive the average currents of transistors connected to the power grid. Figure 2-12 Static Power-Grid Analysis Using Net Activity Data Given these parameters, the average current consumed by a gate is derived from the following equation: where A is the activity ratio of the gate, and CGATE is the total capacitance of the nets in the gate, including loading. IAVG A CGATE× VDD× F×=
  46. 46. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 46 Product Version 10.1 This equation for average current is derived simply by considering the charge, Q, required to charge the outputs of the gate in a clock cycle interval (1/AF). If a gate has multiple transistors connected to VDD, the average current is split evenly among the transistors. This derivation of average current is not a function of transistor size. Computing tap current on the basis of activity introduces two additional requirements for extraction: parasitic capacitances must now be computed for signal nets, and backannotation of net names is required. Static Power-Grid Analysis Using Vector-Based Netlist Analysis You can also derive average transistor currents by performing vector-based simulation in netlist analysis, as shown in Figure 2-13 on page 46. Use this flow when you want to obtain more accurate average power-grid currents by using the transistor-level simulation of several vectors. This approach is most commonly used at the block level for electromigration analysis. You can tally the average currents at the same time as dynamic analysis, as described in “Basic Dynamic Power-Grid Analysis Methodologies” on page 47. Figure 2-13 Static Power-Grid Analysis Using Average Currents Tallied in Vector Netlist Analysis
  47. 47. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 47 Product Version 10.1 VoltageStorm accepts VCD input vectors as well as several other formats. It performs simulation over the vectors provided and tracks the tap currents. It tracks average, peak, and RMS currents at once and reports them in three separate tap current files. Each type of tap current data provides a different perspective of simulation behavior, allowing you to select which form best suits your needs. Computing the average tap current on the basis of vector simulation introduces one additional requirement for extraction: parasitic capacitances should now be computed for signal nets. If the vector input signals are not labeled in the GDSII input, you must backannotate signal names to the netlist in the extraction portion of the flow. Basic Dynamic Power-Grid Analysis Methodologies Dynamic analysis is the next step up in complexity from static analysis using vector-based analysis. The flow diagram in Figure 2-14 on page 48 shows its similarity to vector-based static analysis. The difference appears to be only in the tap currents, but there are other differences. Use this flow when you want to introduce the time variation of currents into your analysis, as discussed in “Dynamic Analysis” on page 40. Rather than averaging currents, this flow enables you to see the finer time variation of currents over a clock cycle.
  48. 48. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 48 Product Version 10.1 Figure 2-14 Dynamic Power-Grid Analysis The challenge in dynamic power-grid analysis is to find the weaknesses in the power grid by using the minimal amount of computation time. To this end, dynamic analysis also includes capabilities for a form of vector compression in the creation of the dynamic tap current data. The vector compression is intended to create an effective worst-case IR drop test vector by merging the behavior of many vectors into a single equivalent. This process is further described in “Vector Compression” on page 49. Dynamic Power-Grid Analysis Requirements Dynamic power-grid analysis introduces two additional requirements for extraction beyond those of static analysis: parasitic capacitances must be computed for both signal nets and power nets, then merged into the power grid for analysis. In addition, if the vector input signals are not labeled in the GDSII input, you must backannotate signal names to the netlist in the extraction portion of the flow. Because dynamic analysis is applied to the power grid, VoltageStorm automatically accounts for a portion of the algorithm. Capacitance on the power grid is due to two sources: parasitic capacitances and transistor capacitances. Parasitic capacitances are provided in the extraction step. Transistor capacitances are automatically encoded in the dynamic tap current
  49. 49. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 49 Product Version 10.1 files. These transistor capacitances include transistors that implement decoupling capacitances, as shown in Figure 2-15 on page 49. Figure 2-15 Mapping of Decoupling Capacitances Dynamic Power-Grid Analysis The flow diagram in Figure 2-14 on page 48 shows the dynamic analysis flow. Power-grid analysis processes the dynamic current data as piecewise constant current sources. The step size is determined by the commands in the netlist analysis step. The recommended step size is about a single gate delay. Many designers use one tenth of the clock cycle as their step, so if your clock cycle is 10 ns, use 1 ns as your step size. If you intend to model pin inductance, a smaller step size is required, such as one twentieth of the clock cycle. Power-grid solutions are performed by constructing and solving matrix problems. The size of the matrix describing the resistive connectivity of a chip’s VDD can be very large. In a three- metal layer process, the number of resistors in VDD may be one to two times the number of transistors in the circuit. In a four- to five-metal layer process, the ratio increases to four to five. A 2-million-transistor chip normally has about 4 million resistors in VDD. An 8-million- transistor chip may have 50 million resistors in VDD. The matrix to solve in power-grid analysis is therefore very large. Cadence strongly recommends using vector compression, if possible, because the time to solve a large matrix for each of a large number of time points can be very long. Vector Compression The vector compression available in VoltageStorm is a complex process that was developed in conjunction with microprocessor designers to optimize the number of power-grid matrix solves required in full-chip dynamic analysis. If you simulate your chip for 100 vectors and select 10 steps per clock cycle in dynamic analysis, you will perform 1,000 solves of the power grid, which might not be practical. Vector compression reduces the number of solves to 10. Use it if your objective is to resolve the temporal issues of static analysis or to estimate the VDD VDD VSS VSS
  50. 50. VoltageStorm Transistor-Level Rail Analysis User Guide Issues in Power-Grid Analysis December 2010 50 Product Version 10.1 magnitude of worst-case IR drop more precisely. You should not use vector compression if your objective is to simulate a specific vector or to find the specific vector with the worst-case IR drop. Two concepts form the basis of vector compression. ■ First, dynamic analysis introduces time correlation to the analysis data. Chips are synchronous in their behavior, with the clock being the synchronization signal. Introducing temporal correlation in dynamic analysis splits activity occurring at different portions in the clock cycle rather than modeling the clock cycle as a single time-averaged value. The key is to improve resolution within a clock cycle, not across many clock cycles (vectors). For example, assume that you split a 10-ns clock cycle into 10 buckets of 1 ns each, B1- B10. B1 corresponds to the interval 0.0–1.0 ns into the clock cycle, B2 to the interval 1.0 ns–2.0 ns, and so on. If gate G1 can only switch in the time interval corresponding to bucket B2, in dynamic analysis the current value for gate G1 in buckets B1and B3–B10 should be 0.0 A in all clock cycles. The current value in bucket B2 may be 0.0 A in some clock cycles and non-zero in others. Figure 2-16 on page 50 illustrates the current for gate G1 over a clock cycle. Figure 2-16 Current Waveform in 10 Buckets of a Single Vector for Gate G1 Over 100 vectors, 1,000 total buckets correspond to gate G1. The 1,000 buckets correspond to 100 vectors and B1–B10 offsets into each vector. The following table shows the breakdown of sample average currents in gate G1 for each of the 1,000 buckets over 100 vectors. Vector B1 B2 B3 B4 B5 B6 ... B10 Gate G1 power current Clock cycle TimeB1 B2 B3 B4 B5 B6 B7 B8 B9 B10 G1

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